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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 27/45] target/arm: Implement SME integer outer product
Date: Mon, 11 Jul 2022 14:57:32 +0100
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From: Richard Henderson <richard.henderson@linaro.org>
This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-28-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper-sme.h | 16 ++++++++
target/arm/sme.decode | 10 +++++
target/arm/sme_helper.c | 82 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-sme.c | 10 +++++
4 files changed, 118 insertions(+)
diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
index 4d5d05db3a0..d2d544a6961 100644
--- a/target/arm/helper-sme.h
+++ b/target/arm/helper-sme.h
@@ -129,3 +129,19 @@ DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_smopa_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_umopa_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_sumopa_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_usmopa_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_smopa_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_umopa_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_sumopa_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_usmopa_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
index e8d27fd8a0e..628804e37a8 100644
--- a/target/arm/sme.decode
+++ b/target/arm/sme.decode
@@ -76,3 +76,13 @@ FMOPA_d 10000000 110 ..... ... ... ..... . 0 ...=
@op_64
=20
BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32
FMOPA_h 10000001 101 ..... ... ... ..... . 00 .. @op_32
+
+SMOPA_s 1010000 0 10 0 ..... ... ... ..... . 00 .. @op_32
+SUMOPA_s 1010000 0 10 1 ..... ... ... ..... . 00 .. @op_32
+USMOPA_s 1010000 1 10 0 ..... ... ... ..... . 00 .. @op_32
+UMOPA_s 1010000 1 10 1 ..... ... ... ..... . 00 .. @op_32
+
+SMOPA_d 1010000 0 11 0 ..... ... ... ..... . 0 ... @op_64
+SUMOPA_d 1010000 0 11 1 ..... ... ... ..... . 0 ... @op_64
+USMOPA_d 1010000 1 11 0 ..... ... ... ..... . 0 ... @op_64
+UMOPA_d 1010000 1 11 1 ..... ... ... ..... . 0 ... @op_64
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
index 302f89c30b3..f891306bb98 100644
--- a/target/arm/sme_helper.c
+++ b/target/arm/sme_helper.c
@@ -1117,3 +1117,85 @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *=
vzm, void *vpn,
} while (row & 15);
}
}
+
+typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool);
+
+static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm,
+ uint8_t *pn, uint8_t *pm,
+ uint32_t desc, IMOPFn *fn)
+{
+ intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8;
+ bool neg =3D simd_data(desc);
+
+ for (row =3D 0; row < oprsz; ++row) {
+ uint8_t pa =3D pn[H1(row)];
+ uint64_t *za_row =3D &za[tile_vslice_index(row)];
+ uint64_t n =3D zn[row];
+
+ for (col =3D 0; col < oprsz; ++col) {
+ uint8_t pb =3D pm[H1(col)];
+ uint64_t *a =3D &za_row[col];
+
+ *a =3D fn(n, zm[col], *a, pa & pb, neg);
+ }
+ }
+}
+
+#define DEF_IMOP_32(NAME, NTYPE, MTYPE) \
+static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool n=
eg) \
+{ =
\
+ uint32_t sum0 =3D 0, sum1 =3D 0; =
\
+ /* Apply P to N as a mask, making the inactive elements 0. */ =
\
+ n &=3D expand_pred_b(p); =
\
+ sum0 +=3D (NTYPE)(n >> 0) * (MTYPE)(m >> 0); =
\
+ sum0 +=3D (NTYPE)(n >> 8) * (MTYPE)(m >> 8); =
\
+ sum0 +=3D (NTYPE)(n >> 16) * (MTYPE)(m >> 16); =
\
+ sum0 +=3D (NTYPE)(n >> 24) * (MTYPE)(m >> 24); =
\
+ sum1 +=3D (NTYPE)(n >> 32) * (MTYPE)(m >> 32); =
\
+ sum1 +=3D (NTYPE)(n >> 40) * (MTYPE)(m >> 40); =
\
+ sum1 +=3D (NTYPE)(n >> 48) * (MTYPE)(m >> 48); =
\
+ sum1 +=3D (NTYPE)(n >> 56) * (MTYPE)(m >> 56); =
\
+ if (neg) { =
\
+ sum0 =3D (uint32_t)a - sum0, sum1 =3D (uint32_t)(a >> 32) - sum1; =
\
+ } else { =
\
+ sum0 =3D (uint32_t)a + sum0, sum1 =3D (uint32_t)(a >> 32) + sum1; =
\
+ } =
\
+ return ((uint64_t)sum1 << 32) | sum0; =
\
+}
+
+#define DEF_IMOP_64(NAME, NTYPE, MTYPE) \
+static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool n=
eg) \
+{ =
\
+ uint64_t sum =3D 0; =
\
+ /* Apply P to N as a mask, making the inactive elements 0. */ =
\
+ n &=3D expand_pred_h(p); =
\
+ sum +=3D (NTYPE)(n >> 0) * (MTYPE)(m >> 0); =
\
+ sum +=3D (NTYPE)(n >> 16) * (MTYPE)(m >> 16); =
\
+ sum +=3D (NTYPE)(n >> 32) * (MTYPE)(m >> 32); =
\
+ sum +=3D (NTYPE)(n >> 48) * (MTYPE)(m >> 48); =
\
+ return neg ? a - sum : a + sum; =
\
+}
+
+DEF_IMOP_32(smopa_s, int8_t, int8_t)
+DEF_IMOP_32(umopa_s, uint8_t, uint8_t)
+DEF_IMOP_32(sumopa_s, int8_t, uint8_t)
+DEF_IMOP_32(usmopa_s, uint8_t, int8_t)
+
+DEF_IMOP_64(smopa_d, int16_t, int16_t)
+DEF_IMOP_64(umopa_d, uint16_t, uint16_t)
+DEF_IMOP_64(sumopa_d, int16_t, uint16_t)
+DEF_IMOP_64(usmopa_d, uint16_t, int16_t)
+
+#define DEF_IMOPH(NAME) \
+ void HELPER(sme_##NAME)(void *vza, void *vzn, void *vzm, void *vpn, =
\
+ void *vpm, uint32_t desc) =
\
+ { do_imopa(vza, vzn, vzm, vpn, vpm, desc, NAME); }
+
+DEF_IMOPH(smopa_s)
+DEF_IMOPH(umopa_s)
+DEF_IMOPH(sumopa_s)
+DEF_IMOPH(usmopa_s)
+DEF_IMOPH(smopa_d)
+DEF_IMOPH(umopa_d)
+DEF_IMOPH(sumopa_d)
+DEF_IMOPH(usmopa_d)
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
index c2953b22ce3..7b87a9df63c 100644
--- a/target/arm/translate-sme.c
+++ b/target/arm/translate-sme.c
@@ -361,3 +361,13 @@ TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, =
a, MO_64, gen_helper_sme_f
=20
/* TODO: FEAT_EBF16 */
TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa)
+
+TRANS_FEAT(SMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_smopa_s)
+TRANS_FEAT(UMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_umopa_s)
+TRANS_FEAT(SUMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_sumopa=
_s)
+TRANS_FEAT(USMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_usmopa=
_s)
+
+TRANS_FEAT(SMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_=
smopa_d)
+TRANS_FEAT(UMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_=
umopa_d)
+TRANS_FEAT(SUMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme=
_sumopa_d)
+TRANS_FEAT(USMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme=
_usmopa_d)
--=20
2.25.1