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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 26/45] target/arm: Implement FMOPA, FMOPS (widening)
Date: Mon, 11 Jul 2022 14:57:31 +0100
Message-Id: <20220711135750.765803-27-peter.maydell@linaro.org>
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Content-Type: text/plain; charset="utf-8"
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-27-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper-sme.h | 2 ++
target/arm/sme.decode | 1 +
target/arm/sme_helper.c | 74 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-sme.c | 1 +
4 files changed, 78 insertions(+)
diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
index 1d68fb8c74f..4d5d05db3a0 100644
--- a/target/arm/helper-sme.h
+++ b/target/arm/helper-sme.h
@@ -121,6 +121,8 @@ DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, =
ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,=
i32)
DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,=
i32)
=20
+DEF_HELPER_FLAGS_7(sme_fmopa_h, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG,
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
index afd9c0dffda..e8d27fd8a0e 100644
--- a/target/arm/sme.decode
+++ b/target/arm/sme.decode
@@ -75,3 +75,4 @@ FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. =
@op_32
FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64
=20
BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32
+FMOPA_h 10000001 101 ..... ... ... ..... . 00 .. @op_32
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
index 690a53eee2d..302f89c30b3 100644
--- a/target/arm/sme_helper.c
+++ b/target/arm/sme_helper.c
@@ -1008,6 +1008,80 @@ static inline uint32_t f16mop_adj_pair(uint32_t pair=
, uint32_t pg, uint32_t neg)
return pair;
}
=20
+static float32 f16_dotadd(float32 sum, uint32_t e1, uint32_t e2,
+ float_status *s_std, float_status *s_odd)
+{
+ float64 e1r =3D float16_to_float64(e1 & 0xffff, true, s_std);
+ float64 e1c =3D float16_to_float64(e1 >> 16, true, s_std);
+ float64 e2r =3D float16_to_float64(e2 & 0xffff, true, s_std);
+ float64 e2c =3D float16_to_float64(e2 >> 16, true, s_std);
+ float64 t64;
+ float32 t32;
+
+ /*
+ * The ARM pseudocode function FPDot performs both multiplies
+ * and the add with a single rounding operation. Emulate this
+ * by performing the first multiply in round-to-odd, then doing
+ * the second multiply as fused multiply-add, and rounding to
+ * float32 all in one step.
+ */
+ t64 =3D float64_mul(e1r, e2r, s_odd);
+ t64 =3D float64r32_muladd(e1c, e2c, t64, 0, s_std);
+
+ /* This conversion is exact, because we've already rounded. */
+ t32 =3D float64_to_float32(t64, s_std);
+
+ /* The final accumulation step is not fused. */
+ return float32_add(sum, t32, s_std);
+}
+
+void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn,
+ void *vpm, void *vst, uint32_t desc)
+{
+ intptr_t row, col, oprsz =3D simd_maxsz(desc);
+ uint32_t neg =3D simd_data(desc) * 0x80008000u;
+ uint16_t *pn =3D vpn, *pm =3D vpm;
+ float_status fpst_odd, fpst_std;
+
+ /*
+ * Make a copy of float_status because this operation does not
+ * update the cumulative fp exception status. It also produces
+ * default nans. Make a second copy with round-to-odd -- see above.
+ */
+ fpst_std =3D *(float_status *)vst;
+ set_default_nan_mode(true, &fpst_std);
+ fpst_odd =3D fpst_std;
+ set_float_rounding_mode(float_round_to_odd, &fpst_odd);
+
+ for (row =3D 0; row < oprsz; ) {
+ uint16_t prow =3D pn[H2(row >> 4)];
+ do {
+ void *vza_row =3D vza + tile_vslice_offset(row);
+ uint32_t n =3D *(uint32_t *)(vzn + H1_4(row));
+
+ n =3D f16mop_adj_pair(n, prow, neg);
+
+ for (col =3D 0; col < oprsz; ) {
+ uint16_t pcol =3D pm[H2(col >> 4)];
+ do {
+ if (prow & pcol & 0b0101) {
+ uint32_t *a =3D vza_row + H1_4(col);
+ uint32_t m =3D *(uint32_t *)(vzm + H1_4(col));
+
+ m =3D f16mop_adj_pair(m, pcol, 0);
+ *a =3D f16_dotadd(*a, n, m, &fpst_std, &fpst_odd);
+
+ col +=3D 4;
+ pcol >>=3D 4;
+ }
+ } while (col & 15);
+ }
+ row +=3D 4;
+ prow >>=3D 4;
+ } while (row & 15);
+ }
+}
+
void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn,
void *vpm, uint32_t desc)
{
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
index ecb7583c559..c2953b22ce3 100644
--- a/target/arm/translate-sme.c
+++ b/target/arm/translate-sme.c
@@ -355,6 +355,7 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a,=
MemOp esz,
return true;
}
=20
+TRANS_FEAT(FMOPA_h, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fm=
opa_h)
TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fm=
opa_s)
TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper=
_sme_fmopa_d)
=20
--=20
2.25.1