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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 25/45] target/arm: Implement BFMOPA, BFMOPS
Date: Mon, 11 Jul 2022 14:57:30 +0100
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From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-26-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper-sme.h | 2 ++
target/arm/sme.decode | 2 ++
target/arm/sme_helper.c | 56 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-sme.c | 30 ++++++++++++++++++++
4 files changed, 90 insertions(+)
diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
index f50d0fe1d62..1d68fb8c74f 100644
--- a/target/arm/helper-sme.h
+++ b/target/arm/helper-sme.h
@@ -125,3 +125,5 @@ DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
index ba4774d1746..afd9c0dffda 100644
--- a/target/arm/sme.decode
+++ b/target/arm/sme.decode
@@ -73,3 +73,5 @@ ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... =
@adda_64
=20
FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32
FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64
+
+BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
index 7dc76b6a1c3..690a53eee2d 100644
--- a/target/arm/sme_helper.c
+++ b/target/arm/sme_helper.c
@@ -987,3 +987,59 @@ void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *v=
zm, void *vpn,
}
}
}
+
+/*
+ * Alter PAIR as needed for controlling predicates being false,
+ * and for NEG on an enabled row element.
+ */
+static inline uint32_t f16mop_adj_pair(uint32_t pair, uint32_t pg, uint32_=
t neg)
+{
+ /*
+ * The pseudocode uses a conditional negate after the conditional zero.
+ * It is simpler here to unconditionally negate before conditional zer=
o.
+ */
+ pair ^=3D neg;
+ if (!(pg & 1)) {
+ pair &=3D 0xffff0000u;
+ }
+ if (!(pg & 4)) {
+ pair &=3D 0x0000ffffu;
+ }
+ return pair;
+}
+
+void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn,
+ void *vpm, uint32_t desc)
+{
+ intptr_t row, col, oprsz =3D simd_maxsz(desc);
+ uint32_t neg =3D simd_data(desc) * 0x80008000u;
+ uint16_t *pn =3D vpn, *pm =3D vpm;
+
+ for (row =3D 0; row < oprsz; ) {
+ uint16_t prow =3D pn[H2(row >> 4)];
+ do {
+ void *vza_row =3D vza + tile_vslice_offset(row);
+ uint32_t n =3D *(uint32_t *)(vzn + H1_4(row));
+
+ n =3D f16mop_adj_pair(n, prow, neg);
+
+ for (col =3D 0; col < oprsz; ) {
+ uint16_t pcol =3D pm[H2(col >> 4)];
+ do {
+ if (prow & pcol & 0b0101) {
+ uint32_t *a =3D vza_row + H1_4(col);
+ uint32_t m =3D *(uint32_t *)(vzm + H1_4(col));
+
+ m =3D f16mop_adj_pair(m, pcol, 0);
+ *a =3D bfdotadd(*a, n, m);
+
+ col +=3D 4;
+ pcol >>=3D 4;
+ }
+ } while (col & 15);
+ }
+ row +=3D 4;
+ prow >>=3D 4;
+ } while (row & 15);
+ }
+}
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
index fa8f343a7d6..ecb7583c559 100644
--- a/target/arm/translate-sme.c
+++ b/target/arm/translate-sme.c
@@ -299,6 +299,33 @@ TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_h=
elper_sme_addva_s)
TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add=
ha_d)
TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add=
va_d)
=20
+static bool do_outprod(DisasContext *s, arg_op *a, MemOp esz,
+ gen_helper_gvec_5 *fn)
+{
+ int svl =3D streaming_vec_reg_size(s);
+ uint32_t desc =3D simd_desc(svl, svl, a->sub);
+ TCGv_ptr za, zn, zm, pn, pm;
+
+ if (!sme_smza_enabled_check(s)) {
+ return true;
+ }
+
+ /* Sum XZR+zad to find ZAd. */
+ za =3D get_tile_rowcol(s, esz, 31, a->zad, false);
+ zn =3D vec_full_reg_ptr(s, a->zn);
+ zm =3D vec_full_reg_ptr(s, a->zm);
+ pn =3D pred_full_reg_ptr(s, a->pn);
+ pm =3D pred_full_reg_ptr(s, a->pm);
+
+ fn(za, zn, zm, pn, pm, tcg_constant_i32(desc));
+
+ tcg_temp_free_ptr(za);
+ tcg_temp_free_ptr(zn);
+ tcg_temp_free_ptr(pn);
+ tcg_temp_free_ptr(pm);
+ return true;
+}
+
static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz,
gen_helper_gvec_5_ptr *fn)
{
@@ -330,3 +357,6 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a,=
MemOp esz,
=20
TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fm=
opa_s)
TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper=
_sme_fmopa_d)
+
+/* TODO: FEAT_EBF16 */
+TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa)
--=20
2.25.1