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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 24/45] target/arm: Implement FMOPA, FMOPS (non-widening)
Date: Mon, 11 Jul 2022 14:57:29 +0100
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Content-Type: text/plain; charset="utf-8"
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-25-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper-sme.h | 5 +++
target/arm/sme.decode | 9 +++++
target/arm/sme_helper.c | 69 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-sme.c | 32 ++++++++++++++++++
4 files changed, 115 insertions(+)
diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
index 753e9e624cc..f50d0fe1d62 100644
--- a/target/arm/helper-sme.h
+++ b/target/arm/helper-sme.h
@@ -120,3 +120,8 @@ DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, =
ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,=
i32)
DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,=
i32)
DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,=
i32)
+
+DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
index 8cb6c4053c3..ba4774d1746 100644
--- a/target/arm/sme.decode
+++ b/target/arm/sme.decode
@@ -64,3 +64,12 @@ ADDHA_s 11000000 10 01000 0 ... ... ..... 000 ..=
@adda_32
ADDVA_s 11000000 10 01000 1 ... ... ..... 000 .. @adda_32
ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64
ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64
+
+### SME Outer Product
+
+&op zad zn zm pm pn sub:bool
+@op_32 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 .. zad:2 &op
+@op_64 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 . zad:3 &op
+
+FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32
+FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
index f1e924db748..7dc76b6a1c3 100644
--- a/target/arm/sme_helper.c
+++ b/target/arm/sme_helper.c
@@ -25,6 +25,7 @@
#include "exec/cpu_ldst.h"
#include "exec/exec-all.h"
#include "qemu/int128.h"
+#include "fpu/softfloat.h"
#include "vec_internal.h"
#include "sve_ldst_internal.h"
=20
@@ -918,3 +919,71 @@ void HELPER(sme_addva_d)(void *vzda, void *vzn, void *=
vpn,
}
}
}
+
+void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn,
+ void *vpm, void *vst, uint32_t desc)
+{
+ intptr_t row, col, oprsz =3D simd_maxsz(desc);
+ uint32_t neg =3D simd_data(desc) << 31;
+ uint16_t *pn =3D vpn, *pm =3D vpm;
+ float_status fpst;
+
+ /*
+ * Make a copy of float_status because this operation does not
+ * update the cumulative fp exception status. It also produces
+ * default nans.
+ */
+ fpst =3D *(float_status *)vst;
+ set_default_nan_mode(true, &fpst);
+
+ for (row =3D 0; row < oprsz; ) {
+ uint16_t pa =3D pn[H2(row >> 4)];
+ do {
+ if (pa & 1) {
+ void *vza_row =3D vza + tile_vslice_offset(row);
+ uint32_t n =3D *(uint32_t *)(vzn + H1_4(row)) ^ neg;
+
+ for (col =3D 0; col < oprsz; ) {
+ uint16_t pb =3D pm[H2(col >> 4)];
+ do {
+ if (pb & 1) {
+ uint32_t *a =3D vza_row + H1_4(col);
+ uint32_t *m =3D vzm + H1_4(col);
+ *a =3D float32_muladd(n, *m, *a, 0, vst);
+ }
+ col +=3D 4;
+ pb >>=3D 4;
+ } while (col & 15);
+ }
+ }
+ row +=3D 4;
+ pa >>=3D 4;
+ } while (row & 15);
+ }
+}
+
+void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn,
+ void *vpm, void *vst, uint32_t desc)
+{
+ intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8;
+ uint64_t neg =3D (uint64_t)simd_data(desc) << 63;
+ uint64_t *za =3D vza, *zn =3D vzn, *zm =3D vzm;
+ uint8_t *pn =3D vpn, *pm =3D vpm;
+ float_status fpst =3D *(float_status *)vst;
+
+ set_default_nan_mode(true, &fpst);
+
+ for (row =3D 0; row < oprsz; ++row) {
+ if (pn[H1(row)] & 1) {
+ uint64_t *za_row =3D &za[tile_vslice_index(row)];
+ uint64_t n =3D zn[row] ^ neg;
+
+ for (col =3D 0; col < oprsz; ++col) {
+ if (pm[H1(col)] & 1) {
+ uint64_t *a =3D &za_row[col];
+ *a =3D float64_muladd(n, zm[col], *a, 0, &fpst);
+ }
+ }
+ }
+ }
+}
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
index d3b9cdd5c4b..fa8f343a7d6 100644
--- a/target/arm/translate-sme.c
+++ b/target/arm/translate-sme.c
@@ -298,3 +298,35 @@ TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_h=
elper_sme_addha_s)
TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s)
TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add=
ha_d)
TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add=
va_d)
+
+static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz,
+ gen_helper_gvec_5_ptr *fn)
+{
+ int svl =3D streaming_vec_reg_size(s);
+ uint32_t desc =3D simd_desc(svl, svl, a->sub);
+ TCGv_ptr za, zn, zm, pn, pm, fpst;
+
+ if (!sme_smza_enabled_check(s)) {
+ return true;
+ }
+
+ /* Sum XZR+zad to find ZAd. */
+ za =3D get_tile_rowcol(s, esz, 31, a->zad, false);
+ zn =3D vec_full_reg_ptr(s, a->zn);
+ zm =3D vec_full_reg_ptr(s, a->zm);
+ pn =3D pred_full_reg_ptr(s, a->pn);
+ pm =3D pred_full_reg_ptr(s, a->pm);
+ fpst =3D fpstatus_ptr(FPST_FPCR);
+
+ fn(za, zn, zm, pn, pm, fpst, tcg_constant_i32(desc));
+
+ tcg_temp_free_ptr(za);
+ tcg_temp_free_ptr(zn);
+ tcg_temp_free_ptr(pn);
+ tcg_temp_free_ptr(pm);
+ tcg_temp_free_ptr(fpst);
+ return true;
+}
+
+TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fm=
opa_s)
+TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper=
_sme_fmopa_d)
--=20
2.25.1