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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 23/45] target/arm: Implement SME ADDHA, ADDVA
Date: Mon, 11 Jul 2022 14:57:28 +0100
Message-Id: <20220711135750.765803-24-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper-sme.h | 5 +++
target/arm/sme.decode | 11 +++++
target/arm/sme_helper.c | 90 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-sme.c | 31 +++++++++++++
4 files changed, 137 insertions(+)
diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
index 95f6e88bdd4..753e9e624cc 100644
--- a/target/arm/helper-sme.h
+++ b/target/arm/helper-sme.h
@@ -115,3 +115,8 @@ DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, v=
oid, env, ptr, ptr, tl, i
DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,=
tl, i32)
DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,=
tl, i32)
DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,=
tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,=
i32)
+DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,=
i32)
+DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,=
i32)
+DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,=
i32)
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
index f1ebd857a57..8cb6c4053c3 100644
--- a/target/arm/sme.decode
+++ b/target/arm/sme.decode
@@ -53,3 +53,14 @@ LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn=
:5 0 za_imm:4 \
=20
LDR 1110000 100 0 000000 .. 000 ..... 0 .... @ldstr
STR 1110000 100 1 000000 .. 000 ..... 0 .... @ldstr
+
+### SME Add Vector to Array
+
+&adda zad zn pm pn
+@adda_32 ........ .. ..... . pm:3 pn:3 zn:5 ... zad:2 &adda
+@adda_64 ........ .. ..... . pm:3 pn:3 zn:5 .. zad:3 &adda
+
+ADDHA_s 11000000 10 01000 0 ... ... ..... 000 .. @adda_32
+ADDVA_s 11000000 10 01000 1 ... ... ..... 000 .. @adda_32
+ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64
+ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
index 10fd1ed910d..f1e924db748 100644
--- a/target/arm/sme_helper.c
+++ b/target/arm/sme_helper.c
@@ -828,3 +828,93 @@ DO_ST(q, _be, MO_128)
DO_ST(q, _le, MO_128)
=20
#undef DO_ST
+
+void HELPER(sme_addha_s)(void *vzda, void *vzn, void *vpn,
+ void *vpm, uint32_t desc)
+{
+ intptr_t row, col, oprsz =3D simd_oprsz(desc) / 4;
+ uint64_t *pn =3D vpn, *pm =3D vpm;
+ uint32_t *zda =3D vzda, *zn =3D vzn;
+
+ for (row =3D 0; row < oprsz; ) {
+ uint64_t pa =3D pn[row >> 4];
+ do {
+ if (pa & 1) {
+ for (col =3D 0; col < oprsz; ) {
+ uint64_t pb =3D pm[col >> 4];
+ do {
+ if (pb & 1) {
+ zda[tile_vslice_index(row) + H4(col)] +=3D zn[=
H4(col)];
+ }
+ pb >>=3D 4;
+ } while (++col & 15);
+ }
+ }
+ pa >>=3D 4;
+ } while (++row & 15);
+ }
+}
+
+void HELPER(sme_addha_d)(void *vzda, void *vzn, void *vpn,
+ void *vpm, uint32_t desc)
+{
+ intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8;
+ uint8_t *pn =3D vpn, *pm =3D vpm;
+ uint64_t *zda =3D vzda, *zn =3D vzn;
+
+ for (row =3D 0; row < oprsz; ++row) {
+ if (pn[H1(row)] & 1) {
+ for (col =3D 0; col < oprsz; ++col) {
+ if (pm[H1(col)] & 1) {
+ zda[tile_vslice_index(row) + col] +=3D zn[col];
+ }
+ }
+ }
+ }
+}
+
+void HELPER(sme_addva_s)(void *vzda, void *vzn, void *vpn,
+ void *vpm, uint32_t desc)
+{
+ intptr_t row, col, oprsz =3D simd_oprsz(desc) / 4;
+ uint64_t *pn =3D vpn, *pm =3D vpm;
+ uint32_t *zda =3D vzda, *zn =3D vzn;
+
+ for (row =3D 0; row < oprsz; ) {
+ uint64_t pa =3D pn[row >> 4];
+ do {
+ if (pa & 1) {
+ uint32_t zn_row =3D zn[H4(row)];
+ for (col =3D 0; col < oprsz; ) {
+ uint64_t pb =3D pm[col >> 4];
+ do {
+ if (pb & 1) {
+ zda[tile_vslice_index(row) + H4(col)] +=3D zn_=
row;
+ }
+ pb >>=3D 4;
+ } while (++col & 15);
+ }
+ }
+ pa >>=3D 4;
+ } while (++row & 15);
+ }
+}
+
+void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn,
+ void *vpm, uint32_t desc)
+{
+ intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8;
+ uint8_t *pn =3D vpn, *pm =3D vpm;
+ uint64_t *zda =3D vzda, *zn =3D vzn;
+
+ for (row =3D 0; row < oprsz; ++row) {
+ if (pn[H1(row)] & 1) {
+ uint64_t zn_row =3D zn[row];
+ for (col =3D 0; col < oprsz; ++col) {
+ if (pm[H1(col)] & 1) {
+ zda[tile_vslice_index(row) + col] +=3D zn_row;
+ }
+ }
+ }
+ }
+}
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
index 35c26448125..d3b9cdd5c4b 100644
--- a/target/arm/translate-sme.c
+++ b/target/arm/translate-sme.c
@@ -267,3 +267,34 @@ static bool do_ldst_r(DisasContext *s, arg_ldstr *a, G=
enLdStR *fn)
=20
TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr)
TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str)
+
+static bool do_adda(DisasContext *s, arg_adda *a, MemOp esz,
+ gen_helper_gvec_4 *fn)
+{
+ int svl =3D streaming_vec_reg_size(s);
+ uint32_t desc =3D simd_desc(svl, svl, 0);
+ TCGv_ptr za, zn, pn, pm;
+
+ if (!sme_smza_enabled_check(s)) {
+ return true;
+ }
+
+ /* Sum XZR+zad to find ZAd. */
+ za =3D get_tile_rowcol(s, esz, 31, a->zad, false);
+ zn =3D vec_full_reg_ptr(s, a->zn);
+ pn =3D pred_full_reg_ptr(s, a->pn);
+ pm =3D pred_full_reg_ptr(s, a->pm);
+
+ fn(za, zn, pn, pm, tcg_constant_i32(desc));
+
+ tcg_temp_free_ptr(za);
+ tcg_temp_free_ptr(zn);
+ tcg_temp_free_ptr(pn);
+ tcg_temp_free_ptr(pm);
+ return true;
+}
+
+TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addha_s)
+TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s)
+TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add=
ha_d)
+TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add=
va_d)
--=20
2.25.1