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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 14/45] target/arm: Mark LD1RO as non-streaming
Date: Mon, 11 Jul 2022 14:57:19 +0100
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From: Richard Henderson <richard.henderson@linaro.org>
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/sme-fa64.decode | 3 ---
target/arm/translate-sve.c | 2 ++
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index 2b5432bf856..47708ccc8da 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -58,6 +58,3 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVT=
ZS
# --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register=
(unscaled imm)
# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register=
(register offset)
# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register=
(scaled imm)
-
-FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 3=
2 bytes (scalar+scalar)
-FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 3=
2 bytes (scalar+imm)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 5182ee4c068..96e934c1ea9 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -5062,6 +5062,7 @@ static bool trans_LD1RO_zprr(DisasContext *s, arg_rpr=
r_load *a)
if (a->rm =3D=3D 31) {
return false;
}
+ s->is_nonstreaming =3D true;
if (sve_access_check(s)) {
TCGv_i64 addr =3D new_tmp_a64(s);
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype));
@@ -5076,6 +5077,7 @@ static bool trans_LD1RO_zpri(DisasContext *s, arg_rpr=
i_load *a)
if (!dc_isar_feature(aa64_sve_f64mm, s)) {
return false;
}
+ s->is_nonstreaming =3D true;
if (sve_access_check(s)) {
TCGv_i64 addr =3D new_tmp_a64(s);
tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 32);
--=20
2.25.1