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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 11/45] target/arm: Mark gather/scatter load/store as
non-streaming
Date: Mon, 11 Jul 2022 14:57:16 +0100
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From: Richard Henderson <richard.henderson@linaro.org>
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/sme-fa64.decode | 9 ---------
target/arm/translate-sve.c | 6 ++++++
2 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index fe462d2ccce..1acc3ae0809 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -59,19 +59,10 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJC=
VTZS
# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register=
(register offset)
# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register=
(scaled imm)
=20
-FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT =
load (vector+scalar)
FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather pref=
etch (vector+imm)
FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather pref=
etch (scalar+vector)
-FAIL 1000 010- -01- ---- 1--- ---- ---- ---- # SVE 32-bit gather load=
(vector+imm)
-FAIL 1000 0100 0-0- ---- 0--- ---- ---- ---- # SVE 32-bit gather load=
byte (scalar+vector)
-FAIL 1000 0100 1--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load=
half (scalar+vector)
-FAIL 1000 0101 0--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load=
word (scalar+vector)
FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load=
(scalar+scalar)
FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load=
(scalar+imm)
FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 3=
2 bytes (scalar+scalar)
FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 3=
2 bytes (scalar+imm)
FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load=
/prefetch
-FAIL 1110 010- -00- ---- 001- ---- ---- ---- # SVE2 64-bit scatter NT=
store (vector+scalar)
-FAIL 1110 010- -10- ---- 001- ---- ---- ---- # SVE2 32-bit scatter NT=
store (vector+scalar)
-FAIL 1110 010- ---- ---- 1-0- ---- ---- ---- # SVE scatter store (sca=
lar+32-bit vector)
-FAIL 1110 010- ---- ---- 101- ---- ---- ---- # SVE scatter store (mis=
c)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index f8e07164748..b23c6aa0bfd 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -5669,6 +5669,7 @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1_z=
prz *a)
if (!dc_isar_feature(aa64_sve, s)) {
return false;
}
+ s->is_nonstreaming =3D true;
if (!sve_access_check(s)) {
return true;
}
@@ -5700,6 +5701,7 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_z=
piz *a)
if (!dc_isar_feature(aa64_sve, s)) {
return false;
}
+ s->is_nonstreaming =3D true;
if (!sve_access_check(s)) {
return true;
}
@@ -5734,6 +5736,7 @@ static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1=
_zprz *a)
if (!dc_isar_feature(aa64_sve2, s)) {
return false;
}
+ s->is_nonstreaming =3D true;
if (!sve_access_check(s)) {
return true;
}
@@ -5857,6 +5860,7 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_z=
prz *a)
if (!dc_isar_feature(aa64_sve, s)) {
return false;
}
+ s->is_nonstreaming =3D true;
if (!sve_access_check(s)) {
return true;
}
@@ -5887,6 +5891,7 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_z=
piz *a)
if (!dc_isar_feature(aa64_sve, s)) {
return false;
}
+ s->is_nonstreaming =3D true;
if (!sve_access_check(s)) {
return true;
}
@@ -5921,6 +5926,7 @@ static bool trans_STNT1_zprz(DisasContext *s, arg_ST1=
_zprz *a)
if (!dc_isar_feature(aa64_sve2, s)) {
return false;
}
+ s->is_nonstreaming =3D true;
if (!sve_access_check(s)) {
return true;
}
--=20
2.25.1