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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=petrot.fr; s=default; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-Id: Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: In-Reply-To:References:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=/PRLQ9cFPMi9YXZy4q8Y22urOLzvANNirfV2Lq3pfpg=; b=oohnpn5Ixl+rpoJgCNkwbCFHAK tkKhQHYw0MTiodm90AIjJLlq8b683l7S4jqFq48S/Qa99VZjqQ9LnqEzj+hPC7jYvdGs2/jd5CXq1 zY/Wz4yOCosZROTxNNoqSLoMjV50Mmsc527j4Sm1FUpT4fLCJwjjLwHFAUH9CiZRwkvg81fDrDjtA dmXE6H7LKndzno30knFIxi6u8CLyKlChmTcmJ32Svn5dT3E7GuACKDMZ87vmimIygP8lsE/hYJ1T0 pmO+apEvtX7twiarjzy4lSmfPcHpglzgvHsk6qU6owCOaJHzPTkBVT5g45DmhRn+rwOkzawVAD3H9 fx6gVkCg==; From: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, palmer@dabbelt.com, Alistair.Francis@wdc.com, bin.meng@windriver.com Cc: =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20P=C3=A9trot?= Subject: [PATCH v2] target/riscv: fix shifts shamt value for rv128c Date: Sun, 10 Jul 2022 13:04:51 +0200 Message-Id: <20220710110451.245567-1-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-AuthUser: frederic@petrot.fr Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: neutral client-ip=23.83.212.6; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=aye.elm.relay.mailchannels.net X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657451208554100001 For rv128c shifts, a shamt of 0 is a shamt of 64, while for rv32c/rv64c it stays 0 and is a hint instruction that does not change processor state. For rv128c right shifts, the 6-bit shamt is in addition sign extended to 7 bits. Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot Reviewed-by: Richard Henderson Reviewed-by: Weiwei Li --- target/riscv/insn16.decode | 7 ++++--- disas/riscv.c | 27 +++++++++++++++++++++------ target/riscv/translate.c | 20 ++++++++++++++++++-- 3 files changed, 43 insertions(+), 11 deletions(-) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 02c8f61b48..ccfe59f294 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -31,7 +31,8 @@ %imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=3Dex_shift_1 %imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=3Dex_shift_1 =20 -%shimm_6bit 12:1 2:5 !function=3Dex_rvc_shifti +%shlimm_6bit 12:1 2:5 !function=3Dex_rvc_shiftli +%shrimm_6bit 12:1 2:5 !function=3Dex_rvc_shiftri %uimm_6bit_lq 2:4 12:1 6:1 !function=3Dex_shift_4 %uimm_6bit_ld 2:3 12:1 5:2 !function=3Dex_shift_3 %uimm_6bit_lw 2:2 12:1 4:3 !function=3Dex_shift_2 @@ -82,9 +83,9 @@ @c_addi16sp ... . ..... ..... .. &i imm=3D%imm_addi16sp rs1=3D2 rd=3D2 =20 @c_shift ... . .. ... ..... .. \ - &shift rd=3D%rs1_3 rs1=3D%rs1_3 shamt=3D%shimm_6bit + &shift rd=3D%rs1_3 rs1=3D%rs1_3 shamt=3D%shrimm_6bit @c_shift2 ... . .. ... ..... .. \ - &shift rd=3D%rd rs1=3D%rd shamt=3D%shimm_6bit + &shift rd=3D%rd rs1=3D%rd shamt=3D%shlimm_6bit =20 @c_andi ... . .. ... ..... .. &i imm=3D%imm_ci rs1=3D%rs1_3 rd=3D%= rs1_3 =20 diff --git a/disas/riscv.c b/disas/riscv.c index 7af6afc8fa..489c2ae5e8 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -2402,10 +2402,25 @@ static int32_t operand_sbimm12(rv_inst inst) ((inst << 56) >> 63) << 11; } =20 -static uint32_t operand_cimmsh6(rv_inst inst) +static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa) { - return ((inst << 51) >> 63) << 5 | + int imm =3D ((inst << 51) >> 63) << 5 | (inst << 57) >> 59; + if (isa =3D=3D rv128) { + imm =3D imm ? imm : 64; + } + return imm; +} + +static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa) +{ + int imm =3D ((inst << 51) >> 63) << 5 | + (inst << 57) >> 59; + if (isa =3D=3D rv128) { + imm =3D imm | (imm & 32) << 1; + imm =3D imm ? imm : 64; + } + return imm; } =20 static int32_t operand_cimmi(rv_inst inst) @@ -2529,7 +2544,7 @@ static uint32_t operand_rnum(rv_inst inst) =20 /* decode operands */ =20 -static void decode_inst_operands(rv_decode *dec) +static void decode_inst_operands(rv_decode *dec, rv_isa isa) { rv_inst inst =3D dec->inst; dec->codec =3D opcode_data[dec->op].codec; @@ -2652,7 +2667,7 @@ static void decode_inst_operands(rv_decode *dec) case rv_codec_cb_sh6: dec->rd =3D dec->rs1 =3D operand_crs1rdq(inst) + 8; dec->rs2 =3D rv_ireg_zero; - dec->imm =3D operand_cimmsh6(inst); + dec->imm =3D operand_cimmshr6(inst, isa); break; case rv_codec_ci: dec->rd =3D dec->rs1 =3D operand_crs1rd(inst); @@ -2667,7 +2682,7 @@ static void decode_inst_operands(rv_decode *dec) case rv_codec_ci_sh6: dec->rd =3D dec->rs1 =3D operand_crs1rd(inst); dec->rs2 =3D rv_ireg_zero; - dec->imm =3D operand_cimmsh6(inst); + dec->imm =3D operand_cimmshl6(inst, isa); break; case rv_codec_ci_16sp: dec->rd =3D rv_ireg_sp; @@ -3193,7 +3208,7 @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, uin= t64_t pc, rv_inst inst) dec.pc =3D pc; dec.inst =3D inst; decode_inst_opcode(&dec, isa); - decode_inst_operands(&dec); + decode_inst_operands(&dec, isa); decode_inst_decompress(&dec, isa); decode_inst_lift_pseudo(&dec); format_inst(buf, buflen, 16, &dec); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 63b04e8a94..d7c82a9c81 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -705,10 +705,26 @@ static int ex_rvc_register(DisasContext *ctx, int reg) return 8 + reg; } =20 -static int ex_rvc_shifti(DisasContext *ctx, int imm) +static int ex_rvc_shiftli(DisasContext *ctx, int imm) { /* For RV128 a shamt of 0 means a shift by 64. */ - return imm ? imm : 64; + if (get_ol(ctx) =3D=3D MXL_RV128) { + imm =3D imm ? imm : 64; + } + return imm; +} + +static int ex_rvc_shiftri(DisasContext *ctx, int imm) +{ + /* + * For RV128 a shamt of 0 means a shift by 64, furthermore, for right + * shifts, the shamt is sign-extended. + */ + if (get_ol(ctx) =3D=3D MXL_RV128) { + imm =3D imm | (imm & 32) << 1; + imm =3D imm ? imm : 64; + } + return imm; } =20 /* Include the auto-generated decoder for 32 bit insn */ --=20 2.36.1