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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r16-20020a05600c35d000b003a0375c4f73sm29177618wmq.44.2022.07.07.05.27.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 05:27:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Oqi7W5KRLEM6TRklN2zjDGigMaQta7JS5duLjMmH+2A=; b=yQ043JkK+fzAG1iQ4K4cf3HZEd5CXrk2FR8jJBNBf+55LVzFu/XNJnztWG1GxDnxaP H7D6jDx1RBl5JGh4JxEle5Gi3NteQiKpJAPu7y1WjYsDsfmvzyuDiqwhICPiwjNCA7aE XtYQEi7ytTso5DNV2ZZ8l4uLcANhqahr9hcM6abVk4N3+5Zyjaa0Eax9RkCFcr44uSxj OzZOaPXCYPZ+B7VF12ihU+01z2qFGI9afn2WaaXNJQ0Ot4E5MswrHjoaUBTGuIkFCa9h ghmb3QNfGZeGVZmbtpVLZBcQh/uwsvzGzBUW6augSPEDSH2q2ePwv+OZLXRmDHIqktXY rB6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Oqi7W5KRLEM6TRklN2zjDGigMaQta7JS5duLjMmH+2A=; b=xdn3TIh+JjCIDa/FfSo+KTeAVp51FpcYw4ezJDrVQWvZH3kOheZ+x41oi1rhsS3aBk y6IipsNhYZKgk/CPbr+28+bal/qStnEPZ+G+X8eMgwSPgtMJtqaT3yLreFL2rnJWz989 ke2/4KFb0HNZd804SHQuBRhKegmtKS354r7r1rm6XuLHZbkP7nTQxbpXRwb6vbUXlXZc mpY3UGnn2AUmILT72sBScfauJWv2mV0vn3+f7vYVZl9/NcLK3QqwUweb3EVWXfHk8r87 l18cVQw+HAn5XxwNfP+oDEe0lKQrvz5Qj5MQeGn5/5GpedhhbizI04xgEjQaC0b3VRSS nDlw== X-Gm-Message-State: AJIora/7ILJoVmynIH1PJqdF72Rx7IXYLDiHVwN7vDQ1sN20WL2gsfFR QrYlm8WTPq/wu79XmtKGhSWMpRaixIChsA== X-Google-Smtp-Source: AGRyM1twkMeY283ewp/vSsSIzmvW2WPAO9kwi+kqQxckSrf9Qm5HBhq8Q/YJwqNIPMv0QxxVq55hVA== X-Received: by 2002:a05:600c:8a9:b0:3a0:3d78:21a4 with SMTP id l41-20020a05600c08a900b003a03d7821a4mr4167614wmp.112.1657196862406; Thu, 07 Jul 2022 05:27:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 5/9] target/arm: Move define_debug_regs() to debug_helper.c Date: Thu, 7 Jul 2022 13:27:30 +0100 Message-Id: <20220707122734.288929-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220707122734.288929-1-peter.maydell@linaro.org> References: <20220707122734.288929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657197908203100001 Content-Type: text/plain; charset="utf-8" The target/arm/helper.c file is very long and is a grabbag of all kinds of functionality. We have already a debug_helper.c which has code for implementing architectural debug. Move the code which defines the debug-related system registers out to this file also. This affects the define_debug_regs() function and the various functions and arrays which are used only by it. The functions raw_write() and arm_mdcr_el2_eff() and define_debug_regs() now need to be global rather than local to helper.c; everything else is pure code movement. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220630194116.3438513-3-peter.maydell@linaro.org --- target/arm/cpregs.h | 3 + target/arm/internals.h | 9 + target/arm/debug_helper.c | 525 +++++++++++++++++++++++++++++++++++++ target/arm/helper.c | 531 +------------------------------------- 4 files changed, 538 insertions(+), 530 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index d30758ee713..7e78c2c05c6 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -442,6 +442,9 @@ void arm_cp_write_ignore(CPUARMState *env, const ARMCPR= egInfo *ri, /* CPReadFn that can be used for read-as-zero behaviour */ uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); =20 +/* CPWriteFn that just writes the value to ri->fieldoffset */ +void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value); + /* * CPResetFn that does nothing, for use if no reset is required even * if fieldoffset is non zero. diff --git a/target/arm/internals.h b/target/arm/internals.h index c66f74a0db1..00e2e710f6c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1307,6 +1307,15 @@ int exception_target_el(CPUARMState *env); bool arm_singlestep_active(CPUARMState *env); bool arm_generate_debug_exceptions(CPUARMState *env); =20 +/* Add the cpreg definitions for debug related system registers */ +void define_debug_regs(ARMCPU *cpu); + +/* Effective value of MDCR_EL2 */ +static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env) +{ + return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0; +} + /* Powers of 2 for sve_vq_map et al. */ #define SVE_VQ_POW2_MAP \ ((1 << (1 - 1)) | (1 << (2 - 1)) | \ diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index b18a6bd3a23..9a78c1db966 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -6,8 +6,10 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "cpu.h" #include "internals.h" +#include "cpregs.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" =20 @@ -528,6 +530,529 @@ void HELPER(exception_swstep)(CPUARMState *env, uint3= 2_t syndrome) raise_exception_debug(env, EXCP_UDEF, syndrome); } =20 +/* + * Check for traps to "powerdown debug" registers, which are controlled + * by MDCR.TDOSA + */ +static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + int el =3D arm_current_el(env); + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + bool mdcr_el2_tdosa =3D (mdcr_el2 & MDCR_TDOSA) || (mdcr_el2 & MDCR_TD= E) || + (arm_hcr_el2_eff(env) & HCR_TGE); + + if (el < 2 && mdcr_el2_tdosa) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +/* + * Check for traps to "debug ROM" registers, which are controlled + * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. + */ +static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + bool mdcr_el2_tdra =3D (mdcr_el2 & MDCR_TDRA) || (mdcr_el2 & MDCR_TDE)= || + (arm_hcr_el2_eff(env) & HCR_TGE); + + if (el < 2 && mdcr_el2_tdra) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +/* + * Check for traps to general debug registers, which are controlled + * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. + */ +static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + bool mdcr_el2_tda =3D (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) || + (arm_hcr_el2_eff(env) & HCR_TGE); + + if (el < 2 && mdcr_el2_tda) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Writes to OSLAR_EL1 may update the OS lock status, which can be + * read via a bit in OSLSR_EL1. + */ + int oslock; + + if (ri->state =3D=3D ARM_CP_STATE_AA32) { + oslock =3D (value =3D=3D 0xC5ACCE55); + } else { + oslock =3D value & 1; + } + + env->cp15.oslsr_el1 =3D deposit32(env->cp15.oslsr_el1, 1, 1, oslock); +} + +static const ARMCPRegInfo debug_cp_reginfo[] =3D { + /* + * DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped + * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; + * unlike DBGDRAR it is never accessible from EL0. + * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AAr= ch64 + * accessor. + */ + { .name =3D "DBGDRAR", .cp =3D 14, .crn =3D 1, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, + .access =3D PL0_R, .accessfn =3D access_tdra, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "MDRAR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_R, .accessfn =3D access_tdra, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "DBGDSAR", .cp =3D 14, .crn =3D 2, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, + .access =3D PL0_R, .accessfn =3D access_tdra, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + /* Monitor debug system control register; the 32-bit alias is DBGDSCRe= xt. */ + { .name =3D "MDSCR_EL1", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 2, + .access =3D PL1_RW, .accessfn =3D access_tda, + .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), + .resetvalue =3D 0 }, + /* + * MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external + * Debug Communication Channel is not implemented. + */ + { .name =3D "MDCCSR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 2, .opc1 =3D 3, .crn =3D 0, .crm =3D 1, .opc2 =3D 0, + .access =3D PL0_R, .accessfn =3D access_tda, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + /* + * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as + * it is unlikely a guest will care. + * We don't implement the configurable EL0 access. + */ + { .name =3D "DBGDSCRint", .state =3D ARM_CP_STATE_AA32, + .cp =3D 14, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D 0, + .type =3D ARM_CP_ALIAS, + .access =3D PL1_R, .accessfn =3D access_tda, + .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), }, + { .name =3D "OSLAR_EL1", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 = =3D 4, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .accessfn =3D access_tdosa, + .writefn =3D oslar_write }, + { .name =3D "OSLSR_EL1", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 = =3D 4, + .access =3D PL1_R, .resetvalue =3D 10, + .accessfn =3D access_tdosa, + .fieldoffset =3D offsetof(CPUARMState, cp15.oslsr_el1) }, + /* Dummy OSDLR_EL1: 32-bit Linux will read this */ + { .name =3D "OSDLR_EL1", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 = =3D 4, + .access =3D PL1_RW, .accessfn =3D access_tdosa, + .type =3D ARM_CP_NOP }, + /* + * Dummy DBGVCR: Linux wants to clear this on startup, but we don't + * implement vector catch debug events yet. + */ + { .name =3D "DBGVCR", + .cp =3D 14, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tda, + .type =3D ARM_CP_NOP }, + /* + * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor + * to save and restore a 32-bit guest's DBGVCR) + */ + { .name =3D "DBGVCR32_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 2, .opc1 =3D 4, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, + .access =3D PL2_RW, .accessfn =3D access_tda, + .type =3D ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, + /* + * Dummy MDCCINT_EL1, since we don't implement the Debug Communications + * Channel but Linux may try to access this register. The 32-bit + * alias is DBGDCCINT. + */ + { .name =3D "MDCCINT_EL1", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tda, + .type =3D ARM_CP_NOP }, +}; + +static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D { + /* 64 bit access versions of the (dummy) debug registers */ + { .name =3D "DBGDRAR", .cp =3D 14, .crm =3D 1, .opc1 =3D 0, + .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalu= e =3D 0 }, + { .name =3D "DBGDSAR", .cp =3D 14, .crm =3D 2, .opc1 =3D 0, + .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalu= e =3D 0 }, +}; + +void hw_watchpoint_update(ARMCPU *cpu, int n) +{ + CPUARMState *env =3D &cpu->env; + vaddr len =3D 0; + vaddr wvr =3D env->cp15.dbgwvr[n]; + uint64_t wcr =3D env->cp15.dbgwcr[n]; + int mask; + int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; + + if (env->cpu_watchpoint[n]) { + cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); + env->cpu_watchpoint[n] =3D NULL; + } + + if (!FIELD_EX64(wcr, DBGWCR, E)) { + /* E bit clear : watchpoint disabled */ + return; + } + + switch (FIELD_EX64(wcr, DBGWCR, LSC)) { + case 0: + /* LSC 00 is reserved and must behave as if the wp is disabled */ + return; + case 1: + flags |=3D BP_MEM_READ; + break; + case 2: + flags |=3D BP_MEM_WRITE; + break; + case 3: + flags |=3D BP_MEM_ACCESS; + break; + } + + /* + * Attempts to use both MASK and BAS fields simultaneously are + * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, + * thus generating a watchpoint for every byte in the masked region. + */ + mask =3D FIELD_EX64(wcr, DBGWCR, MASK); + if (mask =3D=3D 1 || mask =3D=3D 2) { + /* + * Reserved values of MASK; we must act as if the mask value was + * some non-reserved value, or as if the watchpoint were disabled. + * We choose the latter. + */ + return; + } else if (mask) { + /* Watchpoint covers an aligned area up to 2GB in size */ + len =3D 1ULL << mask; + /* + * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTAB= LE + * whether the watchpoint fires when the unmasked bits match; we o= pt + * to generate the exceptions. + */ + wvr &=3D ~(len - 1); + } else { + /* Watchpoint covers bytes defined by the byte address select bits= */ + int bas =3D FIELD_EX64(wcr, DBGWCR, BAS); + int basstart; + + if (extract64(wvr, 2, 1)) { + /* + * Deprecated case of an only 4-aligned address. BAS[7:4] are + * ignored, and BAS[3:0] define which bytes to watch. + */ + bas &=3D 0xf; + } + + if (bas =3D=3D 0) { + /* This must act as if the watchpoint is disabled */ + return; + } + + /* + * The BAS bits are supposed to be programmed to indicate a contig= uous + * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE wheth= er + * we fire for each byte in the word/doubleword addressed by the W= VR. + * We choose to ignore any non-zero bits after the first range of = 1s. + */ + basstart =3D ctz32(bas); + len =3D cto32(bas >> basstart); + wvr +=3D basstart; + } + + cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, + &env->cpu_watchpoint[n]); +} + +void hw_watchpoint_update_all(ARMCPU *cpu) +{ + int i; + CPUARMState *env =3D &cpu->env; + + /* + * Completely clear out existing QEMU watchpoints and our array, to + * avoid possible stale entries following migration load. + */ + cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); + memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); + + for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { + hw_watchpoint_update(cpu, i); + } +} + +static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + int i =3D ri->crm; + + /* + * Bits [1:0] are RES0. + * + * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA) + * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if + * they contain the value written. It is CONSTRAINED UNPREDICTABLE + * whether the RESS bits are ignored when comparing an address. + * + * Therefore we are allowed to compare the entire register, which lets + * us avoid considering whether or not FEAT_LVA is actually enabled. + */ + value &=3D ~3ULL; + + raw_write(env, ri, value); + hw_watchpoint_update(cpu, i); +} + +static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + int i =3D ri->crm; + + raw_write(env, ri, value); + hw_watchpoint_update(cpu, i); +} + +void hw_breakpoint_update(ARMCPU *cpu, int n) +{ + CPUARMState *env =3D &cpu->env; + uint64_t bvr =3D env->cp15.dbgbvr[n]; + uint64_t bcr =3D env->cp15.dbgbcr[n]; + vaddr addr; + int bt; + int flags =3D BP_CPU; + + if (env->cpu_breakpoint[n]) { + cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); + env->cpu_breakpoint[n] =3D NULL; + } + + if (!extract64(bcr, 0, 1)) { + /* E bit clear : watchpoint disabled */ + return; + } + + bt =3D extract64(bcr, 20, 4); + + switch (bt) { + case 4: /* unlinked address mismatch (reserved if AArch64) */ + case 5: /* linked address mismatch (reserved if AArch64) */ + qemu_log_mask(LOG_UNIMP, + "arm: address mismatch breakpoint types not implemen= ted\n"); + return; + case 0: /* unlinked address match */ + case 1: /* linked address match */ + { + /* + * Bits [1:0] are RES0. + * + * It is IMPLEMENTATION DEFINED whether bits [63:49] + * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit + * of the VA field ([48] or [52] for FEAT_LVA), or whether the + * value is read as written. It is CONSTRAINED UNPREDICTABLE + * whether the RESS bits are ignored when comparing an address. + * Therefore we are allowed to compare the entire register, which + * lets us avoid considering whether FEAT_LVA is actually enabled. + * + * The BAS field is used to allow setting breakpoints on 16-bit + * wide instructions; it is CONSTRAINED UNPREDICTABLE whether + * a bp will fire if the addresses covered by the bp and the addre= sses + * covered by the insn overlap but the insn doesn't start at the + * start of the bp address range. We choose to require the insn and + * the bp to have the same address. The constraints on writing to + * BAS enforced in dbgbcr_write mean we have only four cases: + * 0b0000 =3D> no breakpoint + * 0b0011 =3D> breakpoint on addr + * 0b1100 =3D> breakpoint on addr + 2 + * 0b1111 =3D> breakpoint on addr + * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). + */ + int bas =3D extract64(bcr, 5, 4); + addr =3D bvr & ~3ULL; + if (bas =3D=3D 0) { + return; + } + if (bas =3D=3D 0xc) { + addr +=3D 2; + } + break; + } + case 2: /* unlinked context ID match */ + case 8: /* unlinked VMID match (reserved if no EL2) */ + case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ + qemu_log_mask(LOG_UNIMP, + "arm: unlinked context breakpoint types not implemen= ted\n"); + return; + case 9: /* linked VMID match (reserved if no EL2) */ + case 11: /* linked context ID and VMID match (reserved if no EL2) */ + case 3: /* linked context ID match */ + default: + /* + * We must generate no events for Linked context matches (unless + * they are linked to by some other bp/wp, which is handled in + * updates for the linking bp/wp). We choose to also generate no e= vents + * for reserved values. + */ + return; + } + + cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); +} + +void hw_breakpoint_update_all(ARMCPU *cpu) +{ + int i; + CPUARMState *env =3D &cpu->env; + + /* + * Completely clear out existing QEMU breakpoints and our array, to + * avoid possible stale entries following migration load. + */ + cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); + memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); + + for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { + hw_breakpoint_update(cpu, i); + } +} + +static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + int i =3D ri->crm; + + raw_write(env, ri, value); + hw_breakpoint_update(cpu, i); +} + +static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + int i =3D ri->crm; + + /* + * BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only + * copy of BAS[0]. + */ + value =3D deposit64(value, 6, 1, extract64(value, 5, 1)); + value =3D deposit64(value, 8, 1, extract64(value, 7, 1)); + + raw_write(env, ri, value); + hw_breakpoint_update(cpu, i); +} + +void define_debug_regs(ARMCPU *cpu) +{ + /* + * Define v7 and v8 architectural debug registers. + * These are just dummy implementations for now. + */ + int i; + int wrps, brps, ctx_cmps; + + /* + * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot + * use AArch32. Given that bit 15 is RES1, if the value is 0 then + * the register must not exist for this cpu. + */ + if (cpu->isar.dbgdidr !=3D 0) { + ARMCPRegInfo dbgdidr =3D { + .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, + .opc1 =3D 0, .opc2 =3D 0, + .access =3D PL0_R, .accessfn =3D access_tda, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->isar.dbgdidr, + }; + define_one_arm_cp_reg(cpu, &dbgdidr); + } + + brps =3D arm_num_brps(cpu); + wrps =3D arm_num_wrps(cpu); + ctx_cmps =3D arm_num_ctx_cmps(cpu); + + assert(ctx_cmps <=3D brps); + + define_arm_cp_regs(cpu, debug_cp_reginfo); + + if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { + define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); + } + + for (i =3D 0; i < brps; i++) { + char *dbgbvr_el1_name =3D g_strdup_printf("DBGBVR%d_EL1", i); + char *dbgbcr_el1_name =3D g_strdup_printf("DBGBCR%d_EL1", i); + ARMCPRegInfo dbgregs[] =3D { + { .name =3D dbgbvr_el1_name, .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 4, + .access =3D PL1_RW, .accessfn =3D access_tda, + .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbvr[i]), + .writefn =3D dbgbvr_write, .raw_writefn =3D raw_write + }, + { .name =3D dbgbcr_el1_name, .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 5, + .access =3D PL1_RW, .accessfn =3D access_tda, + .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbcr[i]), + .writefn =3D dbgbcr_write, .raw_writefn =3D raw_write + }, + }; + define_arm_cp_regs(cpu, dbgregs); + g_free(dbgbvr_el1_name); + g_free(dbgbcr_el1_name); + } + + for (i =3D 0; i < wrps; i++) { + char *dbgwvr_el1_name =3D g_strdup_printf("DBGWVR%d_EL1", i); + char *dbgwcr_el1_name =3D g_strdup_printf("DBGWCR%d_EL1", i); + ARMCPRegInfo dbgregs[] =3D { + { .name =3D dbgwvr_el1_name, .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 6, + .access =3D PL1_RW, .accessfn =3D access_tda, + .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwvr[i]), + .writefn =3D dbgwvr_write, .raw_writefn =3D raw_write + }, + { .name =3D dbgwcr_el1_name, .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 7, + .access =3D PL1_RW, .accessfn =3D access_tda, + .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwcr[i]), + .writefn =3D dbgwcr_write, .raw_writefn =3D raw_write + }, + }; + define_arm_cp_regs(cpu, dbgregs); + g_free(dbgwvr_el1_name); + g_free(dbgwcr_el1_name); + } +} + #if !defined(CONFIG_USER_ONLY) =20 vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1c7ec2f8678..e6f37e160f8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -51,8 +51,7 @@ static uint64_t raw_read(CPUARMState *env, const ARMCPReg= Info *ri) } } =20 -static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { assert(ri->fieldoffset); if (cpreg_field_is_64bit(ri)) { @@ -302,74 +301,6 @@ static CPAccessResult access_trap_aa32s_el1(CPUARMStat= e *env, return CP_ACCESS_TRAP_UNCATEGORIZED; } =20 -static uint64_t arm_mdcr_el2_eff(CPUARMState *env) -{ - return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0; -} - -/* - * Check for traps to "powerdown debug" registers, which are controlled - * by MDCR.TDOSA - */ -static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *r= i, - bool isread) -{ - int el =3D arm_current_el(env); - uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); - bool mdcr_el2_tdosa =3D (mdcr_el2 & MDCR_TDOSA) || (mdcr_el2 & MDCR_TD= E) || - (arm_hcr_el2_eff(env) & HCR_TGE); - - if (el < 2 && mdcr_el2_tdosa) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_OK; -} - -/* - * Check for traps to "debug ROM" registers, which are controlled - * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. - */ -static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - int el =3D arm_current_el(env); - uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); - bool mdcr_el2_tdra =3D (mdcr_el2 & MDCR_TDRA) || (mdcr_el2 & MDCR_TDE)= || - (arm_hcr_el2_eff(env) & HCR_TGE); - - if (el < 2 && mdcr_el2_tdra) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_OK; -} - -/* - * Check for traps to general debug registers, which are controlled - * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. - */ -static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - int el =3D arm_current_el(env); - uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); - bool mdcr_el2_tda =3D (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) || - (arm_hcr_el2_eff(env) & HCR_TGE); - - if (el < 2 && mdcr_el2_tda) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_OK; -} - /* Check for traps to performance monitor registers, which are controlled * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. */ @@ -5982,116 +5913,6 @@ static CPAccessResult ctr_el0_access(CPUARMState *e= nv, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 -static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* - * Writes to OSLAR_EL1 may update the OS lock status, which can be - * read via a bit in OSLSR_EL1. - */ - int oslock; - - if (ri->state =3D=3D ARM_CP_STATE_AA32) { - oslock =3D (value =3D=3D 0xC5ACCE55); - } else { - oslock =3D value & 1; - } - - env->cp15.oslsr_el1 =3D deposit32(env->cp15.oslsr_el1, 1, 1, oslock); -} - -static const ARMCPRegInfo debug_cp_reginfo[] =3D { - /* - * DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped - * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; - * unlike DBGDRAR it is never accessible from EL0. - * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AAr= ch64 - * accessor. - */ - { .name =3D "DBGDRAR", .cp =3D 14, .crn =3D 1, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, - .access =3D PL0_R, .accessfn =3D access_tdra, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "MDRAR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_R, .accessfn =3D access_tdra, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "DBGDSAR", .cp =3D 14, .crn =3D 2, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, - .access =3D PL0_R, .accessfn =3D access_tdra, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* Monitor debug system control register; the 32-bit alias is DBGDSCRe= xt. */ - { .name =3D "MDSCR_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), - .resetvalue =3D 0 }, - /* - * MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external - * Debug Communication Channel is not implemented. - */ - { .name =3D "MDCCSR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 2, .opc1 =3D 3, .crn =3D 0, .crm =3D 1, .opc2 =3D 0, - .access =3D PL0_R, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* - * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as - * it is unlikely a guest will care. - * We don't implement the configurable EL0 access. - */ - { .name =3D "DBGDSCRint", .state =3D ARM_CP_STATE_AA32, - .cp =3D 14, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D 0, - .type =3D ARM_CP_ALIAS, - .access =3D PL1_R, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), }, - { .name =3D "OSLAR_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 = =3D 4, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .accessfn =3D access_tdosa, - .writefn =3D oslar_write }, - { .name =3D "OSLSR_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 = =3D 4, - .access =3D PL1_R, .resetvalue =3D 10, - .accessfn =3D access_tdosa, - .fieldoffset =3D offsetof(CPUARMState, cp15.oslsr_el1) }, - /* Dummy OSDLR_EL1: 32-bit Linux will read this */ - { .name =3D "OSDLR_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 = =3D 4, - .access =3D PL1_RW, .accessfn =3D access_tdosa, - .type =3D ARM_CP_NOP }, - /* - * Dummy DBGVCR: Linux wants to clear this on startup, but we don't - * implement vector catch debug events yet. - */ - { .name =3D "DBGVCR", - .cp =3D 14, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_NOP }, - /* - * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor - * to save and restore a 32-bit guest's DBGVCR) - */ - { .name =3D "DBGVCR32_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 2, .opc1 =3D 4, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, - .access =3D PL2_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, - /* - * Dummy MDCCINT_EL1, since we don't implement the Debug Communications - * Channel but Linux may try to access this register. The 32-bit - * alias is DBGDCCINT. - */ - { .name =3D "MDCCINT_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_NOP }, -}; - -static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D { - /* 64 bit access versions of the (dummy) debug registers */ - { .name =3D "DBGDRAR", .cp =3D 14, .crm =3D 1, .opc1 =3D 0, - .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalu= e =3D 0 }, - { .name =3D "DBGDSAR", .cp =3D 14, .crm =3D 2, .opc1 =3D 0, - .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalu= e =3D 0 }, -}; - /* * Check for traps to RAS registers, which are controlled * by HCR_EL2.TERR and SCR_EL3.TERR. @@ -6470,356 +6291,6 @@ static const ARMCPRegInfo sme_reginfo[] =3D { }; #endif /* TARGET_AARCH64 */ =20 -void hw_watchpoint_update(ARMCPU *cpu, int n) -{ - CPUARMState *env =3D &cpu->env; - vaddr len =3D 0; - vaddr wvr =3D env->cp15.dbgwvr[n]; - uint64_t wcr =3D env->cp15.dbgwcr[n]; - int mask; - int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; - - if (env->cpu_watchpoint[n]) { - cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); - env->cpu_watchpoint[n] =3D NULL; - } - - if (!FIELD_EX64(wcr, DBGWCR, E)) { - /* E bit clear : watchpoint disabled */ - return; - } - - switch (FIELD_EX64(wcr, DBGWCR, LSC)) { - case 0: - /* LSC 00 is reserved and must behave as if the wp is disabled */ - return; - case 1: - flags |=3D BP_MEM_READ; - break; - case 2: - flags |=3D BP_MEM_WRITE; - break; - case 3: - flags |=3D BP_MEM_ACCESS; - break; - } - - /* - * Attempts to use both MASK and BAS fields simultaneously are - * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, - * thus generating a watchpoint for every byte in the masked region. - */ - mask =3D FIELD_EX64(wcr, DBGWCR, MASK); - if (mask =3D=3D 1 || mask =3D=3D 2) { - /* - * Reserved values of MASK; we must act as if the mask value was - * some non-reserved value, or as if the watchpoint were disabled. - * We choose the latter. - */ - return; - } else if (mask) { - /* Watchpoint covers an aligned area up to 2GB in size */ - len =3D 1ULL << mask; - /* - * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTAB= LE - * whether the watchpoint fires when the unmasked bits match; we o= pt - * to generate the exceptions. - */ - wvr &=3D ~(len - 1); - } else { - /* Watchpoint covers bytes defined by the byte address select bits= */ - int bas =3D FIELD_EX64(wcr, DBGWCR, BAS); - int basstart; - - if (extract64(wvr, 2, 1)) { - /* - * Deprecated case of an only 4-aligned address. BAS[7:4] are - * ignored, and BAS[3:0] define which bytes to watch. - */ - bas &=3D 0xf; - } - - if (bas =3D=3D 0) { - /* This must act as if the watchpoint is disabled */ - return; - } - - /* - * The BAS bits are supposed to be programmed to indicate a contig= uous - * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE wheth= er - * we fire for each byte in the word/doubleword addressed by the W= VR. - * We choose to ignore any non-zero bits after the first range of = 1s. - */ - basstart =3D ctz32(bas); - len =3D cto32(bas >> basstart); - wvr +=3D basstart; - } - - cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, - &env->cpu_watchpoint[n]); -} - -void hw_watchpoint_update_all(ARMCPU *cpu) -{ - int i; - CPUARMState *env =3D &cpu->env; - - /* - * Completely clear out existing QEMU watchpoints and our array, to - * avoid possible stale entries following migration load. - */ - cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); - memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); - - for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { - hw_watchpoint_update(cpu, i); - } -} - -static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - int i =3D ri->crm; - - /* - * Bits [1:0] are RES0. - * - * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA) - * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if - * they contain the value written. It is CONSTRAINED UNPREDICTABLE - * whether the RESS bits are ignored when comparing an address. - * - * Therefore we are allowed to compare the entire register, which lets - * us avoid considering whether or not FEAT_LVA is actually enabled. - */ - value &=3D ~3ULL; - - raw_write(env, ri, value); - hw_watchpoint_update(cpu, i); -} - -static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - int i =3D ri->crm; - - raw_write(env, ri, value); - hw_watchpoint_update(cpu, i); -} - -void hw_breakpoint_update(ARMCPU *cpu, int n) -{ - CPUARMState *env =3D &cpu->env; - uint64_t bvr =3D env->cp15.dbgbvr[n]; - uint64_t bcr =3D env->cp15.dbgbcr[n]; - vaddr addr; - int bt; - int flags =3D BP_CPU; - - if (env->cpu_breakpoint[n]) { - cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); - env->cpu_breakpoint[n] =3D NULL; - } - - if (!extract64(bcr, 0, 1)) { - /* E bit clear : watchpoint disabled */ - return; - } - - bt =3D extract64(bcr, 20, 4); - - switch (bt) { - case 4: /* unlinked address mismatch (reserved if AArch64) */ - case 5: /* linked address mismatch (reserved if AArch64) */ - qemu_log_mask(LOG_UNIMP, - "arm: address mismatch breakpoint types not implemen= ted\n"); - return; - case 0: /* unlinked address match */ - case 1: /* linked address match */ - { - /* - * Bits [1:0] are RES0. - * - * It is IMPLEMENTATION DEFINED whether bits [63:49] - * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit - * of the VA field ([48] or [52] for FEAT_LVA), or whether the - * value is read as written. It is CONSTRAINED UNPREDICTABLE - * whether the RESS bits are ignored when comparing an address. - * Therefore we are allowed to compare the entire register, which - * lets us avoid considering whether FEAT_LVA is actually enabled. - * - * The BAS field is used to allow setting breakpoints on 16-bit - * wide instructions; it is CONSTRAINED UNPREDICTABLE whether - * a bp will fire if the addresses covered by the bp and the addre= sses - * covered by the insn overlap but the insn doesn't start at the - * start of the bp address range. We choose to require the insn and - * the bp to have the same address. The constraints on writing to - * BAS enforced in dbgbcr_write mean we have only four cases: - * 0b0000 =3D> no breakpoint - * 0b0011 =3D> breakpoint on addr - * 0b1100 =3D> breakpoint on addr + 2 - * 0b1111 =3D> breakpoint on addr - * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). - */ - int bas =3D extract64(bcr, 5, 4); - addr =3D bvr & ~3ULL; - if (bas =3D=3D 0) { - return; - } - if (bas =3D=3D 0xc) { - addr +=3D 2; - } - break; - } - case 2: /* unlinked context ID match */ - case 8: /* unlinked VMID match (reserved if no EL2) */ - case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ - qemu_log_mask(LOG_UNIMP, - "arm: unlinked context breakpoint types not implemen= ted\n"); - return; - case 9: /* linked VMID match (reserved if no EL2) */ - case 11: /* linked context ID and VMID match (reserved if no EL2) */ - case 3: /* linked context ID match */ - default: - /* - * We must generate no events for Linked context matches (unless - * they are linked to by some other bp/wp, which is handled in - * updates for the linking bp/wp). We choose to also generate no e= vents - * for reserved values. - */ - return; - } - - cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); -} - -void hw_breakpoint_update_all(ARMCPU *cpu) -{ - int i; - CPUARMState *env =3D &cpu->env; - - /* - * Completely clear out existing QEMU breakpoints and our array, to - * avoid possible stale entries following migration load. - */ - cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); - memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); - - for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { - hw_breakpoint_update(cpu, i); - } -} - -static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - int i =3D ri->crm; - - raw_write(env, ri, value); - hw_breakpoint_update(cpu, i); -} - -static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - int i =3D ri->crm; - - /* - * BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only - * copy of BAS[0]. - */ - value =3D deposit64(value, 6, 1, extract64(value, 5, 1)); - value =3D deposit64(value, 8, 1, extract64(value, 7, 1)); - - raw_write(env, ri, value); - hw_breakpoint_update(cpu, i); -} - -static void define_debug_regs(ARMCPU *cpu) -{ - /* - * Define v7 and v8 architectural debug registers. - * These are just dummy implementations for now. - */ - int i; - int wrps, brps, ctx_cmps; - - /* - * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot - * use AArch32. Given that bit 15 is RES1, if the value is 0 then - * the register must not exist for this cpu. - */ - if (cpu->isar.dbgdidr !=3D 0) { - ARMCPRegInfo dbgdidr =3D { - .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, - .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL0_R, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->isar.dbgdidr, - }; - define_one_arm_cp_reg(cpu, &dbgdidr); - } - - brps =3D arm_num_brps(cpu); - wrps =3D arm_num_wrps(cpu); - ctx_cmps =3D arm_num_ctx_cmps(cpu); - - assert(ctx_cmps <=3D brps); - - define_arm_cp_regs(cpu, debug_cp_reginfo); - - if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { - define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); - } - - for (i =3D 0; i < brps; i++) { - char *dbgbvr_el1_name =3D g_strdup_printf("DBGBVR%d_EL1", i); - char *dbgbcr_el1_name =3D g_strdup_printf("DBGBCR%d_EL1", i); - ARMCPRegInfo dbgregs[] =3D { - { .name =3D dbgbvr_el1_name, .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 4, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbvr[i]), - .writefn =3D dbgbvr_write, .raw_writefn =3D raw_write - }, - { .name =3D dbgbcr_el1_name, .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 5, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbcr[i]), - .writefn =3D dbgbcr_write, .raw_writefn =3D raw_write - }, - }; - define_arm_cp_regs(cpu, dbgregs); - g_free(dbgbvr_el1_name); - g_free(dbgbcr_el1_name); - } - - for (i =3D 0; i < wrps; i++) { - char *dbgwvr_el1_name =3D g_strdup_printf("DBGWVR%d_EL1", i); - char *dbgwcr_el1_name =3D g_strdup_printf("DBGWCR%d_EL1", i); - ARMCPRegInfo dbgregs[] =3D { - { .name =3D dbgwvr_el1_name, .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 6, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwvr[i]), - .writefn =3D dbgwvr_write, .raw_writefn =3D raw_write - }, - { .name =3D dbgwcr_el1_name, .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 7, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwcr[i]), - .writefn =3D dbgwcr_write, .raw_writefn =3D raw_write - }, - }; - define_arm_cp_regs(cpu, dbgregs); - g_free(dbgwvr_el1_name); - g_free(dbgwcr_el1_name); - } -} - static void define_pmu_regs(ARMCPU *cpu) { /* --=20 2.25.1