From nobody Wed Feb 11 00:55:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1657099257; cv=none; d=zohomail.com; s=zohoarc; b=Aw/7DjvlgJ39P8JnkDcpghBrvxCP6i0/26KCYnkaizGbQ+ncpJwtNUXzqjk9MS7UhIRTZQpGFuggCYJ7HW0gIL8WYAudSJ8B+I38jffKLlPgeVKvwNQfFFAir9YgPOEavjY5UPZYuePsmjX49tB+Z4g55y+z6S3q/7S2kbSsVaI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1657099257; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xDxZQB7t7jC7e11iBt04ewldeYznmzQBar7IyZiGr2c=; b=Xz73vv7eZtthbFGW8tU09TgifQcLUGrI+3hn133vYrGtvQzSmgelv8QukItTLmIuHOUx5CM8ZPd8+9UkRTojjJ9trSE/+xd9msgBQyKQ5HbWqiSRjNWT7g7BpZYx3mfsnLEeOCf3vFixQFS48eG1B9uZysRGK/P/SnQLwYQ6IT4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657099257075943.7290716893244; Wed, 6 Jul 2022 02:20:57 -0700 (PDT) Received: from localhost ([::1]:52986 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o91DL-0006rF-1T for importer@patchew.org; Wed, 06 Jul 2022 05:20:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o90Lv-0006eb-PP for qemu-devel@nongnu.org; Wed, 06 Jul 2022 04:25:43 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:46596) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o90Lt-0000lS-Ry for qemu-devel@nongnu.org; Wed, 06 Jul 2022 04:25:43 -0400 Received: by mail-pg1-x52a.google.com with SMTP id s27so13418884pga.13 for ; Wed, 06 Jul 2022 01:25:40 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id t17-20020a170902e85100b00162529828aesm25199256plg.109.2022.07.06.01.25.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 01:25:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xDxZQB7t7jC7e11iBt04ewldeYznmzQBar7IyZiGr2c=; b=mHQ9B5S9w/+Xzi1hEengo43Rb2BSCsX5SiYQ6kmJG/RvtwFGtZf0KwhJ+HaVXip03P nSrQbThHbZFdqh52wII+7Y5cDSpvmuPqDgkdf6IeCqY2izLPAgy3pK2sY2npB35BQS3e MEi7Ix7OXNE7H3GyWaBb5m8ov/6nC//f41rcgcX6zWp1yLQwIWCg6cQufPOiprfL2RG9 gUdQZk15Rr3JOW7mausVauS2bxNUvy5foDAQAzbCjr8YjeYzF2I+WKSBCaNLqTlCm+y4 JA1xgPtEsj1sKSt4wTd9NfgQHsjrfhBOnyeUUw6y/nDO+rJEt8KM+yoU+/NnNbCBAfRj zesQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xDxZQB7t7jC7e11iBt04ewldeYznmzQBar7IyZiGr2c=; b=LiYsOMi6gOcOy/LXZ/znvPO79ctVZQFO3NP0EbroHneuPKTHbFSonf9pU/WZGdP9mb crhgS1STc3Zv6vmIKmUfowEbXh9df+BRzCd/VBXUYPDrVnxMLsxrl2Y9cXE5zvh5wXRP tsirHfqIMGxvXci0uGI/WTjEjk2sOajP1ruGaq1DcCNhPMbqIvCoqizulyTr3JcxS/LI Piq8suld2LzDOwSxyyZyyZYm7ueU7uESiewfoCpHcyi3/wp1mlE10/ww0xKk2gcNYCNI 7zrSSaY5zUNSZ5JRzdevGPKtgKPiC0+GQnN3GV9mRLn/iwmlr7EJbnV7WeP+CX9/El0e aSRQ== X-Gm-Message-State: AJIora+RUX52JiCgeKqa47tm2i1WY0NISm6eVWn+Y/2OcfHgNqMrIiVL p3BUcwRz6GvciLGOtDh6nOUcydcULWAbMAq0 X-Google-Smtp-Source: AGRyM1vQwaWID7Qp3Mcoo6wAddY1hxCYfvRD+k/m0q20rPxMVhP3hRjZ7GSaT3J+OU8eqnMCk3idBA== X-Received: by 2002:a63:d315:0:b0:411:bbff:efbc with SMTP id b21-20020a63d315000000b00411bbffefbcmr26256340pgg.342.1657095939972; Wed, 06 Jul 2022 01:25:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v5 30/45] target/arm: Implement SCLAMP, UCLAMP Date: Wed, 6 Jul 2022 13:53:56 +0530 Message-Id: <20220706082411.1664825-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220706082411.1664825-1-richard.henderson@linaro.org> References: <20220706082411.1664825-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1657099258097100003 Content-Type: text/plain; charset="utf-8" This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h | 18 +++++++ target/arm/sve.decode | 5 ++ target/arm/translate-sve.c | 102 +++++++++++++++++++++++++++++++++++++ target/arm/vec_helper.c | 24 +++++++++ 4 files changed, 149 insertions(+) diff --git a/target/arm/helper.h b/target/arm/helper.h index 3a8ce42ab0..92f36d9dbb 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1019,6 +1019,24 @@ DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_uclamp_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a9e48f07b4..14b3a69c36 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1695,3 +1695,8 @@ PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0= .... \ @psel esz=3D2 imm=3D%psel_imm_s PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ @psel esz=3D3 imm=3D%psel_imm_d + +### SVE clamp + +SCLAMP 01000100 .. 0 ..... 110000 ..... ..... @rda_rn_rm +UCLAMP 01000100 .. 0 ..... 110001 ..... ..... @rda_rn_rm diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 9ed3b267fd..41f8b12259 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7478,3 +7478,105 @@ static bool trans_PSEL(DisasContext *s, arg_psel *a) tcg_temp_free_ptr(ptr); return true; } + +static void gen_sclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a) +{ + tcg_gen_smax_i32(d, a, n); + tcg_gen_smin_i32(d, d, m); +} + +static void gen_sclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a) +{ + tcg_gen_smax_i64(d, a, n); + tcg_gen_smin_i64(d, d, m); +} + +static void gen_sclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n, + TCGv_vec m, TCGv_vec a) +{ + tcg_gen_smax_vec(vece, d, a, n); + tcg_gen_smin_vec(vece, d, d, m); +} + +static void gen_sclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m, + uint32_t a, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop[] =3D { + INDEX_op_smin_vec, INDEX_op_smax_vec, 0 + }; + static const GVecGen4 ops[4] =3D { + { .fniv =3D gen_sclamp_vec, + .fno =3D gen_helper_gvec_sclamp_b, + .opt_opc =3D vecop, + .vece =3D MO_8 }, + { .fniv =3D gen_sclamp_vec, + .fno =3D gen_helper_gvec_sclamp_h, + .opt_opc =3D vecop, + .vece =3D MO_16 }, + { .fni4 =3D gen_sclamp_i32, + .fniv =3D gen_sclamp_vec, + .fno =3D gen_helper_gvec_sclamp_s, + .opt_opc =3D vecop, + .vece =3D MO_32 }, + { .fni8 =3D gen_sclamp_i64, + .fniv =3D gen_sclamp_vec, + .fno =3D gen_helper_gvec_sclamp_d, + .opt_opc =3D vecop, + .vece =3D MO_64, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64 } + }; + tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]); +} + +TRANS_FEAT(SCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_sclamp, a) + +static void gen_uclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a) +{ + tcg_gen_umax_i32(d, a, n); + tcg_gen_umin_i32(d, d, m); +} + +static void gen_uclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a) +{ + tcg_gen_umax_i64(d, a, n); + tcg_gen_umin_i64(d, d, m); +} + +static void gen_uclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n, + TCGv_vec m, TCGv_vec a) +{ + tcg_gen_umax_vec(vece, d, a, n); + tcg_gen_umin_vec(vece, d, d, m); +} + +static void gen_uclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m, + uint32_t a, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop[] =3D { + INDEX_op_umin_vec, INDEX_op_umax_vec, 0 + }; + static const GVecGen4 ops[4] =3D { + { .fniv =3D gen_uclamp_vec, + .fno =3D gen_helper_gvec_uclamp_b, + .opt_opc =3D vecop, + .vece =3D MO_8 }, + { .fniv =3D gen_uclamp_vec, + .fno =3D gen_helper_gvec_uclamp_h, + .opt_opc =3D vecop, + .vece =3D MO_16 }, + { .fni4 =3D gen_uclamp_i32, + .fniv =3D gen_uclamp_vec, + .fno =3D gen_helper_gvec_uclamp_s, + .opt_opc =3D vecop, + .vece =3D MO_32 }, + { .fni8 =3D gen_uclamp_i64, + .fniv =3D gen_uclamp_vec, + .fno =3D gen_helper_gvec_uclamp_d, + .opt_opc =3D vecop, + .vece =3D MO_64, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64 } + }; + tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]); +} + +TRANS_FEAT(UCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_uclamp, a) diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 9a9c034e36..f59d3b26ea 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -2690,3 +2690,27 @@ void HELPER(gvec_bfmlal_idx)(void *vd, void *vn, voi= d *vm, } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +#define DO_CLAMP(NAME, TYPE) \ +void HELPER(NAME)(void *d, void *n, void *m, void *a, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc); \ + for (i =3D 0; i < opr_sz; i +=3D sizeof(TYPE)) { = \ + TYPE aa =3D *(TYPE *)(a + i); \ + TYPE nn =3D *(TYPE *)(n + i); \ + TYPE mm =3D *(TYPE *)(m + i); \ + TYPE dd =3D MIN(MAX(aa, nn), mm); \ + *(TYPE *)(d + i) =3D dd; \ + } \ + clear_tail(d, opr_sz, simd_maxsz(desc)); \ +} + +DO_CLAMP(gvec_sclamp_b, int8_t) +DO_CLAMP(gvec_sclamp_h, int16_t) +DO_CLAMP(gvec_sclamp_s, int32_t) +DO_CLAMP(gvec_sclamp_d, int64_t) + +DO_CLAMP(gvec_uclamp_b, uint8_t) +DO_CLAMP(gvec_uclamp_h, uint16_t) +DO_CLAMP(gvec_uclamp_s, uint32_t) +DO_CLAMP(gvec_uclamp_d, uint64_t) --=20 2.34.1