From nobody Mon Feb 9 18:54:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657004082856294.07380009304165; Mon, 4 Jul 2022 23:54:42 -0700 (PDT) Received: from localhost ([::1]:42108 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o8cSG-0007WU-Kq for importer@patchew.org; Tue, 05 Jul 2022 02:54:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45802) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o8cN6-0002En-Pc for qemu-devel@nongnu.org; Tue, 05 Jul 2022 02:49:20 -0400 Received: from mail.loongson.cn ([114.242.206.163]:56862 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o8cN1-00056P-Au for qemu-devel@nongnu.org; Tue, 05 Jul 2022 02:49:20 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax+eDd3sNi_PcJAA--.31000S3; Tue, 05 Jul 2022 14:49:02 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, maobibo@loongson.cn, mark.cave-ayland@ilande.co.uk, mst@redhat.com, imammedo@redhat.com, ani@anisinha.ca, f4bug@amsat.org, peter.maydell@linaro.org Subject: [PATCH 1/2] hw/intc/loongarch_ipi: Fix ipi device access of 64bits Date: Tue, 5 Jul 2022 14:49:00 +0800 Message-Id: <20220705064901.2353349-2-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220705064901.2353349-1-yangxiaojuan@loongson.cn> References: <20220705064901.2353349-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf9Ax+eDd3sNi_PcJAA--.31000S3 X-Coremail-Antispam: 1UD129KBjvJXoWxAw47GFy8tF1Utw4fJw15twb_yoWrWFWDpr y7uFy5Wr48AFnrXr93KasrXFn8Jwn7GFy29anIkay09F47XryjvF1SyryDXFyUA3sxGF90 qrykWFW7W3WUZwUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657004084843100001 Content-Type: text/plain; charset="utf-8" In general loongarch ipi device, 32bit registers is emulated, however for anysend/mailsend device only 64bit register access is supported. So separate the ipi memory region into two regions, including 32 bits and 64 bits. Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson --- hw/intc/loongarch_ipi.c | 38 +++++++++++++++++++++++++++------ hw/loongarch/loongson3.c | 5 ++++- include/hw/intc/loongarch_ipi.h | 7 +++--- 3 files changed, 39 insertions(+), 11 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 66bee93675..b8b1b9cd53 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -150,12 +150,6 @@ static void loongarch_ipi_writel(void *opaque, hwaddr = addr, uint64_t val, case IOCSR_IPI_SEND: ipi_send(val); break; - case IOCSR_MAIL_SEND: - mail_send(val); - break; - case IOCSR_ANY_SEND: - any_send(val); - break; default: qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); break; @@ -172,6 +166,32 @@ static const MemoryRegionOps loongarch_ipi_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 +/* mail send and any send only support writeq */ +static void loongarch_ipi_writeq(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + addr &=3D 0xfff; + switch (addr) { + case MAIL_SEND_OFFSET: + mail_send(val); + break; + case ANY_SEND_OFFSET: + any_send(val); + break; + default: + break; + } +} + +static const MemoryRegionOps loongarch_ipi64_ops =3D { + .write =3D loongarch_ipi_writeq, + .impl.min_access_size =3D 8, + .impl.max_access_size =3D 8, + .valid.min_access_size =3D 8, + .valid.max_access_size =3D 8, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + static void loongarch_ipi_init(Object *obj) { int cpu; @@ -187,8 +207,12 @@ static void loongarch_ipi_init(Object *obj) lams =3D LOONGARCH_MACHINE(machine); for (cpu =3D 0; cpu < MAX_IPI_CORE_NUM; cpu++) { memory_region_init_io(&s->ipi_iocsr_mem[cpu], obj, &loongarch_ipi_= ops, - &lams->ipi_core[cpu], "loongarch_ipi_iocsr", 0= x100); + &lams->ipi_core[cpu], "loongarch_ipi_iocsr", 0= x48); sysbus_init_mmio(sbd, &s->ipi_iocsr_mem[cpu]); + + memory_region_init_io(&s->ipi64_iocsr_mem[cpu], obj, &loongarch_ip= i64_ops, + &lams->ipi_core[cpu], "loongarch_ipi64_iocsr= ", 0x118); + sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem[cpu]); qdev_init_gpio_out(DEVICE(obj), &lams->ipi_core[cpu].irq, 1); } } diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c index a0cd61cc88..d14ec06d02 100644 --- a/hw/loongarch/loongson3.c +++ b/hw/loongarch/loongson3.c @@ -453,7 +453,10 @@ static void loongarch_irq_init(LoongArchMachineState *= lams) /* IPI iocsr memory region */ memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX, sysbus_mmio_get_region(SYS_BUS_DEVICE(= ipi), - cpu)); + cpu * 2)); + memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR, + sysbus_mmio_get_region(SYS_BUS_DEVICE(= ipi), + cpu * 2 + 1)); /* extioi iocsr memory region */ memory_region_add_subregion(&env->system_iocsr, APIC_BASE, sysbus_mmio_get_region(SYS_BUS_DEVICE(exti= oi), diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ip= i.h index 996ed7ea93..0ee48fca55 100644 --- a/include/hw/intc/loongarch_ipi.h +++ b/include/hw/intc/loongarch_ipi.h @@ -24,8 +24,9 @@ #define IOCSR_MAIL_SEND 0x48 #define IOCSR_ANY_SEND 0x158 =20 -/* IPI system memory address */ -#define IPI_SYSTEM_MEM 0x1fe01000 +#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND) +#define MAIL_SEND_OFFSET 0 +#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND) =20 #define MAX_IPI_CORE_NUM 4 #define MAX_IPI_MBX_NUM 4 @@ -46,7 +47,7 @@ typedef struct IPICore { struct LoongArchIPI { SysBusDevice parent_obj; MemoryRegion ipi_iocsr_mem[MAX_IPI_CORE_NUM]; - MemoryRegion ipi_system_mem[MAX_IPI_CORE_NUM]; + MemoryRegion ipi64_iocsr_mem[MAX_IPI_CORE_NUM]; }; =20 #endif --=20 2.31.1 From nobody Mon Feb 9 18:54:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1657004103898387.37495216629463; Mon, 4 Jul 2022 23:55:03 -0700 (PDT) Received: from localhost ([::1]:42638 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o8cSc-0007s6-NN for importer@patchew.org; Tue, 05 Jul 2022 02:55:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45822) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o8cN9-0002LJ-Rb for qemu-devel@nongnu.org; Tue, 05 Jul 2022 02:49:23 -0400 Received: from mail.loongson.cn ([114.242.206.163]:56864 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o8cN2-00056Q-0X for qemu-devel@nongnu.org; Tue, 05 Jul 2022 02:49:23 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Ax+eDd3sNi_PcJAA--.31000S4; Tue, 05 Jul 2022 14:49:02 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, maobibo@loongson.cn, mark.cave-ayland@ilande.co.uk, mst@redhat.com, imammedo@redhat.com, ani@anisinha.ca, f4bug@amsat.org, peter.maydell@linaro.org Subject: [PATCH 2/2] hw/intc/loongarch_ipi: Fix mail send and any send function Date: Tue, 5 Jul 2022 14:49:01 +0800 Message-Id: <20220705064901.2353349-3-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220705064901.2353349-1-yangxiaojuan@loongson.cn> References: <20220705064901.2353349-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf9Ax+eDd3sNi_PcJAA--.31000S4 X-Coremail-Antispam: 1UD129KBjvJXoWxXryfXw45Kw4rZF17ur4xCrg_yoW5Cw4Upr 9xur4ayw48Aay3WayDJ34UZF1DJr97Way5CFsxK34F9w1DZr9I934qg39aqF1qka48WF1Y vr4kAw4FvF4UXaDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1657004104862100001 Content-Type: text/plain; charset="utf-8" By the document of ipi mailsend device, byte is written only when the mask = bit is 0. The original code discards mask bit and overwrite the data always, th= is patch fixes the issue. Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson --- hw/intc/loongarch_ipi.c | 54 +++++++++++++++++++++++------------------ 1 file changed, 31 insertions(+), 23 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index b8b1b9cd53..4f3c58f872 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -50,35 +50,45 @@ static uint64_t loongarch_ipi_readl(void *opaque, hwadd= r addr, unsigned size) return ret; } =20 -static int get_ipi_data(target_ulong val) +static void send_ipi_data(CPULoongArchState *env, target_ulong val, target= _ulong addr) { - int i, mask, data; + int i, mask =3D 0, data =3D 0; =20 - data =3D val >> 32; - mask =3D (val >> 27) & 0xf; - - for (i =3D 0; i < 4; i++) { - if ((mask >> i) & 1) { - data &=3D ~(0xff << (i * 8)); + /* + * bit 27-30 is mask for byte writing, + * if the mask is 0, we need not to do anything. + */ + if ((val >> 27) & 0xf) { + data =3D address_space_ldl(&env->address_space_iocsr, addr, + MEMTXATTRS_UNSPECIFIED, NULL); + for (i =3D 0; i < 4; i++) { + /* get mask for byte writing */ + if (val & (0x1 << (27 + i))) { + mask |=3D 0xff << (i * 8); + } } } - return data; + + data &=3D mask; + data |=3D (val >> 32) & ~mask; + address_space_stl(&env->address_space_iocsr, addr, + data, MEMTXATTRS_UNSPECIFIED, NULL); } =20 static void ipi_send(uint64_t val) { int cpuid, data; CPULoongArchState *env; + CPUState *cs; + LoongArchCPU *cpu; =20 cpuid =3D (val >> 16) & 0x3ff; /* IPI status vector */ data =3D 1 << (val & 0x1f); - qemu_mutex_lock_iothread(); - CPUState *cs =3D qemu_get_cpu(cpuid); - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + cs =3D qemu_get_cpu(cpuid); + cpu =3D LOONGARCH_CPU(cs); env =3D &cpu->env; loongarch_cpu_set_irq(cpu, IRQ_IPI, 1); - qemu_mutex_unlock_iothread(); address_space_stl(&env->address_space_iocsr, 0x1008, data, MEMTXATTRS_UNSPECIFIED, NULL); =20 @@ -86,23 +96,23 @@ static void ipi_send(uint64_t val) =20 static void mail_send(uint64_t val) { - int cpuid, data; + int cpuid; hwaddr addr; CPULoongArchState *env; + CPUState *cs; + LoongArchCPU *cpu; =20 cpuid =3D (val >> 16) & 0x3ff; addr =3D 0x1020 + (val & 0x1c); - CPUState *cs =3D qemu_get_cpu(cpuid); - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + cs =3D qemu_get_cpu(cpuid); + cpu =3D LOONGARCH_CPU(cs); env =3D &cpu->env; - data =3D get_ipi_data(val); - address_space_stl(&env->address_space_iocsr, addr, - data, MEMTXATTRS_UNSPECIFIED, NULL); + send_ipi_data(env, val, addr); } =20 static void any_send(uint64_t val) { - int cpuid, data; + int cpuid; hwaddr addr; CPULoongArchState *env; =20 @@ -111,9 +121,7 @@ static void any_send(uint64_t val) CPUState *cs =3D qemu_get_cpu(cpuid); LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); env =3D &cpu->env; - data =3D get_ipi_data(val); - address_space_stl(&env->address_space_iocsr, addr, - data, MEMTXATTRS_UNSPECIFIED, NULL); + send_ipi_data(env, val, addr); } =20 static void loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_t val, --=20 2.31.1