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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.30.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:30:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jSRI4ytW1sFMKbuxbbpqso1yyhuZxQO9hmINCal5n3U=; b=GAvxKuOc20SOBp8VQ6wHvnSUQffmw9QPpbW+G6hu/Flm3VYu8DTrezT/cJlG0B15dz 8lTLEQB3NuyvYhTfZSFblmhIBcYECpGfRT+9OvfTNbkBG3CaEzMN/ye2XS/alrHHyuv4 aSnzHHCaauUWmHt/lxzInDrz+KEppAy8mV3wEtQFuyxBgxdf/15yqbEKzX4Iz6hB+DER AiE/bjDYB3RGzAHejT//hmzEYUYCdJss2QCMY7wQNn41U1JStvyyxpGXC+E3AfWSwDJP XVq2vlj6/nx/2Bhu/8ECWUD6tiZrb9U2+cbkUzxWcdgX0rKYp8IqVO8DNnw/xNq3Fbyu pyhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jSRI4ytW1sFMKbuxbbpqso1yyhuZxQO9hmINCal5n3U=; b=QrbY9Qa7xTSgmT/BI5wkXxC2Y8ErFCeEtrefSN5tNvDHZVh/YEcP+otYv4a93ZAwo5 IO/2GcnvBydnVsDrBUlZRkN2lqlLcViN3CBCVrMyMyn8qt3RXmBYgePTKRtMSouvWxW7 5kCaj4o8eiWfrx0TnPUpmTKsWnCSsaqAY861h4RQM+lYOs+nDDkyjw0XJFeNC3HbfZ7E tWQ5lEN3nBKpIXOGUGNrti3uFiPOIOe2HDwcQY99x+q71SOpw74bi9W6x6c5IF1c+TG9 DGaCjDbNCDVtrjJ5ICcHhsDYTjWbnkFiLdN40VuLNpiMZOLJAEWBYuf7jpH2Ch8QwzLr 3t+A== X-Gm-Message-State: AJIora8e0QoyZ2QC16rU3gTjXBKjczWuT9mrmpNz/SZpOphc/ywZdxVk Jt/mY/7Tq8yE2a/trSF+dZhJ/aW5mFDOBKaX X-Google-Smtp-Source: AGRyM1tMp8M3hO0iYcQIUXpYiSXFU/ZYPlFmUVnEq4wx5ewn0yP6aTh57CW7/7XLF267azslyjKmGw== X-Received: by 2002:a63:80c8:0:b0:411:73dd:809b with SMTP id j191-20020a6380c8000000b0041173dd809bmr19793594pgd.441.1656837024835; Sun, 03 Jul 2022 01:30:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 59/62] target/arm: Fix fault reporting in get_phys_addr_lpae Date: Sun, 3 Jul 2022 13:54:16 +0530 Message-Id: <20220703082419.770989-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656841123054100001 Content-Type: text/plain; charset="utf-8" Always overriding fi->type was incorrect, as we would not properly propagate the fault type from S1_ptw_translate, or arm_ldq_ptw. Simplify things by providing a new label for reporting a translation fault. For other faults, store into fi directly. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a3f063e0bc..678ad2ac0c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1012,8 +1012,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) { ARMCPU *cpu =3D env_archcpu(env); - /* Read an LPAE long-descriptor translation table. */ - ARMFaultType fault_type =3D ARMFault_Translation; uint32_t level; ARMVAParameters param; uint64_t ttbr; @@ -1051,8 +1049,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, * so our choice is to always raise the fault. */ if (param.tsz_oob) { - fault_type =3D ARMFault_Translation; - goto do_fault; + goto do_translation_fault; } =20 addrsize =3D 64 - 8 * param.tbi; @@ -1089,8 +1086,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, addrsize - inputsize); if (-top_bits !=3D param.select) { /* The gap between the two regions is a Translation fault */ - fault_type =3D ARMFault_Translation; - goto do_fault; + goto do_translation_fault; } } =20 @@ -1122,7 +1118,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, * Translation table walk disabled =3D> Translation fault on TLB m= iss * Note: This is always 0 on 64-bit EL2 and EL3. */ - goto do_fault; + goto do_translation_fault; } =20 if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2_S) { @@ -1153,8 +1149,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, if (param.ds && stride =3D=3D 9 && sl2) { if (sl0 !=3D 0) { level =3D 0; - fault_type =3D ARMFault_Translation; - goto do_fault; + goto do_translation_fault; } startlevel =3D -1; } else if (!aarch64 || stride =3D=3D 9) { @@ -1173,8 +1168,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, ok =3D check_s2_mmu_setup(cpu, aarch64, startlevel, inputsize, stride, outputsize); if (!ok) { - fault_type =3D ARMFault_Translation; - goto do_fault; + goto do_translation_fault; } level =3D startlevel; } @@ -1196,7 +1190,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, descaddr |=3D extract64(ttbr, 2, 4) << 48; } else if (descaddr >> outputsize) { level =3D 0; - fault_type =3D ARMFault_AddressSize; + fi->type =3D ARMFault_AddressSize; goto do_fault; } =20 @@ -1246,7 +1240,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, =20 if (!(descriptor & 1) || (!(descriptor & 2) && (level =3D=3D 3))) { /* Invalid, or the Reserved level 3 encoding */ - goto do_fault; + goto do_translation_fault; } =20 descaddr =3D descriptor & descaddrmask; @@ -1264,7 +1258,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, descaddr |=3D extract64(descriptor, 12, 4) << 48; } } else if (descaddr >> outputsize) { - fault_type =3D ARMFault_AddressSize; + fi->type =3D ARMFault_AddressSize; goto do_fault; } =20 @@ -1321,9 +1315,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, * Here descaddr is the final physical address, and attributes * are all in attrs. */ - fault_type =3D ARMFault_AccessFlag; if ((attrs & (1 << 8)) =3D=3D 0) { /* Access flag */ + fi->type =3D ARMFault_AccessFlag; goto do_fault; } =20 @@ -1340,8 +1334,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, result->prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn= ); } =20 - fault_type =3D ARMFault_Permission; if (!(result->prot & (1 << access_type))) { + fi->type =3D ARMFault_Permission; goto do_fault; } =20 @@ -1385,8 +1379,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint= 64_t address, result->page_size =3D page_size; return false; =20 -do_fault: - fi->type =3D fault_type; + do_translation_fault: + fi->type =3D ARMFault_Translation; + do_fault: fi->level =3D level; /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ fi->stage2 =3D fi->s1ptw || (mmu_idx =3D=3D ARMMMUIdx_Stage2 || --=20 2.34.1