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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656840126099100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 ++ target/arm/helper.c | 8 +++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1bbe4d950e..f2a421972e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1004,6 +1004,8 @@ typedef struct ARMVAParameters { bool using64k : 1; bool tsz_oob : 1; /* tsz has been clamped to legal range */ bool ds : 1; + bool ha : 1; + bool hd : 1; } ARMVAParameters; =20 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, diff --git a/target/arm/helper.c b/target/arm/helper.c index 499577f24e..9aea6ad5f4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10626,7 +10626,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, ARMMMUIdx mmu_idx, bool data) { uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; - bool epd, hpd, using16k, using64k, tsz_oob, ds; + bool epd, hpd, using16k, using64k, tsz_oob, ds, ha, hd; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; ARMCPU *cpu =3D env_archcpu(env); =20 @@ -10644,6 +10644,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, epd =3D false; sh =3D extract32(tcr, 12, 2); ps =3D extract32(tcr, 16, 3); + ha =3D extract32(tcr, 21, 1) && cpu_isar_feature(aa64_hafs, cpu); + hd =3D extract32(tcr, 22, 1) && cpu_isar_feature(aa64_hdbs, cpu); ds =3D extract64(tcr, 32, 1); } else { /* @@ -10668,6 +10670,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, hpd =3D extract64(tcr, 42, 1); } ps =3D extract64(tcr, 32, 3); + ha =3D extract64(tcr, 39, 1) && cpu_isar_feature(aa64_hafs, cpu); + hd =3D extract64(tcr, 40, 1) && cpu_isar_feature(aa64_hdbs, cpu); ds =3D extract64(tcr, 59, 1); } =20 @@ -10739,6 +10743,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, .using64k =3D using64k, .tsz_oob =3D tsz_oob, .ds =3D ds, + .ha =3D ha, + .hd =3D ha & hd, }; } =20 --=20 2.34.1