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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.29.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:29:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AgrCDzDvTqOdWxJ0VR4VmcOIV2B9QnGlk8qFxEZQR4I=; b=OxUyRGI4/edokV/YWLZKHq+7yfgsT2CE+cPE4UTyAgrga+jjmKG00RKaSWYfhxm+BB dh7YLayO6oFHMNV0/55hpxlZyiGxoq7JUjL58pGF70p2QJHWdv83zCWCUAscei2I7u+4 Cj2uEiD0JmOAb4HGV6Y/q9hRkuo1+mkmQGQgIFlZxWvyoQ/0Ft2zBEmft89JvNQUjtC9 j2fjGpBSA0A3Jnf7EnHlTY2x/tTSytQ6up7eBwbl1vnngV8WsjIblTIvwR+w8XY2rWk4 W/3C0GmxGZcHHqVWfaFIbRlaxMykGJCaTuiAlADq2u0nuNhSq4ThoL6d4on2yQthadKS N7dA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AgrCDzDvTqOdWxJ0VR4VmcOIV2B9QnGlk8qFxEZQR4I=; b=HcrtVi4jkG5XW/Gkcw94/gumOfvclcLiHtQyM/V1SHmHNa2xow9SDvdagTNfjqIAQ+ 3MD56IMPR1wVS+Z1nOJD6IK/5asTOXXw9/1UIesVxcgTkNjfUQVEl2mr3CrMroqiDiUF sxn6haC6k0T5ETHOmyHlxYnsaGkliYY022Ml/YQ6XsYXb6F/jSxqZ4lzFvMpRqkR1gnV QN4zmnfL/de6+0Ve7OqYRLWTOBDNqR8YYgvpTtJMHfaANqPRI2XqNsI0Dqz7TgUoNRZr JNjWE3w6PsBaLV5FILRw1tT5PpuUwmiJYXOCW/+/t3pl+5pqhjO6iYlVmQc2O3YHpamg dY2w== X-Gm-Message-State: AJIora+7kc030UnNUTmKlTUc+Nx4jaguJysnp/3hXWXUVvEMuW3Olv3R eOHIu45fmwSSydO+flTln0rKRwFdg5wIVVyq X-Google-Smtp-Source: AGRyM1sSy5meGc+loMUp7I0MnhkUthNBGj2L+T7UsIz6OhvfvHF1I6oDNaOvpj9WPyCItctFOqqKGg== X-Received: by 2002:a17:902:d50e:b0:16a:13d:30ab with SMTP id b14-20020a170902d50e00b0016a013d30abmr29985412plg.31.1656836988547; Sun, 03 Jul 2022 01:29:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 46/62] target/arm: Use softmmu tlbs for page table walking Date: Sun, 3 Jul 2022 13:54:03 +0530 Message-Id: <20220703082419.770989-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656840475750100001 Content-Type: text/plain; charset="utf-8" So far, limit the change to S1_ptw_translate, arm_ldl_ptw, and arm_ldq_ptw. Use probe_access_extra to find the host address, and if so use a host load. If the probe fails, we've got our fault info already. On the off chance that page tables are not in RAM, continue to use the address_space_ld* functions. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + target/arm/ptw.c | 206 +++++++++++++++++++++++----------------- target/arm/tlb_helper.c | 17 +++- 3 files changed, 139 insertions(+), 89 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8ea9f08511..e5e3084ec9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -231,6 +231,8 @@ typedef struct CPUARMTBFlags { target_ulong flags2; } CPUARMTBFlags; =20 +typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; + typedef struct CPUArchState { /* Regs for current mode. */ uint32_t regs[16]; @@ -720,6 +722,9 @@ typedef struct CPUArchState { struct CPUBreakpoint *cpu_breakpoint[16]; struct CPUWatchpoint *cpu_watchpoint[16]; =20 + /* Optional fault info across tlb lookup. */ + ARMMMUFaultInfo *tlb_fi; + /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7510a9276a..ed25f4b91e 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/range.h" +#include "exec/exec-all.h" #include "cpu.h" #include "internals.h" #include "idau.h" @@ -191,52 +192,58 @@ static bool regime_translation_disabled(CPUARMState *= env, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; } =20 -static bool ptw_attrs_are_device(uint64_t hcr, ARMCacheAttrs cacheattrs) -{ - /* - * For an S1 page table walk, the stage 1 attributes are always - * some form of "this is Normal memory". The combined S1+S2 - * attributes are therefore only Device if stage 2 specifies Device. - * With HCR_EL2.FWB =3D=3D 0 this is when descriptor bits [5:4] are 0b= 00, - * ie when cacheattrs.attrs bits [3:2] are 0b00. - * With HCR_EL2.FWB =3D=3D 1 this is when descriptor bit [4] is 0, ie - * when cacheattrs.attrs bit [2] is 0. - */ - assert(cacheattrs.is_s2_format); - if (hcr & HCR_FWB) { - return (cacheattrs.attrs & 0x4) =3D=3D 0; - } else { - return (cacheattrs.attrs & 0xc) =3D=3D 0; - } -} - /* Translate a S1 pagetable walk through S2 if needed. */ -static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, - hwaddr addr, bool *is_secure_ptr, - ARMMMUFaultInfo *fi) +static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr a= ddr, + bool *is_secure_ptr, void **hphys, hwaddr *gp= hys, + ARMMMUFaultInfo *fi) { bool is_secure =3D *is_secure_ptr; ARMMMUIdx s2_mmu_idx =3D is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_St= age2; + MemTxAttrs attrs =3D {}; + PageEntryExtra extra; + int flags; =20 - if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, s2_mmu_idx, is_secure)) { - GetPhysAddrResult s2 =3D {}; - uint64_t hcr; - int ret; + if (!arm_mmu_idx_is_stage1_of_2(mmu_idx) + || regime_translation_disabled(env, s2_mmu_idx, is_secure)) { + s2_mmu_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; + } =20 - ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, - is_secure, false, &s2, fi); - if (ret) { - assert(fi->type !=3D ARMFault_None); - fi->s2addr =3D addr; - fi->stage2 =3D true; - fi->s1ptw =3D true; - fi->s1ns =3D !is_secure; - return ~0; + env->tlb_fi =3D fi; + flags =3D probe_access_extra(env, addr, MMU_DATA_LOAD, + arm_to_core_mmu_idx(s2_mmu_idx), + true, hphys, &attrs, &extra, 0); + env->tlb_fi =3D NULL; + + if (unlikely(flags & TLB_INVALID_MASK)) { + assert(fi->type !=3D ARMFault_None); + fi->s2addr =3D addr; + fi->stage2 =3D true; + fi->s1ptw =3D true; + fi->s1ns =3D !is_secure; + return false; + } + + if (s2_mmu_idx =3D=3D ARMMMUIdx_Stage2 || s2_mmu_idx =3D=3D ARMMMUIdx_= Stage2_S) { + uint64_t hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); + uint8_t s2attrs =3D FIELD_EX64(extra.x, PAGEENTRYEXTRA, ATTRS); + bool is_device; + + /* + * For an S1 page table walk, the stage 1 attributes are always + * some form of "this is Normal memory". The combined S1+S2 + * attributes are therefore only Device if stage 2 specifies Devic= e. + * With HCR_EL2.FWB =3D=3D 0 this is when descriptor bits [5:4] ar= e 0b00, + * ie when s2attrs bits [3:2] are 0b00. + * With HCR_EL2.FWB =3D=3D 1 this is when descriptor bit [4] is 0,= ie + * when s2attrs bit [2] is 0. + */ + if (hcr & HCR_FWB) { + is_device =3D (s2attrs & 0x4) =3D=3D 0; + } else { + is_device =3D (s2attrs & 0xc) =3D=3D 0; } =20 - hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); - if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) { + if ((hcr & HCR_PTW) && is_device) { /* * PTW set and S1 walk touched S2 Device memory: * generate Permission fault. @@ -246,24 +253,19 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, fi->stage2 =3D true; fi->s1ptw =3D true; fi->s1ns =3D !is_secure; - return ~0; + return false; } - - if (arm_is_secure_below_el3(env)) { - /* Check if page table walk is to secure or non-secure PA spac= e. */ - if (is_secure) { - is_secure =3D !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); - } else { - is_secure =3D !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); - } - *is_secure_ptr =3D is_secure; - } else { - assert(!is_secure); - } - - addr =3D s2.phys; } - return addr; + + if (is_secure) { + /* Check if page table walk is to secure or non-secure PA space. */ + *is_secure_ptr =3D !(attrs.secure + ? env->cp15.vstcr_el2.raw_tcr & VSTCR_SW + : env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); + } + + *gphys =3D extra.x & R_PAGEENTRYEXTRA_PA_MASK; + return true; } =20 /* All loads done in the course of a page table walk go through here. */ @@ -271,56 +273,88 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr = addr, bool is_secure, ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); - MemTxAttrs attrs =3D {}; - MemTxResult result =3D MEMTX_OK; - AddressSpace *as; + void *hphys; + hwaddr gphys; uint32_t data; + bool be; =20 - addr =3D S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); - attrs.secure =3D is_secure; - as =3D arm_addressspace(cs, attrs); - if (fi->s1ptw) { + if (!S1_ptw_translate(env, mmu_idx, addr, &is_secure, + &hphys, &gphys, fi)) { + /* Failure. */ + assert(fi->s1ptw); return 0; } - if (regime_translation_big_endian(env, mmu_idx)) { - data =3D address_space_ldl_be(as, addr, attrs, &result); + + be =3D regime_translation_big_endian(env, mmu_idx); + if (likely(hphys)) { + /* Page tables are in RAM, and we have the host address. */ + if (be) { + data =3D ldl_be_p(hphys); + } else { + data =3D ldl_le_p(hphys); + } } else { - data =3D address_space_ldl_le(as, addr, attrs, &result); + /* Page tables are in MMIO. */ + MemTxAttrs attrs =3D { .secure =3D is_secure }; + AddressSpace *as =3D arm_addressspace(cs, attrs); + MemTxResult result =3D MEMTX_OK; + + if (be) { + data =3D address_space_ldl_be(as, gphys, attrs, &result); + } else { + data =3D address_space_ldl_le(as, gphys, attrs, &result); + } + if (unlikely(result !=3D MEMTX_OK)) { + fi->type =3D ARMFault_SyncExternalOnWalk; + fi->ea =3D arm_extabort_type(result); + return 0; + } } - if (result =3D=3D MEMTX_OK) { - return data; - } - fi->type =3D ARMFault_SyncExternalOnWalk; - fi->ea =3D arm_extabort_type(result); - return 0; + return data; } =20 static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); - MemTxAttrs attrs =3D {}; - MemTxResult result =3D MEMTX_OK; - AddressSpace *as; + void *hphys; + hwaddr gphys; uint64_t data; + bool be; =20 - addr =3D S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); - attrs.secure =3D is_secure; - as =3D arm_addressspace(cs, attrs); - if (fi->s1ptw) { + if (!S1_ptw_translate(env, mmu_idx, addr, &is_secure, + &hphys, &gphys, fi)) { + /* Failure. */ + assert(fi->s1ptw); return 0; } - if (regime_translation_big_endian(env, mmu_idx)) { - data =3D address_space_ldq_be(as, addr, attrs, &result); + + be =3D regime_translation_big_endian(env, mmu_idx); + if (likely(hphys)) { + /* Page tables are in RAM, and we have the host address. */ + if (be) { + data =3D ldq_be_p(hphys); + } else { + data =3D ldq_le_p(hphys); + } } else { - data =3D address_space_ldq_le(as, addr, attrs, &result); + /* Page tables are in MMIO. */ + MemTxAttrs attrs =3D { .secure =3D is_secure }; + AddressSpace *as =3D arm_addressspace(cs, attrs); + MemTxResult result =3D MEMTX_OK; + + if (be) { + data =3D address_space_ldq_be(as, gphys, attrs, &result); + } else { + data =3D address_space_ldq_le(as, gphys, attrs, &result); + } + if (unlikely(result !=3D MEMTX_OK)) { + fi->type =3D ARMFault_SyncExternalOnWalk; + fi->ea =3D arm_extabort_type(result); + return 0; + } } - if (result =3D=3D MEMTX_OK) { - return data; - } - fi->type =3D ARMFault_SyncExternalOnWalk; - fi->ea =3D arm_extabort_type(result); - return 0; + return data; } =20 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 28495ff525..d0b978bb9a 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -208,10 +208,21 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr) { ARMCPU *cpu =3D ARM_CPU(cs); - ARMMMUFaultInfo fi =3D {}; GetPhysAddrResult res =3D {}; + ARMMMUFaultInfo local_fi, *fi; int ret; =20 + /* + * Allow S1_ptw_translate to see any fault generated here. + * Since this may recurse, read and clear. + */ + fi =3D cpu->env.tlb_fi; + if (fi) { + cpu->env.tlb_fi =3D NULL; + } else { + fi =3D memset(&local_fi, 0, sizeof(local_fi)); + } + /* * Walk the page table and (if the mapping exists) add the page * to the TLB. On success, return true. Otherwise, if probing, @@ -220,7 +231,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, */ ret =3D get_phys_addr(&cpu->env, address, access_type, core_to_arm_mmu_idx(&cpu->env, mmu_idx), - &res, &fi); + &res, fi); if (likely(!ret)) { PageEntryExtra extra =3D {}; =20 @@ -252,7 +263,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, } else { /* now we have a real cpu fault */ cpu_restore_state(cs, retaddr, true); - arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); + arm_deliver_fault(cpu, address, access_type, mmu_idx, fi); } } #else --=20 2.34.1