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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.29.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:29:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2GREabbEg+nDIDAuvpznWWqWDzHWosOK+NnY9rFGuOE=; b=ZvUEkPZpWXWtBAkQaMCS/tYuuu4ZYd0Y3JEZr8wTZWqg57dShVzKxiZWYis2lIkC5c V9ySmkPVaO+ZK7ElRo1/x6OghG/vVWW8DKgM7O71/GLI1pZ61Pwnqi6kT8taa+Cbd1uB cjhExKpXvDPe2ap0QlWpxMQTvrLkjkSyamHAaOVNevCoH7rYpKO+HOWmy3Hnf2O0cd54 58R3fmlLLtlO/aqUfUK/tIyuaAysG0RSpX7ZB2/vrVg1iuYamts9CNVZcXc7migu1z0D iuCL4ecaab/wDCYJ9ioV2QxFUPR7NJa0GVqyF5Qd/GQhTk45BqDLxyNgrL01i3Dzwwea /b4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2GREabbEg+nDIDAuvpznWWqWDzHWosOK+NnY9rFGuOE=; b=esqaJYV1UcobLr8y8y8XqIk1DTfB+ZS8Gyu7uxJM7MXjKIr8tXpe8+DYku0ezXfxd9 wpSARwa5frHAe7w0jMlJuOG3NYAzDj2SvHJud8+ud9T9/Izz2i6PW+r3dSbss/vd6ipY oP6cw4RwBl0BNqpf9+gzvkHLgTcDHMg7LdG1QPwk79M72YWhqSq8sYokVRyLa8z7QBPk 6MW2WfcyJNIIawftNioM8OkXqUkeSTtTbtbqP5R18I2VLMSDn0eCfEb/EwI6ecGh+EmG IlCfvFWv+VSl5xcRs60vB3hrqUBFGyE4IiTiKaW8ubYy2i+/DmyqGPhQ7668QwdPjlVg U0TA== X-Gm-Message-State: AJIora+H+O/smCPznCEiYdMW6331EQvvDfy5Zu6itlBZN1kabrK2KYlN Poi50ruxJqGPtE4qbY+P7QSO4NJBByoxbLL2 X-Google-Smtp-Source: AGRyM1tdMScX0GmoVmf5H1AZNAdtT2vUzaqtMl2nvUkLrIJD+NnkWKICMHqprt1cfAIexrAmFraREw== X-Received: by 2002:a17:902:dac3:b0:16b:914a:81ba with SMTP id q3-20020a170902dac300b0016b914a81bamr26663447plx.19.1656836982539; Sun, 03 Jul 2022 01:29:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 44/62] target/arm: Add ARMMMUIdx_Phys_{S,NS} Date: Sun, 3 Jul 2022 13:54:01 +0530 Message-Id: <20220703082419.770989-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656840091782100001 Content-Type: text/plain; charset="utf-8" Not yet used, but add mmu indexes for 1-1 mapping to physical addresses. Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 4 ++++ target/arm/ptw.c | 9 +++++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 6f702f58d9..931808f2e7 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -40,6 +40,6 @@ struct PageEntryExtra { }; #endif =20 -#define NB_MMU_MODES 8 +#define NB_MMU_MODES 10 =20 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index dd577a08bc..c5aec164ba 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2934,6 +2934,10 @@ typedef enum ARMMMUIdx { ARMMMUIdx_E2 =3D 6 | ARM_MMU_IDX_A, ARMMMUIdx_E3 =3D 7 | ARM_MMU_IDX_A, =20 + /* TLBs with 1-1 mapping to the physical address spaces. */ + ARMMMUIdx_Phys_NS =3D 8 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_S =3D 9 | ARM_MMU_IDX_A, + /* * These are not allocated TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 3a098882a6..7510a9276a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -179,6 +179,11 @@ static bool regime_translation_disabled(CPUARMState *e= nv, ARMMMUIdx mmu_idx, case ARMMMUIdx_E3: break; =20 + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_S: + /* No translation for physical address spaces. */ + return true; + default: g_assert_not_reached(); } @@ -2284,6 +2289,8 @@ static bool get_phys_addr_disabled(CPUARMState *env, = target_ulong address, switch (mmu_idx) { case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2_S: + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_S: memattr =3D 0x00; /* unused, but Device, nGnRnE */ shareability =3D 0; /* unused, but non-shareable */ break; @@ -2574,6 +2581,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, is_secure =3D arm_is_secure_below_el3(env); break; case ARMMMUIdx_Stage2: + case ARMMMUIdx_Phys_NS: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: @@ -2582,6 +2590,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, break; case ARMMMUIdx_E3: case ARMMMUIdx_Stage2_S: + case ARMMMUIdx_Phys_S: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: --=20 2.34.1