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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id g6-20020a1709026b4600b0016788487357sm18574523plt.132.2022.07.03.01.29.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:29:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=czDINC237o/2raNbHTOaskPo+9bv5Oqa4q6sEcK6I78=; b=Hj7o0Y3r0lqvTyK2CYq3RAtYEkMqg5+A2HjmDvajpOo51ezGApVpCreR0ukp+GfmLu qF51M3RIYa2xn+n+52SoShWRg8l+8R4sY3WQP/mjvJttVW5ymSOcq7dco9OL1VlPNkJH gdgbD8posTwN6G+zLGMhYAlbqed9aQQpX8IMAMEdkGjGatchparTbVYDLnxcoD8pk1A7 MQ2sEX20DzMsDOGQm0w6FzwZKrVc+RCO6CozZXe+EMdmT2WEEwKO8KxnKgd+IQDlv79S W5TpZyjYLi5WUkpWm8V7xUqAKqG+H1epEe06JuXtL20AZnLbPbdQAAMQ3pDoHDrx/YnM Tlgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=czDINC237o/2raNbHTOaskPo+9bv5Oqa4q6sEcK6I78=; b=5H8h1dh4J0s4n/zw8P0r+ieH+fRfKGtYQXRzqY+0/NYnLWFOUt1dnT8peOU/l2G/fq KnyNpclqb8QaUMDAE6jlR31x8Q4VMpB9y3O9S6LxzUxh0wxwbFfQsS7v6vYXi51Hykqs ad5MFGhr61M+XpoEohavBLtfZrwEPhg2Pugl2NlEPlo537YedMa3i0iEUt5lE8o4YYiQ XgHsxBmGzQgTC68lJ5JHs2N91C+yhEkeRAcs1E/68332OjLFKXsXhDCyi//9DU341EVP wQXNOcbMEoVehl5eJmBnMc81BEd0GIKlJJfF7MCo/OMpsAwWP68UI88Rfn/C6dbbAcH8 fhZg== X-Gm-Message-State: AJIora/hbWMlQsASIxnRhlrMCG3rTNqQMBCx6VjRIU7z299iMqRp++rN i2YiJ8g3hb0qHtqddmr0HDIPO0FbXd9t5zrn X-Google-Smtp-Source: AGRyM1sWv/VhA3Y18QDmA8JAWHlh3HyTumptIw/1GE3Xuf/86g1BCyxD/bRnC4TTi6mBw5HU5o8fwg== X-Received: by 2002:a17:902:9046:b0:168:b8ee:8164 with SMTP id w6-20020a170902904600b00168b8ee8164mr28932579plz.159.1656836979283; Sun, 03 Jul 2022 01:29:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 43/62] target/arm: Reorg get_phys_addr_disabled Date: Sun, 3 Jul 2022 13:54:00 +0530 Message-Id: <20220703082419.770989-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656839762371100001 Content-Type: text/plain; charset="utf-8" Use a switch. Do not apply memattr or shareability for Stage2 translations. Make sure to apply HCR_{DC,DCT} only to Regime_EL10, per the pseudocode in AArch64.S1DisabledOutput. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 115 +++++++++++++++++++++++++++-------------------- 1 file changed, 67 insertions(+), 48 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0f4b9b0166..3a098882a6 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2278,64 +2278,83 @@ static bool get_phys_addr_disabled(CPUARMState *env= , target_ulong address, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - uint64_t hcr; - uint8_t memattr; + uint64_t hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); + uint8_t memattr, shareability; =20 - if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2_S) { - int r_el =3D regime_el(env, mmu_idx); - if (arm_el_is_aa64(env, r_el)) { - int pamax =3D arm_pamax(env_archcpu(env)); - uint64_t tcr =3D env->cp15.tcr_el[r_el].raw_tcr; - int addrtop, tbi; + switch (mmu_idx) { + case ARMMMUIdx_Stage2: + case ARMMMUIdx_Stage2_S: + memattr =3D 0x00; /* unused, but Device, nGnRnE */ + shareability =3D 0; /* unused, but non-shareable */ + break; =20 - tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); - if (access_type =3D=3D MMU_INST_FETCH) { - tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: + if (hcr & HCR_DC) { + if (hcr & HCR_DCT) { + memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ + } else { + memattr =3D 0xff; /* Normal, WB, RWA */ } - tbi =3D (tbi >> extract64(address, 55, 1)) & 1; - addrtop =3D (tbi ? 55 : 63); - - if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0) { - fi->type =3D ARMFault_AddressSize; - fi->level =3D 0; - fi->stage2 =3D false; - return 1; - } - - /* - * When TBI is disabled, we've just validated that all of the - * bits above PAMax are zero, so logically we only need to - * clear the top byte for TBI. But it's clearer to follow - * the pseudocode set of addrdesc.paddress. - */ - address =3D extract64(address, 0, 52); + shareability =3D 0; /* non-shareable */ + goto check_range; } + /* fall through */ + + default: + if (access_type =3D=3D MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr =3D 0xee; /* Normal, WT, RA, NT */ + } else { + memattr =3D 0x44; /* Normal, NC, No */ + } + shareability =3D 2; /* Outer sharable */ + } else { + memattr =3D 0x00; /* unused, but Device, nGnRnE */ + shareability =3D 0; /* non-shareable */ + } + /* fall through */ + + check_range: + { + int r_el =3D regime_el(env, mmu_idx); + if (arm_el_is_aa64(env, r_el)) { + int pamax =3D arm_pamax(env_archcpu(env)); + uint64_t tcr =3D env->cp15.tcr_el[r_el].raw_tcr; + int addrtop, tbi; + + tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); + if (access_type =3D=3D MMU_INST_FETCH) { + tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi =3D (tbi >> extract64(address, 55, 1)) & 1; + addrtop =3D (tbi ? 55 : 63); + + if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0)= { + fi->type =3D ARMFault_AddressSize; + fi->level =3D 0; + fi->stage2 =3D false; + return 1; + } + + /* + * When TBI is disabled, we've just validated that all of + * the bits above PAMax are zero, so logically we only + * need to clear the top byte for TBI. But it's clearer + * to follow the pseudocode set of addrdesc.paddress. + */ + address =3D extract64(address, 0, 52); + } + } + break; } =20 result->phys =3D address; result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; result->page_size =3D TARGET_PAGE_SIZE; - - /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr =3D arm_hcr_el2_eff_secstate(env, is_secure); - result->cacheattrs.shareability =3D 0; result->cacheattrs.is_s2_format =3D false; - if (hcr & HCR_DC) { - if (hcr & HCR_DCT) { - memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ - } else { - memattr =3D 0xff; /* Normal, WB, RWA */ - } - } else if (access_type =3D=3D MMU_INST_FETCH) { - if (regime_sctlr(env, mmu_idx) & SCTLR_I) { - memattr =3D 0xee; /* Normal, WT, RA, NT */ - } else { - memattr =3D 0x44; /* Normal, NC, No */ - } - result->cacheattrs.shareability =3D 2; /* outer sharable */ - } else { - memattr =3D 0x00; /* Device, nGnRnE */ - } + result->cacheattrs.shareability =3D shareability; result->cacheattrs.attrs =3D memattr; return 0; } --=20 2.34.1