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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.24.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:24:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DdLOiptFXL9CcnkCotyXYaThQ0hCVa+9TlUHODJFgEk=; b=VecQKocG1eKt0ihSygv1Rk7I8ZZdEo1pjTU903hoX144uKNnS9ciuF/CWSsMAHOgNv 7h6Sb/YDUZy1qD/alplytzYFpx10HALTx54zzbXZ9NwJ/OemghMpJmF81ZhCXqosZ4Ow xS3Y0GQAIsSAhi9IxFNGy0AbAT7WBoZYRSkRDLxaxpLhz/MwhQR/8lpQxae+lLi60/ap N/nAoXykVzZwzSLfQGCpS65T4o1cv3STXyx+bADTGuEC1lvF+kTnSckfsSC+NBSp1RAp GpVBwmbY+j98//xEaFMRfGC73oL76ct1xjv6vSpI/We+Q2aSZxDctGr7nLkm01yDep8V PLEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DdLOiptFXL9CcnkCotyXYaThQ0hCVa+9TlUHODJFgEk=; b=l5f4bYie4YaPnZA4THBCuhsxGSillU32nWg5eBiWvlYCHsRhhpHhH5dQRE6pKmJJvi 10Zv+xo2/OYzzje26G7/+aAaNNDBm2NE1Dgw3h8FN0wDNZ0no7YyC2mZTgfaMuB3TEYh jpGRkmjnhtOKROcuBBtUoRjO8qFdY2QLoek+zPF43uONe7t4wy50mn3n4VbWThZjZvSS ql6QXS+2gXA54CODaPbOoxKQZ1QM7lki7TMD6bB4BTDUtIssXztLTsHM9eCF2ZVNWSnJ Go8Xala9Yqog5eUtX3yVA2uxn/duE7fJISfWOl6zJqaIDuBcVluxhdO+y88n4HTbWfqc kPpw== X-Gm-Message-State: AJIora/OX6JDa7dsvkcCUz/+p2CENXIOLTiV8sYnjmMkkNa3xYIqm+zb ShXeRQEaIo3rYb+DpDQ3HSXgzaPc5CzYKMZ2 X-Google-Smtp-Source: AGRyM1tAy43OfzDQlqcj7I439obAjKTJHZbWibALUcl8MjhFrCNtGeTXtBrOk57JQ2onJ0sy1u2UYg== X-Received: by 2002:a17:90b:3ec7:b0:1ed:ded:abd1 with SMTP id rm7-20020a17090b3ec700b001ed0dedabd1mr26943209pjb.56.1656836669229; Sun, 03 Jul 2022 01:24:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 01/62] accel/tcg: Introduce PageEntryExtra Date: Sun, 3 Jul 2022 13:53:18 +0530 Message-Id: <20220703082419.770989-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656836795368100003 Content-Type: text/plain; charset="utf-8" Add an optional structure, controlled by TARGET_PAGE_ENTRY_EXTRA, that allows arbitrary extra data to be saved in the TLB for a given page. Set it with tlb_set_page_with_extra() and fetch it with probe_access_extra(). Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 5 +++ include/exec/exec-all.h | 26 +++++++++++++-- include/qemu/typedefs.h | 1 + accel/tcg/cputlb.c | 73 ++++++++++++++++++++++++++++++----------- 4 files changed, 84 insertions(+), 21 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index ba3cd32a1e..f14586e219 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -76,6 +76,10 @@ typedef uint64_t target_ulong; =20 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) =20 +#ifndef TARGET_PAGE_ENTRY_EXTRA +struct PageEntryExtra { }; +#endif + /* use a fully associative victim tlb of 8 entries */ #define CPU_VTLB_SIZE 8 =20 @@ -148,6 +152,7 @@ typedef struct CPUIOTLBEntry { */ hwaddr addr; MemTxAttrs attrs; + PageEntryExtra extra; } CPUIOTLBEntry; =20 /* diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 311e5fb422..2c036de3d8 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -259,11 +259,12 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUSta= te *cpu, unsigned bits); =20 /** - * tlb_set_page_with_attrs: + * tlb_set_page_with_extra: * @cpu: CPU to add this TLB entry for * @vaddr: virtual address of page to add entry for * @paddr: physical address of the page * @attrs: memory transaction attributes + * @extra: cpu specific extra information * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) * @mmu_idx: MMU index to insert TLB entry for * @size: size of the page in bytes @@ -279,11 +280,25 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUSta= te *cpu, * At most one entry for a given virtual address is permitted. Only a * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only * used by tlb_flush_page. + * + * The @extra information is target-specific, and may be retrieved + * by calling probe_access_extra(). + */ +void tlb_set_page_with_extra(CPUState *cpu, target_ulong vaddr, hwaddr pad= dr, + MemTxAttrs attrs, PageEntryExtra extra, + int prot, int mmu_idx, target_ulong size); + +/** + * tlb_set_page_with_attrs: + * + * This function is equivalent to calling tlb_set_page_with_extra() + * with an @extra argument of all zeros. */ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, hwaddr paddr, MemTxAttrs attrs, int prot, int mmu_idx, target_ulong size); -/* tlb_set_page: +/** + * tlb_set_page: * * This function is equivalent to calling tlb_set_page_with_attrs() * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided @@ -435,6 +450,13 @@ int probe_access_flags(CPUArchState *env, target_ulong= addr, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr); =20 +#ifdef CONFIG_SOFTMMU +int probe_access_extra(CPUArchState *env, target_ulong addr, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, MemTxAttrs *pattrs, + PageEntryExtra *pextra, uintptr_t retaddr); +#endif + #define CODE_GEN_ALIGN 16 /* must be >=3D of the size of a icach= e line */ =20 /* Estimated block size for TB allocation. */ diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 42f4ceb701..a4de3bb07c 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -82,6 +82,7 @@ typedef struct NodeInfo NodeInfo; typedef struct NumaNodeMem NumaNodeMem; typedef struct Object Object; typedef struct ObjectClass ObjectClass; +typedef struct PageEntryExtra PageEntryExtra; typedef struct PCIBridge PCIBridge; typedef struct PCIBus PCIBus; typedef struct PCIDevice PCIDevice; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f90f4312ea..05555961c9 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1095,16 +1095,21 @@ static void tlb_add_large_page(CPUArchState *env, i= nt mmu_idx, env_tlb(env)->d[mmu_idx].large_page_mask =3D lp_mask; } =20 -/* Add a new TLB entry. At most one entry for a given virtual address +/* + * Add a new TLB entry. At most one entry for a given virtual address * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the * supplied size is only used by tlb_flush_page. * * Called from TCG-generated code, which is under an RCU read-side * critical section. + * + * Returns a pointer to the iotlb entry, with env_tlb(env)->c.lock + * still locked, for final additions to the iotlb entry. The caller + * must unlock the lock. */ -void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, - hwaddr paddr, MemTxAttrs attrs, int prot, - int mmu_idx, target_ulong size) +void tlb_set_page_with_extra(CPUState *cpu, target_ulong vaddr, hwaddr pad= dr, + MemTxAttrs attrs, PageEntryExtra extra, + int prot, int mmu_idx, target_ulong size) { CPUArchState *env =3D cpu->env_ptr; CPUTLB *tlb =3D env_tlb(env); @@ -1238,6 +1243,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ul= ong vaddr, */ desc->iotlb[index].addr =3D iotlb - vaddr_page; desc->iotlb[index].attrs =3D attrs; + desc->iotlb[index].extra =3D extra; =20 /* Now calculate the new entry */ tn.addend =3D addend - vaddr_page; @@ -1272,7 +1278,23 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_u= long vaddr, qemu_spin_unlock(&tlb->c.lock); } =20 -/* Add a new TLB entry, but without specifying the memory +/* + * Add a new TLB entry, specifying the memory transaction + * attributes to be used. + */ +void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, + hwaddr paddr, MemTxAttrs attrs, int prot, + int mmu_idx, target_ulong size) +{ + PageEntryExtra extra; + + memset(&extra, 0, sizeof(extra)); + tlb_set_page_with_extra(cpu, vaddr, paddr, attrs, extra, + prot, mmu_idx, size); +} + +/* + * Add a new TLB entry, but without specifying the memory * transaction attributes to be used. */ void tlb_set_page(CPUState *cpu, target_ulong vaddr, @@ -1633,25 +1655,38 @@ static int probe_access_internal(CPUArchState *env,= target_ulong addr, return flags; } =20 +int probe_access_extra(CPUArchState *env, target_ulong addr, + MMUAccessType access_type, int mmu_idx, + bool nonfault, void **phost, MemTxAttrs *pattrs, + PageEntryExtra *pextra, uintptr_t retaddr) +{ + int flags =3D probe_access_internal(env, addr, 0, access_type, mmu_idx, + nonfault, phost, retaddr); + + if (likely(!(flags & TLB_INVALID_MASK))) { + uintptr_t index =3D tlb_index(env, mmu_idx, addr); + CPUIOTLBEntry *iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[inde= x]; + + /* Handle clean RAM pages. */ + if (unlikely(flags & TLB_NOTDIRTY)) { + notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr); + flags &=3D ~TLB_NOTDIRTY; + } + *pattrs =3D iotlbentry->attrs; + *pextra =3D iotlbentry->extra; + } + return flags; +} + int probe_access_flags(CPUArchState *env, target_ulong addr, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr) { - int flags; + MemTxAttrs attrs; + PageEntryExtra extra; =20 - flags =3D probe_access_internal(env, addr, 0, access_type, mmu_idx, - nonfault, phost, retaddr); - - /* Handle clean RAM pages. */ - if (unlikely(flags & TLB_NOTDIRTY)) { - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUIOTLBEntry *iotlbentry =3D &env_tlb(env)->d[mmu_idx].iotlb[inde= x]; - - notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr); - flags &=3D ~TLB_NOTDIRTY; - } - - return flags; + return probe_access_extra(env, addr, access_type, mmu_idx, nonfault, + phost, &attrs, &extra, retaddr); } =20 void *probe_access(CPUArchState *env, target_ulong addr, int size, --=20 2.34.1