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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656837114836100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/ptw.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 490a57ec5a..f2e429574d 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1347,7 +1347,7 @@ do_fault: =20 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_= idx, - hwaddr *phys_ptr, int *prot, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { int n; @@ -1357,12 +1357,12 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, =20 if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled. */ - *phys_ptr =3D address; - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->phys =3D address; + result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return false; } =20 - *phys_ptr =3D address; + result->phys =3D address; for (n =3D 7; n >=3D 0; n--) { base =3D env->cp15.c6_region[n]; if ((base & 1) =3D=3D 0) { @@ -1398,16 +1398,16 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, fi->level =3D 1; return true; } - *prot =3D PAGE_READ | PAGE_WRITE; + result->prot =3D PAGE_READ | PAGE_WRITE; break; case 2: - *prot =3D PAGE_READ; + result->prot =3D PAGE_READ; if (!is_user) { - *prot |=3D PAGE_WRITE; + result->prot |=3D PAGE_WRITE; } break; case 3: - *prot =3D PAGE_READ | PAGE_WRITE; + result->prot =3D PAGE_READ | PAGE_WRITE; break; case 5: if (is_user) { @@ -1415,10 +1415,10 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, fi->level =3D 1; return true; } - *prot =3D PAGE_READ; + result->prot =3D PAGE_READ; break; case 6: - *prot =3D PAGE_READ; + result->prot =3D PAGE_READ; break; default: /* Bad permission. */ @@ -1426,7 +1426,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, ui= nt32_t address, fi->level =3D 1; return true; } - *prot |=3D PAGE_EXEC; + result->prot |=3D PAGE_EXEC; return false; } =20 @@ -2421,7 +2421,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, } else { /* Pre-v7 MPU */ ret =3D get_phys_addr_pmsav5(env, address, access_type, mmu_id= x, - &result->phys, &result->prot, fi); + result, fi); } qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 " mmu_idx %u -> %s (prot %c%c%c)\n", --=20 2.34.1