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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656837909229100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/ptw.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5e79c9be98..d70c9120fc 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -532,8 +532,7 @@ do_fault: =20 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *pro= t, - target_ulong *page_size, ARMMMUFaultInfo *fi) + GetPhysAddrResult *result, ARMMMUFaultInfo *f= i) { ARMCPU *cpu =3D env_archcpu(env); int level =3D 1; @@ -593,11 +592,11 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, phys_addr =3D (desc & 0xff000000) | (address & 0x00ffffff); phys_addr |=3D (uint64_t)extract32(desc, 20, 4) << 32; phys_addr |=3D (uint64_t)extract32(desc, 5, 4) << 36; - *page_size =3D 0x1000000; + result->page_size =3D 0x1000000; } else { /* Section. */ phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); - *page_size =3D 0x100000; + result->page_size =3D 0x100000; } ap =3D ((desc >> 10) & 3) | ((desc >> 13) & 4); xn =3D desc & (1 << 4); @@ -623,12 +622,12 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, case 1: /* 64k page. */ phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); xn =3D desc & (1 << 15); - *page_size =3D 0x10000; + result->page_size =3D 0x10000; break; case 2: case 3: /* 4k page. */ phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); xn =3D desc & 1; - *page_size =3D 0x1000; + result->page_size =3D 0x1000; break; default: /* Never happens, but compiler isn't smart enough to tell. */ @@ -636,7 +635,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, } } if (domain_prot =3D=3D 3) { - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + result->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; } else { if (pxn && !regime_is_user(env, mmu_idx)) { xn =3D 1; @@ -654,14 +653,14 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32= _t address, fi->type =3D ARMFault_AccessFlag; goto do_fault; } - *prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); + result->prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); } else { - *prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + result->prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); } - if (*prot && !xn) { - *prot |=3D PAGE_EXEC; + if (result->prot && !xn) { + result->prot |=3D PAGE_EXEC; } - if (!(*prot & (1 << access_type))) { + if (!(result->prot & (1 << access_type))) { /* Access permission fault. */ fi->type =3D ARMFault_Permission; goto do_fault; @@ -672,9 +671,9 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t= address, * the CPU doesn't support TZ or this is a non-secure translation * regime, because the attribute will already be non-secure. */ - attrs->secure =3D false; + result->attrs.secure =3D false; } - *phys_ptr =3D phys_addr; + result->phys =3D phys_addr; return false; do_fault: fi->domain =3D domain; @@ -2512,8 +2511,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, result, fi); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, - &result->phys, &result->attrs, - &result->prot, &result->page_size, fi); + result, fi); } else { return get_phys_addr_v5(env, address, access_type, mmu_idx, &result->phys, &result->prot, --=20 2.34.1