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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id im22-20020a170902bb1600b0016a3f9e528asm13569112plb.57.2022.07.03.01.24.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Jul 2022 01:24:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nWhJRX2CcLLqjJLeiFrCW24//WXCOsrf/EygkQpW/6g=; b=MuttzmbSQvnQ4fDjSiKUpl9JiTPG1eNTnxWXj15G3yp6TXpYvXu1W988Ah7Eo1dI2w CSpSBq4mAPaUHqnpsx8OKknvRoTXedMJ8P7/834A9766VCXRmBEhPJiAuhwuNx1qQyIM iQBtnu097NzckEEJiSsaRDQ5EaE7Jq/xa3TfhjZ7FENTTqC11sHt6ZWDlpeoIfp4mjav mPWGWbv3ZiyK8q545xLW6vYQznHnRN88slLeRLXlbKyk9UpXl7ZrM8890I+41fUKh1gE hhB3POkqmyu6wVH1CYBprVLpYq02w0Nko4AJABatxDbjDyr/24XKsGb6lTQdbk/WtYOC 5OOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nWhJRX2CcLLqjJLeiFrCW24//WXCOsrf/EygkQpW/6g=; b=xyBoX9kCpnBZY9ecDRAr/IZ1XG/Y60vK3Z5XCXbgvDHrC3I2zkTKeHmMXZrTcauZdi S5bfyZqw9C4qS9UYIFW4Tx3dXTkuLEmEwc+U1WMXmGMqM7HRjW38HezNSMux5J6PDBuA /Av6trQOH1xSKoML/U6V9ffkN8GgPJpLe3TroUJ7euBvG6w4EkZ5HQax9QJkN1NSvCza TpV++zUoCUsixxy/UyEKXlki/hdOetacTtITc2zTSmZaNCNI1AZJBIGVbSlGUZ2HNdXS RAIapFm284ghdf9nWRRt/ZWpzcc6BLqs512P9ix10J1PQsTgO8lLgSHLnDXSWSieqcIG rnxg== X-Gm-Message-State: AJIora/y7+vaTxddEyR6/jcLpMvw9RshMg1wFB4SG4oqyDZR/0Ua7Kta kt9P8eZ8o9AvGHxFU4SCQF4cDERTHypo6kdQ X-Google-Smtp-Source: AGRyM1u/GxVi9uPP3xxvEt7rZsKVRlJnRWs4nt3znGz+5vWtw7gPFIzTOS1U4EcVc2NBWhoiKtdg+w== X-Received: by 2002:a17:90b:218:b0:1ef:1440:ebe1 with SMTP id fy24-20020a17090b021800b001ef1440ebe1mr28988693pjb.166.1656836695664; Sun, 03 Jul 2022 01:24:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 10/62] target/arm: Use GetPhysAddrResult in get_phys_addr_lpae Date: Sun, 3 Jul 2022 13:53:27 +0530 Message-Id: <20220703082419.770989-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org> References: <20220703082419.770989-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656837764631100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/ptw.c | 69 ++++++++++++++++++------------------------------ 1 file changed, 26 insertions(+), 43 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b78658161f..5e79c9be98 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -16,10 +16,8 @@ =20 static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool s1_is_el0, hwaddr *phys_ptr, - MemTxAttrs *txattrs, int *prot, - target_ulong *page_size_ptr, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs) + bool s1_is_el0, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) __attribute__((nonnull)); =20 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. = */ @@ -204,18 +202,13 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMM= MUIdx mmu_idx, { if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { - target_ulong s2size; - hwaddr s2pa; - int s2prot; - int ret; ARMMMUIdx s2_mmu_idx =3D *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; - ARMCacheAttrs cacheattrs =3D {}; - MemTxAttrs txattrs =3D {}; + GetPhysAddrResult s2 =3D {}; + int ret; =20 ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, f= alse, - &s2pa, &txattrs, &s2prot, &s2size, fi, - &cacheattrs); + &s2, fi); if (ret) { assert(fi->type !=3D ARMFault_None); fi->s2addr =3D addr; @@ -225,7 +218,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, return ~0; } if ((arm_hcr_el2_eff(env) & HCR_PTW) && - ptw_attrs_are_device(env, cacheattrs)) { + ptw_attrs_are_device(env, s2.cacheattrs)) { /* * PTW set and S1 walk touched S2 Device memory: * generate Permission fault. @@ -249,7 +242,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMU= Idx mmu_idx, assert(!*is_secure); } =20 - addr =3D s2pa; + addr =3D s2.phys; } return addr; } @@ -968,19 +961,13 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_a= a64, int level, * table walk), must be true if this is stage 2 of a stage 1+2 * walk for an EL0 access. If @mmu_idx is anything else, * @s1_is_el0 is ignored. - * @phys_ptr: set to the physical address corresponding to the virtual add= ress - * @attrs: set to the memory transaction attributes to use - * @prot: set to the permissions for the page containing phys_ptr - * @page_size_ptr: set to the size of the page containing phys_ptr + * @result: set on translation success, * @fi: set to fault info if the translation fails - * @cacheattrs: (if non-NULL) set to the cacheability/shareability attribu= tes */ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool s1_is_el0, hwaddr *phys_ptr, - MemTxAttrs *txattrs, int *prot, - target_ulong *page_size_ptr, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs) + bool s1_is_el0, GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) { ARMCPU *cpu =3D env_archcpu(env); /* Read an LPAE long-descriptor translation table. */ @@ -1298,16 +1285,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; xn =3D extract32(attrs, 11, 2); - *prot =3D get_S2prot(env, ap, xn, s1_is_el0); + result->prot =3D get_S2prot(env, ap, xn, s1_is_el0); } else { ns =3D extract32(attrs, 3, 1); xn =3D extract32(attrs, 12, 1); pxn =3D extract32(attrs, 11, 1); - *prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); + result->prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn= ); } =20 fault_type =3D ARMFault_Permission; - if (!(*prot & (1 << access_type))) { + if (!(result->prot & (1 << access_type))) { goto do_fault; } =20 @@ -1317,23 +1304,23 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, * the CPU doesn't support TZ or this is a non-secure translation * regime, because the attribute will already be non-secure. */ - txattrs->secure =3D false; + result->attrs.secure =3D false; } /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB.= */ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { - cacheattrs->guarded =3D guarded; + result->cacheattrs.guarded =3D guarded; } =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { - cacheattrs->is_s2_format =3D true; - cacheattrs->attrs =3D extract32(attrs, 0, 4); + result->cacheattrs.is_s2_format =3D true; + result->cacheattrs.attrs =3D extract32(attrs, 0, 4); } else { /* Index into MAIR registers for cache attributes */ uint8_t attrindx =3D extract32(attrs, 0, 3); uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; assert(attrindx <=3D 7); - cacheattrs->is_s2_format =3D false; - cacheattrs->attrs =3D extract64(mair, attrindx * 8, 8); + result->cacheattrs.is_s2_format =3D false; + result->cacheattrs.attrs =3D extract64(mair, attrindx * 8, 8); } =20 /* @@ -1342,13 +1329,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, * that case comes from TCR_ELx, which we extracted earlier. */ if (param.ds) { - cacheattrs->shareability =3D param.sh; + result->cacheattrs.shareability =3D param.sh; } else { - cacheattrs->shareability =3D extract32(attrs, 6, 2); + result->cacheattrs.shareability =3D extract32(attrs, 6, 2); } =20 - *phys_ptr =3D descaddr; - *page_size_ptr =3D page_size; + result->phys =3D descaddr; + result->page_size =3D page_size; return false; =20 do_fault: @@ -2350,10 +2337,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, cacheattrs1 =3D result->cacheattrs; memset(result, 0, sizeof(*result)); =20 - ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, = is_el0, - &result->phys, &result->attrs, - &result->prot, &result->page_size, - fi, &result->cacheattrs); + ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, + is_el0, result, fi); fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ @@ -2524,9 +2509,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, =20 if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, fals= e, - &result->phys, &result->attrs, - &result->prot, &result->page_size, - fi, &result->cacheattrs); + result, fi); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, &result->phys, &result->attrs, --=20 2.34.1