From nobody Mon Feb 9 14:37:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1656692091; cv=none; d=zohomail.com; s=zohoarc; b=VhjGKq1dQHB2n9kG58N91cOXCPOEgDcnqVm5FuF7QYaK/RslSVKr8+xO08Dqg8HeQSvrpFRWg3LDOatiac9ZgGmC7wxs+kI9ZFIPuSAyLLMoAuKwb8deYMsFe1dqZFGXlEAIV2AFnpzjnCt2+3jAGDUXvX4PxUP6i5dfrjJWyds= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1656692091; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=l4j53TXvpMUQL1XYG2KLBZYfAFqLkalOnb8qfF7Pa9Q=; b=hDEkp3HislSx/DeyHW7hb8xoJ2nqoyGX10nb7ytHwVPHqTcRfhJGXHNjMg+bLM7REX4T0o+M8EA49FTpiexIUjM4u64oyzMarH0iF453pynMoB1jH8ghKKfJhGG7V/5gQLnWFBR3kVhEIipAwmfCm+lLKNU2MyCSIqYRm9Sz11Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656692091984341.11804087362475; Fri, 1 Jul 2022 09:14:51 -0700 (PDT) Received: from localhost ([::1]:48416 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o7JIA-0005sy-WB for importer@patchew.org; Fri, 01 Jul 2022 12:14:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46810) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o7JET-0008TN-Sg for qemu-devel@nongnu.org; Fri, 01 Jul 2022 12:11:01 -0400 Received: from mx0a-00069f02.pphosted.com ([205.220.165.32]:25048) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o7JEO-000245-DO for qemu-devel@nongnu.org; Fri, 01 Jul 2022 12:10:58 -0400 Received: from pps.filterd (m0246617.ppops.net [127.0.0.1]) by mx0b-00069f02.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 261G3O2c021265; Fri, 1 Jul 2022 16:10:46 GMT Received: from phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta03.appoci.oracle.com [138.1.37.129]) by mx0b-00069f02.pphosted.com (PPS) with ESMTPS id 3gwtwufraf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 01 Jul 2022 16:10:46 +0000 Received: from pps.filterd (phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (8.16.1.2/8.16.1.2) with SMTP id 261G5hDQ016077; Fri, 1 Jul 2022 16:10:46 GMT Received: from pps.reinject (localhost [127.0.0.1]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com with ESMTP id 3gwrt4svxf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 01 Jul 2022 16:10:46 +0000 Received: from phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 261GAftE029065; Fri, 1 Jul 2022 16:10:45 GMT Received: from paddy.uk.oracle.com (dhcp-10-175-184-247.vpn.oracle.com [10.175.184.247]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com with ESMTP id 3gwrt4svtm-2; Fri, 01 Jul 2022 16:10:45 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2021-07-09; bh=l4j53TXvpMUQL1XYG2KLBZYfAFqLkalOnb8qfF7Pa9Q=; b=hz7gupflXo41o+nE+uZR0+Ei0l3hQTEpXyb2aYrCSIA5cTTh3t/b2EOuzJQ8P0zHKwgj HRARESMDaRFwMC1NY3a+5qbFm6oYi8o8Tvc8quxbXu6RgLFxN21aG4gDmtpie8bV4ULc Th/agqKH/XwgkKR5fmqmQ6cogUJHiODSXcpuZD0IkrL9FjyqD+Wj4gxnamhZtIJtUS/l Ev/dpX3V3Fa/I1+gYz1JO1zL2bnAsfWtQcqBc0Ih9l7jZBATa2EsXKk1/I73alrwWFQ/ qUg50sld9DhsxXPnTTFu3UmGfgbEidjoHzCKml0QI6+jf1x3D6SeHRH4rgPgH7AuHYI4 Ng== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins Subject: [PATCH v6 01/10] hw/i386: add 4g boundary start to X86MachineState Date: Fri, 1 Jul 2022 17:10:05 +0100 Message-Id: <20220701161014.3850-2-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220701161014.3850-1-joao.m.martins@oracle.com> References: <20220701161014.3850-1-joao.m.martins@oracle.com> X-Proofpoint-ORIG-GUID: 2kgZG3lg3Ds_Af_U0smC3UM_ljlQpW8g X-Proofpoint-GUID: 2kgZG3lg3Ds_Af_U0smC3UM_ljlQpW8g Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.165.32; envelope-from=joao.m.martins@oracle.com; helo=mx0a-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1656692094098100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than hardcoding the 4G boundary everywhere, introduce a X86MachineState field @above_4g_mem_start and use it accordingly. This is in preparation for relocating ram-above-4g to be dynamically start at 1T on AMD platforms. Signed-off-by: Joao Martins Reviewed-by: Igor Mammedov --- hw/i386/acpi-build.c | 2 +- hw/i386/pc.c | 11 ++++++----- hw/i386/sgx.c | 2 +- hw/i386/x86.c | 1 + include/hw/i386/x86.h | 3 +++ 5 files changed, 12 insertions(+), 7 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index cad6f5ac41e9..0355bd3ddaad 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -2024,7 +2024,7 @@ build_srat(GArray *table_data, BIOSLinker *linker, Ma= chineState *machine) build_srat_memory(table_data, mem_base, mem_len, i - 1, MEM_AFFINITY_ENABLED); } - mem_base =3D 1ULL << 32; + mem_base =3D x86ms->above_4g_mem_start; mem_len =3D next_base - x86ms->below_4g_mem_size; next_base =3D mem_base + mem_len; } diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 774cb2bf0748..a9d1bf95649a 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -850,9 +850,10 @@ void pc_memory_init(PCMachineState *pcms, machine->ram, x86ms->below_4g_mem_size, x86ms->above_4g_mem_size); - memory_region_add_subregion(system_memory, 0x100000000ULL, + memory_region_add_subregion(system_memory, x86ms->above_4g_mem_sta= rt, ram_above_4g); - e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); + e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, + E820_RAM); } =20 if (pcms->sgx_epc.size !=3D 0) { @@ -893,7 +894,7 @@ void pc_memory_init(PCMachineState *pcms, machine->device_memory->base =3D sgx_epc_above_4g_end(&pcms->s= gx_epc); } else { machine->device_memory->base =3D - 0x100000000ULL + x86ms->above_4g_mem_size; + x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; } =20 machine->device_memory->base =3D @@ -929,7 +930,7 @@ void pc_memory_init(PCMachineState *pcms, } else if (pcms->sgx_epc.size !=3D 0) { cxl_base =3D sgx_epc_above_4g_end(&pcms->sgx_epc); } else { - cxl_base =3D 0x100000000ULL + x86ms->above_4g_mem_size; + cxl_base =3D x86ms->above_4g_mem_start + x86ms->above_4g_mem_s= ize; } =20 e820_add_entry(cxl_base, cxl_size, E820_RESERVED); @@ -1037,7 +1038,7 @@ uint64_t pc_pci_hole64_start(void) } else if (pcms->sgx_epc.size !=3D 0) { hole64_start =3D sgx_epc_above_4g_end(&pcms->sgx_epc); } else { - hole64_start =3D 0x100000000ULL + x86ms->above_4g_mem_size; + hole64_start =3D x86ms->above_4g_mem_start + x86ms->above_4g_mem_s= ize; } =20 return ROUND_UP(hole64_start, 1 * GiB); diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c index a44d66ba2afc..09d9c7c73d9f 100644 --- a/hw/i386/sgx.c +++ b/hw/i386/sgx.c @@ -295,7 +295,7 @@ void pc_machine_init_sgx_epc(PCMachineState *pcms) return; } =20 - sgx_epc->base =3D 0x100000000ULL + x86ms->above_4g_mem_size; + sgx_epc->base =3D x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; =20 memory_region_init(&sgx_epc->mr, OBJECT(pcms), "sgx-epc", UINT64_MAX); memory_region_add_subregion(get_system_memory(), sgx_epc->base, diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 6003b4b2dfea..029264c54fe2 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -1373,6 +1373,7 @@ static void x86_machine_initfn(Object *obj) x86ms->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); x86ms->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); x86ms->bus_lock_ratelimit =3D 0; + x86ms->above_4g_mem_start =3D 4 * GiB; } =20 static void x86_machine_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index 9089bdd99c3a..df82c5fd4252 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -56,6 +56,9 @@ struct X86MachineState { /* RAM information (sizes, addresses, configuration): */ ram_addr_t below_4g_mem_size, above_4g_mem_size; =20 + /* Start address of the initial RAM above 4G */ + uint64_t above_4g_mem_start; + /* CPU and apic information: */ bool apic_xrupt_override; unsigned pci_irq_mask; --=20 2.17.2 From nobody Mon Feb 9 14:37:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1656692057; cv=none; d=zohomail.com; s=zohoarc; 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s=corp-2021-07-09; bh=fRUaM6BoTCnpEt8yk7mTglXXc901MlgM1s5jUyNf8tE=; b=m3NAWtyzAzg3EBbmDbaDd0FSGukoqIrJ1B/1geZ+CIhRwqqSrk7cvrpOHH0zU6uUdpTK AampiCipSeJNa85QgXL9Qpf7LO9r84Eh6LmJuhI9sdo4A083aYTfimCKP4eKXnis63GG 8IVZizPv3GGBYAFFpG5Q8wcIATCoO6imOYWc7A9tjnz6RuzPwSzAxgMv/rNWyifkbnDG FGi5LptjGryHfJWn21HJW0bdhNsC1aeBur7eY1piIg/kYf/mSaXNnx1CyCetlFTFYF2u p+9Ra3Xq4B5e7Rt04IpUbh1lxPSO/R9pRFLjczpzwDUN0VUI+aAhCFPTqHIfcBcYK9ZZ Jg== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins Subject: [PATCH v6 02/10] i386/pc: create pci-host qdev prior to pc_memory_init() Date: Fri, 1 Jul 2022 17:10:06 +0100 Message-Id: <20220701161014.3850-3-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220701161014.3850-1-joao.m.martins@oracle.com> References: <20220701161014.3850-1-joao.m.martins@oracle.com> X-Proofpoint-ORIG-GUID: JE0Hd52pvjP57WBrWC9EX5iKzMvAug1t X-Proofpoint-GUID: JE0Hd52pvjP57WBrWC9EX5iKzMvAug1t Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=joao.m.martins@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1656692059913100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" At the start of pc_memory_init() we usually pass a range of 0..UINT64_MAX as pci_memory, when really its 2G (i440fx) or 32G (q35). To get the real user value, we need to get pci-host passed property for default pci_hole64_size. Thus to get that, create the qdev prior to memory init to better make estimations on max used/phys addr. This is in preparation to determine that host-phys-bits are enough and also for pci-hole64-size to be considered to relocate ram-above-4g to be at 1T (on AMD platforms). Signed-off-by: Joao Martins Reviewed-by: Igor Mammedov --- hw/i386/pc_piix.c | 7 +++++-- hw/i386/pc_q35.c | 6 +++--- hw/pci-host/i440fx.c | 5 ++--- include/hw/pci-host/i440fx.h | 3 ++- 4 files changed, 12 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index a234989ac363..6186a1473755 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -91,6 +91,7 @@ static void pc_init1(MachineState *machine, MemoryRegion *pci_memory; MemoryRegion *rom_memory; ram_addr_t lowmem; + DeviceState *i440fx_host; =20 /* * Calculate ram split, for memory below and above 4G. It's a bit @@ -164,9 +165,11 @@ static void pc_init1(MachineState *machine, pci_memory =3D g_new(MemoryRegion, 1); memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); rom_memory =3D pci_memory; + i440fx_host =3D qdev_new(host_type); } else { pci_memory =3D NULL; rom_memory =3D system_memory; + i440fx_host =3D NULL; } =20 pc_guest_info_init(pcms); @@ -200,8 +203,8 @@ static void pc_init1(MachineState *machine, const char *type =3D xen_enabled() ? TYPE_PIIX3_XEN_DEVICE : TYPE_PIIX3_DEVICE; =20 - pci_bus =3D i440fx_init(host_type, - pci_type, + pci_bus =3D i440fx_init(pci_type, + i440fx_host, system_memory, system_io, machine->ram_size, x86ms->below_4g_mem_size, x86ms->above_4g_mem_size, diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index f96cbd04e284..46ea89e564de 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -203,12 +203,12 @@ static void pc_q35_init(MachineState *machine) pcms->smbios_entry_point_type); } =20 - /* allocate ram and load rom/bios */ - pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory); - /* create pci host bus */ q35_host =3D Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE)); =20 + /* allocate ram and load rom/bios */ + pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory); + object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host)); object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM, OBJECT(ram_memory), NULL); diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c index 1c5ad5f918a2..d5426ef4a53c 100644 --- a/hw/pci-host/i440fx.c +++ b/hw/pci-host/i440fx.c @@ -237,7 +237,8 @@ static void i440fx_realize(PCIDevice *dev, Error **errp) } } =20 -PCIBus *i440fx_init(const char *host_type, const char *pci_type, +PCIBus *i440fx_init(const char *pci_type, + DeviceState *dev, MemoryRegion *address_space_mem, MemoryRegion *address_space_io, ram_addr_t ram_size, @@ -246,7 +247,6 @@ PCIBus *i440fx_init(const char *host_type, const char *= pci_type, MemoryRegion *pci_address_space, MemoryRegion *ram_memory) { - DeviceState *dev; PCIBus *b; PCIDevice *d; PCIHostState *s; @@ -254,7 +254,6 @@ PCIBus *i440fx_init(const char *host_type, const char *= pci_type, unsigned i; I440FXState *i440fx; =20 - dev =3D qdev_new(host_type); s =3D PCI_HOST_BRIDGE(dev); b =3D pci_root_bus_new(dev, NULL, pci_address_space, address_space_io, 0, TYPE_PCI_BUS); diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h index 52518dbf08e6..d02bf1ed6b93 100644 --- a/include/hw/pci-host/i440fx.h +++ b/include/hw/pci-host/i440fx.h @@ -35,7 +35,8 @@ struct PCII440FXState { =20 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" =20 -PCIBus *i440fx_init(const char *host_type, const char *pci_type, +PCIBus *i440fx_init(const char *pci_type, + DeviceState *dev, MemoryRegion *address_space_mem, MemoryRegion *address_space_io, ram_addr_t ram_size, --=20 2.17.2 From nobody Mon Feb 9 14:37:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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s=corp-2021-07-09; bh=z+z27MuS4laK8hOrevo85qcYt+7RV4yIWeCTw+GvVWs=; b=cOBns+OfnbpwTNvegSF1XHptZp/1tOdviTms7Tfl5GZuaoB8HciO8NgANBjcpJcIPhe9 AblEw/FmlTMovZtUYlTydBKQp27Csfpiu3Js8K0vv7IXcVZGb814fZcNizzWXNuOjnnm xkEQLG9cp4c4a95DP3AC/HZ2s3efQQgkHKbSmoF8yfQmC8j7FE3bEJLEV/oa27VKuMcS 6JIqmOqEiLuW0b4pg2Y67vF/citVHYxW8mMEKFc1+vQmVOVDGzzBN/IE1jzS17wivTPs aH2BRYlEGlG1Jw2xLXSUY1q25Bb/77Bj3+usWMVhu9QSm6INXt9+xLHLKN1u7yAqTb7T MA== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins Subject: [PATCH v6 03/10] i386/pc: pass pci_hole64_size to pc_memory_init() Date: Fri, 1 Jul 2022 17:10:07 +0100 Message-Id: <20220701161014.3850-4-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220701161014.3850-1-joao.m.martins@oracle.com> References: <20220701161014.3850-1-joao.m.martins@oracle.com> X-Proofpoint-ORIG-GUID: KDj-HXEl_O1D9bWrRCMDZfLN9_xF2_4v X-Proofpoint-GUID: KDj-HXEl_O1D9bWrRCMDZfLN9_xF2_4v Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.165.32; envelope-from=joao.m.martins@oracle.com; helo=mx0a-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1656692311525100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use the pre-initialized pci-host qdev and fetch the pci-hole64-size into pc_memory_init() newly added argument. piix needs a bit of care given all the !pci_enabled() and that the pci_hole64_size is private to i440fx. This is in preparation to determine that host-phys-bits are enough and for pci-hole64-size to be considered to relocate ram-above-4g to be at 1T (on AMD platforms). Signed-off-by: Joao Martins Reviewed-by: Igor Mammedov --- hw/i386/pc.c | 3 ++- hw/i386/pc_piix.c | 5 ++++- hw/i386/pc_q35.c | 8 +++++++- hw/pci-host/i440fx.c | 7 +++++++ include/hw/i386/pc.h | 3 ++- include/hw/pci-host/i440fx.h | 1 + 6 files changed, 23 insertions(+), 4 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index a9d1bf95649a..1bb89a9c17ec 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -817,7 +817,8 @@ void xen_load_linux(PCMachineState *pcms) void pc_memory_init(PCMachineState *pcms, MemoryRegion *system_memory, MemoryRegion *rom_memory, - MemoryRegion **ram_memory) + MemoryRegion **ram_memory, + uint64_t pci_hole64_size) { int linux_boot, i; MemoryRegion *option_rom_mr; diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 6186a1473755..f3c726e42400 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -91,6 +91,7 @@ static void pc_init1(MachineState *machine, MemoryRegion *pci_memory; MemoryRegion *rom_memory; ram_addr_t lowmem; + uint64_t hole64_size; DeviceState *i440fx_host; =20 /* @@ -166,10 +167,12 @@ static void pc_init1(MachineState *machine, memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); rom_memory =3D pci_memory; i440fx_host =3D qdev_new(host_type); + hole64_size =3D i440fx_pci_hole64_size(i440fx_host); } else { pci_memory =3D NULL; rom_memory =3D system_memory; i440fx_host =3D NULL; + hole64_size =3D 0; } =20 pc_guest_info_init(pcms); @@ -186,7 +189,7 @@ static void pc_init1(MachineState *machine, /* allocate ram and load rom/bios */ if (!xen_enabled()) { pc_memory_init(pcms, system_memory, - rom_memory, &ram_memory); + rom_memory, &ram_memory, hole64_size); } else { pc_system_flash_cleanup_unused(pcms); if (machine->kernel_filename !=3D NULL) { diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 46ea89e564de..5a4a737fe203 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -138,6 +138,7 @@ static void pc_q35_init(MachineState *machine) MachineClass *mc =3D MACHINE_GET_CLASS(machine); bool acpi_pcihp; bool keep_pci_slot_hpc; + uint64_t pci_hole64_size =3D 0; =20 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping @@ -206,8 +207,13 @@ static void pc_q35_init(MachineState *machine) /* create pci host bus */ q35_host =3D Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE)); =20 + if (pcmc->pci_enabled) { + pci_hole64_size =3D q35_host->mch.pci_hole64_size; + } + /* allocate ram and load rom/bios */ - pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory); + pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory, + pci_hole64_size); =20 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host)); object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM, diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c index d5426ef4a53c..15680da7d709 100644 --- a/hw/pci-host/i440fx.c +++ b/hw/pci-host/i440fx.c @@ -237,6 +237,13 @@ static void i440fx_realize(PCIDevice *dev, Error **err= p) } } =20 +uint64_t i440fx_pci_hole64_size(DeviceState *i440fx_dev) +{ + I440FXState *i440fx =3D I440FX_PCI_HOST_BRIDGE(i440fx_dev); + + return i440fx->pci_hole64_size; +} + PCIBus *i440fx_init(const char *pci_type, DeviceState *dev, MemoryRegion *address_space_mem, diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index b7735dccfc81..568c226d3034 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -159,7 +159,8 @@ void xen_load_linux(PCMachineState *pcms); void pc_memory_init(PCMachineState *pcms, MemoryRegion *system_memory, MemoryRegion *rom_memory, - MemoryRegion **ram_memory); + MemoryRegion **ram_memory, + uint64_t pci_hole64_size); uint64_t pc_pci_hole64_start(void); DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); void pc_basic_device_init(struct PCMachineState *pcms, diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h index d02bf1ed6b93..2234dd5a2a6a 100644 --- a/include/hw/pci-host/i440fx.h +++ b/include/hw/pci-host/i440fx.h @@ -45,5 +45,6 @@ PCIBus *i440fx_init(const char *pci_type, MemoryRegion *pci_memory, MemoryRegion *ram_memory); =20 +uint64_t i440fx_pci_hole64_size(DeviceState *i440fx_dev); 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Fri, 1 Jul 2022 16:10:57 GMT Received: from paddy.uk.oracle.com (dhcp-10-175-184-247.vpn.oracle.com [10.175.184.247]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com with ESMTP id 3gwrt4svtm-5; Fri, 01 Jul 2022 16:10:56 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2021-07-09; bh=/fOjQMvb2Uf1FvJO1CQiRWrUOJHH4ZD8LgRZRaf/fpc=; b=K123vNEtN/PBc5+q6BD6evdIb+JL6BKeLtDILyZ5wURw5/c+rja6CpAx/Z4sUZqb7Z/0 aiNYFGZFBYySZQW3SHdTm6aYidbCVWoNpBdTAyiM+BhEPNoRDjNxozMWbLhR63VCY5fU JoFahMZ25NJHjnYxsUjac4nD3NmyJ32yMoer9TlfKs7mooxMJrGXtZXDNoooBII7AeYZ /D5kft9I6wyiCgSvU/ASU5NolTcYtMNmo92KN/pMH/nV1zN1gGEM2HAKCnUcWfq/epad t7WH3O/UecNnfMXjehKXeWhSlSmOjHe5660EjJ4B/qlFLLanckBTnaR3K22jL0J+LCgj fQ== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins Subject: [PATCH v6 04/10] i386/pc: factor out above-4g end to an helper Date: Fri, 1 Jul 2022 17:10:08 +0100 Message-Id: <20220701161014.3850-5-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220701161014.3850-1-joao.m.martins@oracle.com> References: <20220701161014.3850-1-joao.m.martins@oracle.com> X-Proofpoint-ORIG-GUID: W14OQlREpPXvHIUAN3ngYx81UyLcgCH_ X-Proofpoint-GUID: W14OQlREpPXvHIUAN3ngYx81UyLcgCH_ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=joao.m.martins@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1656692437837100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There's a couple of places that seem to duplicate this calculation of RAM size above the 4G boundary. Move all those to a helper function. Signed-off-by: Joao Martins Reviewed-by: Igor Mammedov --- hw/i386/pc.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 1bb89a9c17ec..6c7c49ca5a32 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -814,6 +814,17 @@ void xen_load_linux(PCMachineState *pcms) #define PC_ROM_ALIGN 0x800 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) =20 +static hwaddr pc_above_4g_end(PCMachineState *pcms) +{ + X86MachineState *x86ms =3D X86_MACHINE(pcms); + + if (pcms->sgx_epc.size !=3D 0) { + return sgx_epc_above_4g_end(&pcms->sgx_epc); + } + + return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; +} + void pc_memory_init(PCMachineState *pcms, MemoryRegion *system_memory, MemoryRegion *rom_memory, @@ -891,15 +902,8 @@ void pc_memory_init(PCMachineState *pcms, exit(EXIT_FAILURE); } =20 - if (pcms->sgx_epc.size !=3D 0) { - machine->device_memory->base =3D sgx_epc_above_4g_end(&pcms->s= gx_epc); - } else { - machine->device_memory->base =3D - x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; - } - machine->device_memory->base =3D - ROUND_UP(machine->device_memory->base, 1 * GiB); + ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); =20 if (pcmc->enforce_aligned_dimm) { /* size device region assuming 1G page max alignment per slot = */ @@ -928,10 +932,8 @@ void pc_memory_init(PCMachineState *pcms, if (!pcmc->broken_reserved_end) { cxl_base +=3D memory_region_size(&machine->device_memory->= mr); } - } else if (pcms->sgx_epc.size !=3D 0) { - cxl_base =3D sgx_epc_above_4g_end(&pcms->sgx_epc); } else { - cxl_base =3D x86ms->above_4g_mem_start + x86ms->above_4g_mem_s= ize; + cxl_base =3D pc_above_4g_end(pcms); } =20 e820_add_entry(cxl_base, cxl_size, E820_RESERVED); @@ -1018,7 +1020,6 @@ uint64_t pc_pci_hole64_start(void) PCMachineState *pcms =3D PC_MACHINE(qdev_get_machine()); PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); MachineState *ms =3D MACHINE(pcms); - X86MachineState *x86ms =3D X86_MACHINE(pcms); uint64_t hole64_start =3D 0; =20 if (pcms->cxl_devices_state.host_mr.addr) { @@ -1036,10 +1037,8 @@ uint64_t pc_pci_hole64_start(void) if (!pcmc->broken_reserved_end) { hole64_start +=3D memory_region_size(&ms->device_memory->mr); } - } else if (pcms->sgx_epc.size !=3D 0) { - hole64_start =3D sgx_epc_above_4g_end(&pcms->sgx_epc); } else { - hole64_start =3D x86ms->above_4g_mem_start + x86ms->above_4g_mem_s= ize; + hole64_start =3D pc_above_4g_end(pcms); } =20 return ROUND_UP(hole64_start, 1 * GiB); --=20 2.17.2 From nobody Mon Feb 9 14:37:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1656692525; cv=none; d=zohomail.com; s=zohoarc; b=AvHZRGAheeA+jZGngZapOxuejhh1OU7uBoFDFI/gp8DF/R7VoPd4phqJ1FmR73B0xVU+OoDGI7gXJxFXxeb3H+fokeBZ+ovH0eGa7hcgD5dlvFMHULF7AOnMWfPxDBxrJiDS74ea0DEgl9KADwiv7HghMtJ9S6SN08Qelpl81DU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1656692525; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; 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Fri, 01 Jul 2022 16:11:01 +0000 Received: from phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 261GAftM029065; Fri, 1 Jul 2022 16:11:01 GMT Received: from paddy.uk.oracle.com (dhcp-10-175-184-247.vpn.oracle.com [10.175.184.247]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com with ESMTP id 3gwrt4svtm-6; Fri, 01 Jul 2022 16:11:00 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2021-07-09; bh=V5IBKjj/BgWoWCYG9hxiuVLSiFR1zl8HACZUbFc6czw=; b=qcH+/i9+/+EZrnRZuT5QJtSgmJBSWW7SBjMRtl8er3M3Mq9Z9RECc81dj/s8bHXD75G4 qNKeVv7vjTl1OsgAhDfyVJYp02qdI4SbWYvoLw9JuX+BblXWxmy3NYpIkX7wHU1oadni v5d2QDYstTALAbHvtY0nJWG7WWkAxCgU6KNOFTzbo3c970hWde/Y+aDKIy1cXRx2IqRV LjaBL00diJfLm/zY5y9oy61bnvAGCqAqlGovHpy72A4PfcikiGqHeS+ZMImhi7xiCvRx MlQyg335R1w3NPTF23JcONSJrmz4qK7jn9RZxRQCmnZrxXM6lXqPUF0u1cCWfNQeRIBT Gw== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins , Jonathan Cameron Subject: [PATCH v6 05/10] i386/pc: factor out cxl range end to helper Date: Fri, 1 Jul 2022 17:10:09 +0100 Message-Id: <20220701161014.3850-6-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220701161014.3850-1-joao.m.martins@oracle.com> References: <20220701161014.3850-1-joao.m.martins@oracle.com> X-Proofpoint-ORIG-GUID: h3ARozB3j0mA_GvZJbjcJ23LX_K0QCqb X-Proofpoint-GUID: h3ARozB3j0mA_GvZJbjcJ23LX_K0QCqb Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=joao.m.martins@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1656692526237100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move calculation of CXL memory region end to separate helper in preparation to allow pc_pci_hole64_start() to be called before any mrs are initialized. Cc: Jonathan Cameron Signed-off-by: Joao Martins --- hw/i386/pc.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 6c7c49ca5a32..0abbf81841a9 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -825,6 +825,25 @@ static hwaddr pc_above_4g_end(PCMachineState *pcms) return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; } =20 +static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) +{ + uint64_t start =3D 0; + + if (pcms->cxl_devices_state.host_mr.addr) { + start =3D pcms->cxl_devices_state.host_mr.addr + + memory_region_size(&pcms->cxl_devices_state.host_mr); + if (pcms->cxl_devices_state.fixed_windows) { + GList *it; + for (it =3D pcms->cxl_devices_state.fixed_windows; it; it =3D = it->next) { + CXLFixedWindow *fw =3D it->data; + start =3D fw->mr.addr + memory_region_size(&fw->mr); + } + } + } + + return start; +} + void pc_memory_init(PCMachineState *pcms, MemoryRegion *system_memory, MemoryRegion *rom_memory, @@ -1022,16 +1041,8 @@ uint64_t pc_pci_hole64_start(void) MachineState *ms =3D MACHINE(pcms); uint64_t hole64_start =3D 0; =20 - if (pcms->cxl_devices_state.host_mr.addr) { - hole64_start =3D pcms->cxl_devices_state.host_mr.addr + - memory_region_size(&pcms->cxl_devices_state.host_mr); - if (pcms->cxl_devices_state.fixed_windows) { - GList *it; - for (it =3D pcms->cxl_devices_state.fixed_windows; it; it =3D = it->next) { - CXLFixedWindow *fw =3D it->data; - hole64_start =3D fw->mr.addr + memory_region_size(&fw->mr); - } - } + if (pcms->cxl_devices_state.is_enabled) { + hole64_start =3D pc_get_cxl_range_end(pcms); } else if (pcmc->has_reserved_memory && ms->device_memory->base) { hole64_start =3D ms->device_memory->base; if (!pcmc->broken_reserved_end) { --=20 2.17.2 From nobody Mon Feb 9 14:37:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; 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s=corp-2021-07-09; bh=O4pTTLxZV+n0/VuPRBbRciJ+yiI5rPj2CVwAg/SdhcE=; b=c/QLCaeAICXDXebPrtvSVRcHNPowJ5Ja07994doxyFJouvhTppYnw/I0kI2p/YJxAkJC xAzEuBxaDC7KIYoOfQRhNNWhcN3IInIJWmsPb71+qjNNi5IOP0/ZYMaUs9fHYlilnN5f szSGM80Icl8fqEL4Wy8AJpkK4l9BsRXmb2IKF4AmlkeSwoGz+rkLgGhtPbJ9M8KKYGb1 t4VjN6X0PRhxFt/sVf2cqQPjlRJRtw8YfZp7+KNBCB4m+vEMfzlT98DlLAksx+0OP4C8 xj6wTaLIPnbhzKyKAvlKqDTJQf05U8AwXre4UFzxGS1MAGneWQV99FuVwuwQ8bOrB8B+ iA== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins , Jonathan Cameron Subject: [PATCH v6 06/10] i386/pc: factor out cxl range start to helper Date: Fri, 1 Jul 2022 17:10:10 +0100 Message-Id: <20220701161014.3850-7-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220701161014.3850-1-joao.m.martins@oracle.com> References: <20220701161014.3850-1-joao.m.martins@oracle.com> X-Proofpoint-ORIG-GUID: 76_xH_wqoQTg3jlpckUgWri9EaxnUiaR X-Proofpoint-GUID: 76_xH_wqoQTg3jlpckUgWri9EaxnUiaR Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=joao.m.martins@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1656692819991100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Factor out the calculation of the base address of the MR. It will be used later on for the cxl range end counterpart calculation and as well in pc_memory_init() CXL mr initialization, thus avoiding duplication. Cc: Jonathan Cameron Signed-off-by: Joao Martins --- hw/i386/pc.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 0abbf81841a9..8655cc3b8894 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -825,6 +825,24 @@ static hwaddr pc_above_4g_end(PCMachineState *pcms) return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; } =20 +static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) +{ + PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); + MachineState *machine =3D MACHINE(pcms); + hwaddr cxl_base; + + if (pcmc->has_reserved_memory && machine->device_memory->base) { + cxl_base =3D machine->device_memory->base; + if (!pcmc->broken_reserved_end) { + cxl_base +=3D memory_region_size(&machine->device_memory->mr); + } + } else { + cxl_base =3D pc_above_4g_end(pcms); + } + + return cxl_base; +} + static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) { uint64_t start =3D 0; @@ -946,15 +964,7 @@ void pc_memory_init(PCMachineState *pcms, MemoryRegion *mr =3D &pcms->cxl_devices_state.host_mr; hwaddr cxl_size =3D MiB; =20 - if (pcmc->has_reserved_memory && machine->device_memory->base) { - cxl_base =3D machine->device_memory->base; - if (!pcmc->broken_reserved_end) { - cxl_base +=3D memory_region_size(&machine->device_memory->= mr); - } - } else { - cxl_base =3D pc_above_4g_end(pcms); - } - + cxl_base =3D pc_get_cxl_range_start(pcms); e820_add_entry(cxl_base, cxl_size, E820_RESERVED); memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); memory_region_add_subregion(system_memory, cxl_base, mr); --=20 2.17.2 From nobody Mon Feb 9 14:37:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1656693022; cv=none; d=zohomail.com; s=zohoarc; b=FMnREQx2qlFcYrtskrqfEtZPGezW8yeCorJofoodG77g7sagSByiiC0yYAXIEu5WHuOuUC5wUMmJr1ctJLu8A3DHF8HKxatdYQ7cdmK04Lh1RoFb7kp2HxEUUDAfpxaZgFyL49mSS+CscNuh1Waj6gZTMtzhU7dnfcamVHh5q78= ARC-Message-Signature: i=1; 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Fri, 1 Jul 2022 16:11:09 GMT Received: from pps.reinject (localhost [127.0.0.1]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com with ESMTP id 3gwrt4sw8j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 01 Jul 2022 16:11:09 +0000 Received: from phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 261GAftQ029065; Fri, 1 Jul 2022 16:11:09 GMT Received: from paddy.uk.oracle.com (dhcp-10-175-184-247.vpn.oracle.com [10.175.184.247]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com with ESMTP id 3gwrt4svtm-8; Fri, 01 Jul 2022 16:11:08 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2021-07-09; bh=VJlmpe4pYK56nIEHjuZWkSH5o0PHsSFuupV7x9j3pJ4=; b=tUthhc4ZnuAD23cgC1dxihfT0zruFf47wvaBCRd+P+IkV3YvaTLS1jHDpwdtw74VQELH N6r8ylkFvyxHZnwTaWMDehg7jV7okolfw6hmamGj5HXjkggluULijp9K3Qf6nJHWPAmW 7UIku5A8Z0fbBcEM4gwmHOyMD2eJwUJ783nmDFwJplueaMPJ19qHzSz84wD+Pmtb0q7K OEf5fR+ld7tarZeXQJBMuyoI/zYI1fPGdtDe4GRFT6blHdUiuhEEOfUc+ErX4qmqC11Z xeZn4ru32WHHj/gemV6T5H3LGOpD63Wh1/kwix4SKryB55min9n6LkL0DUMv7GOk1t5U BA== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins , Jonathan Cameron Subject: [PATCH v6 07/10] i386/pc: handle unitialized mr in pc_get_cxl_range_end() Date: Fri, 1 Jul 2022 17:10:11 +0100 Message-Id: <20220701161014.3850-8-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220701161014.3850-1-joao.m.martins@oracle.com> References: <20220701161014.3850-1-joao.m.martins@oracle.com> X-Proofpoint-ORIG-GUID: 0VsQps7W65mOJs6avNlHINTotK0dSlQ6 X-Proofpoint-GUID: 0VsQps7W65mOJs6avNlHINTotK0dSlQ6 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=joao.m.martins@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1656693023000100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This in preparation to allow pc_pci_hole64_start() to be called early in pc_memory_init(), handle CXL memory region end when its underlying memory region isn't yet initialized. Cc: Jonathan Cameron Signed-off-by: Joao Martins --- hw/i386/pc.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 8655cc3b8894..d6dff71012ab 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -857,6 +857,19 @@ static uint64_t pc_get_cxl_range_end(PCMachineState *p= cms) start =3D fw->mr.addr + memory_region_size(&fw->mr); } } + } else { + hwaddr cxl_size =3D MiB; + + start =3D pc_get_cxl_range_start(pcms); + if (pcms->cxl_devices_state.fixed_windows) { + GList *it; + + start =3D ROUND_UP(start + cxl_size, 256 * MiB); + for (it =3D pcms->cxl_devices_state.fixed_windows; it; it =3D = it->next) { + CXLFixedWindow *fw =3D it->data; + start +=3D fw->size; + } + } } =20 return start; --=20 2.17.2 From nobody Mon Feb 9 14:37:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1656692670; cv=none; d=zohomail.com; s=zohoarc; b=egyyZ+h4Ke+YhwBfbs/RAr/4kl74kdXtZ7Uclax5hoyotO6MgIEgrCZJavsLhMEjp99ljh4kdJtfViq3F/AnY44IstjG+EAVEZAAJmmET4mRQ7CC68YjlMAckUzL16NwV9jc+f7yNvPy40dYD++KDwFWpH5Wl3FnF3tszB0i1ro= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1656692670; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=Kw2G9dR6MvexJfZ1dxN18sQdQ7xLSnJUnZkiTP0mJLA=; b=aib146O6TnT3TcdZhu8xs1lN8O2nvoJ7ZwK2CkFoFfaXemW6zrZNZN/ux2iAOMw9cFea8PUvA5vXidTST8FPjARzJhAuHwgDRUaS6MEI8dYGJtmhnYpLY2KNL6leTfArMvX/Gk385Yink/4nYp3yzAXgU3AdhijHb+fcjzYdviI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16566926702461016.6864190934143; Fri, 1 Jul 2022 09:24:30 -0700 (PDT) Received: from localhost ([::1]:43942 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o7JRV-0005hT-0P for importer@patchew.org; Fri, 01 Jul 2022 12:24:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47046) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o7JEr-0000rL-W7 for qemu-devel@nongnu.org; Fri, 01 Jul 2022 12:11:26 -0400 Received: from mx0b-00069f02.pphosted.com ([205.220.177.32]:13070) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o7JEq-0002qT-1V for qemu-devel@nongnu.org; Fri, 01 Jul 2022 12:11:25 -0400 Received: from pps.filterd (m0246630.ppops.net [127.0.0.1]) by mx0b-00069f02.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 261G2upv002374; Fri, 1 Jul 2022 16:11:14 GMT Received: from phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta03.appoci.oracle.com [138.1.37.129]) by mx0b-00069f02.pphosted.com (PPS) with ESMTPS id 3gwrscq9hp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 01 Jul 2022 16:11:14 +0000 Received: from pps.filterd (phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (8.16.1.2/8.16.1.2) with SMTP id 261G5jU3016287; Fri, 1 Jul 2022 16:11:13 GMT Received: from pps.reinject (localhost [127.0.0.1]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com with ESMTP id 3gwrt4swa2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 01 Jul 2022 16:11:13 +0000 Received: from phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 261GAftS029065; Fri, 1 Jul 2022 16:11:13 GMT Received: from paddy.uk.oracle.com (dhcp-10-175-184-247.vpn.oracle.com [10.175.184.247]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com with ESMTP id 3gwrt4svtm-9; Fri, 01 Jul 2022 16:11:13 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2021-07-09; bh=Kw2G9dR6MvexJfZ1dxN18sQdQ7xLSnJUnZkiTP0mJLA=; b=rommBto96/W2A2qDPR/RwI/ZOG2yABMC0tYhoLir/WjOVMLIgGa/VYHDHi7rMkEeVZrZ MERAeOQm+795mWo0L0eUqhSGnVhdGt4fpGpQAuznuhLwb2UCezgF0K9yfb5Oa5fBbV9Z t3aGGKO+DT50tBXiISe0IRfpYdBjG/iAwaA6aLyUankflyYIlaP7s90u0HbX01lHif7E nBka8CmOnCMp7D4KaumN7sPlI9u/otL0/i7XmPjB5BMm4xXhMQqTJxvJKNZ7hYGjSGlB HNoIcz7PoDrEiLhnIpXPCmhr2HJEyjE205uMhpJrTL7rnA8Eo9qj9swfx1+s4TZPWCa2 WA== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins , Jonathan Cameron Subject: [PATCH v6 08/10] i386/pc: factor out device_memory base/size to helper Date: Fri, 1 Jul 2022 17:10:12 +0100 Message-Id: <20220701161014.3850-9-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220701161014.3850-1-joao.m.martins@oracle.com> References: <20220701161014.3850-1-joao.m.martins@oracle.com> X-Proofpoint-ORIG-GUID: YrdSaC9PFo6ygvktI0jrY7XT4p78QqkU X-Proofpoint-GUID: YrdSaC9PFo6ygvktI0jrY7XT4p78QqkU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=joao.m.martins@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1656692671088100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move obtaining hole64_start from device_memory MR base/size into an helper alongside correspondent getters in pc_memory_init() when the hotplug range is unitialized. This is the final step that allows pc_pci_hole64_start() to be callable at the beginning of pc_memory_init() before any MRs are initialized. Cc: Jonathan Cameron Signed-off-by: Joao Martins --- hw/i386/pc.c | 55 +++++++++++++++++++++++++++++++++++++++------------- 1 file changed, 41 insertions(+), 14 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index d6dff71012ab..a79fa1b6beeb 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -825,16 +825,48 @@ static hwaddr pc_above_4g_end(PCMachineState *pcms) return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; } =20 +static void pc_get_device_memory_range(PCMachineState *pcms, + hwaddr *base, + ram_addr_t *device_mem_size) +{ + PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); + MachineState *machine =3D MACHINE(pcms); + ram_addr_t size; + hwaddr addr; + + if (pcmc->has_reserved_memory && + machine->device_memory && machine->device_memory->base) { + *base =3D machine->device_memory->base; + *device_mem_size =3D memory_region_size(&machine->device_memory->m= r); + return; + } + + /* handles uninitialized @device_memory MR */ + size =3D machine->maxram_size - machine->ram_size; + addr =3D ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); + + if (pcmc->enforce_aligned_dimm) { + /* size device region assuming 1G page max alignment per slot */ + size +=3D (1 * GiB) * machine->ram_slots; + } + + *base =3D addr; + *device_mem_size =3D size; +} + + static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) { PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); MachineState *machine =3D MACHINE(pcms); hwaddr cxl_base; + ram_addr_t size; =20 - if (pcmc->has_reserved_memory && machine->device_memory->base) { - cxl_base =3D machine->device_memory->base; + if (pcmc->has_reserved_memory && + machine->device_memory && machine->device_memory->base) { + pc_get_device_memory_range(pcms, &cxl_base, &size); if (!pcmc->broken_reserved_end) { - cxl_base +=3D memory_region_size(&machine->device_memory->mr); + cxl_base +=3D size; } } else { cxl_base =3D pc_above_4g_end(pcms); @@ -937,7 +969,7 @@ void pc_memory_init(PCMachineState *pcms, /* initialize device memory address space */ if (pcmc->has_reserved_memory && (machine->ram_size < machine->maxram_size)) { - ram_addr_t device_mem_size =3D machine->maxram_size - machine->ram= _size; + ram_addr_t device_mem_size; =20 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { error_report("unsupported amount of memory slots: %"PRIu64, @@ -952,13 +984,7 @@ void pc_memory_init(PCMachineState *pcms, exit(EXIT_FAILURE); } =20 - machine->device_memory->base =3D - ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); - - if (pcmc->enforce_aligned_dimm) { - /* size device region assuming 1G page max alignment per slot = */ - device_mem_size +=3D (1 * GiB) * machine->ram_slots; - } + pc_get_device_memory_range(pcms, &machine->device_memory->base, &d= evice_mem_size); =20 if ((machine->device_memory->base + device_mem_size) < device_mem_size) { @@ -1063,13 +1089,14 @@ uint64_t pc_pci_hole64_start(void) PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); MachineState *ms =3D MACHINE(pcms); uint64_t hole64_start =3D 0; + ram_addr_t size =3D 0; =20 if (pcms->cxl_devices_state.is_enabled) { hole64_start =3D pc_get_cxl_range_end(pcms); - } else if (pcmc->has_reserved_memory && ms->device_memory->base) { - hole64_start =3D ms->device_memory->base; + } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_siz= e)) { + pc_get_device_memory_range(pcms, &hole64_start, &size); if (!pcmc->broken_reserved_end) { - hole64_start +=3D memory_region_size(&ms->device_memory->mr); + hole64_start +=3D size; } } else { hole64_start =3D pc_above_4g_end(pcms); --=20 2.17.2 From nobody Mon Feb 9 14:37:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1656692603; cv=none; d=zohomail.com; s=zohoarc; b=SHubH8gYtfUlBipiXKHNGjpMdRI5FoMpfDy0AYnZUeuvqvSyZltp56y1jpSJQrYcDsyTiFnklYaJp8pkis9MMztW1mbEbkjInrJtVlnXzKYBhS7dXjjrYPtkQoeqczQkCHv+EvkBE73Sneu4be3MhKmamLGDxn/gTGx+s/jNJjQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1656692603; 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Fri, 01 Jul 2022 16:11:17 +0000 Received: from phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 261GAftU029065; Fri, 1 Jul 2022 16:11:17 GMT Received: from paddy.uk.oracle.com (dhcp-10-175-184-247.vpn.oracle.com [10.175.184.247]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com with ESMTP id 3gwrt4svtm-10; Fri, 01 Jul 2022 16:11:17 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2021-07-09; bh=1tZZSQLrz9hbXFSEbGz0upDFbZ/ZpsB4PA8XKw+kgRg=; b=r9gf40tak9rG5d7BwDfMar1ojRAZ3TxAEtpbZ22+593zTSgOLumiFRC2P8AvflUyCyJ1 Ezv51JVWZ0KBWzD7YbNlHDqiQ8AyLUTcsJ/gg7AZ7k5L7h7RaM3cZLP+LFC087fmazbs p8+AC7iD0cdIJtsaZVE5Ukw28q4oI35hiHr+szmtw+WaI7LmxHT1JaP+RvOahOYsiD9o /5PgE2fDg8FG0Ml0O148A9qUqQ8w0KOHyCdiDzJvqsxi8nxiZC+Per94E0xIKw1Vumw2 qaNapPf7Z4UDmOuxRevwjuMZ7ZbWuWNsAiJm+w8g20fA1M7UkXTuuedvrRd2wSiwDgvm KQ== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins Subject: [PATCH v6 09/10] i386/pc: relocate 4g start to 1T where applicable Date: Fri, 1 Jul 2022 17:10:13 +0100 Message-Id: <20220701161014.3850-10-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220701161014.3850-1-joao.m.martins@oracle.com> References: <20220701161014.3850-1-joao.m.martins@oracle.com> X-Proofpoint-ORIG-GUID: nPc82lI1rNhF5Uo-31W96mh0ukzXrZN0 X-Proofpoint-GUID: nPc82lI1rNhF5Uo-31W96mh0ukzXrZN0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.177.32; envelope-from=joao.m.martins@oracle.com; helo=mx0b-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1656692604622100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" It is assumed that the whole GPA space is available to be DMA addressable, within a given address space limit, except for a tiny region before the 4G. Since Linux v5.4, VFIO validates whether the selected GPA is indeed valid i.e. not reserved by IOMMU on behalf of some specific devices or platform-defined restrictions, and thus failing the ioctl(VFIO_DMA_MAP) with -EINVAL. AMD systems with an IOMMU are examples of such platforms and particularly may only have these ranges as allowed: 0000000000000000 - 00000000fedfffff (0 .. 3.982G) 00000000fef00000 - 000000fcffffffff (3.983G .. 1011.9G) 0000010000000000 - ffffffffffffffff (1Tb .. 16Pb[*]) We already account for the 4G hole, albeit if the guest is big enough we will fail to allocate a guest with >1010G due to the ~12G hole at the 1Tb boundary, reserved for HyperTransport (HT). [*] there is another reserved region unrelated to HT that exists in the 256T boundary in Fam 17h according to Errata #1286, documeted also in "Open-Source Register Reference for AMD Family 17h Processors (PUB)" When creating the region above 4G, take into account that on AMD platforms the HyperTransport range is reserved and hence it cannot be used either as GPAs. On those cases rather than establishing the start of ram-above-4g to be 4G, relocate instead to 1Tb. See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", for more information on the underlying restriction of IOVAs. After accounting for the 1Tb hole on AMD hosts, mtree should look like: 0000000000000000-000000007fffffff (prio 0, i/o): alias ram-below-4g @pc.ram 0000000000000000-000000007fffffff 0000010000000000-000001ff7fffffff (prio 0, i/o): alias ram-above-4g @pc.ram 0000000080000000-000000ffffffffff If the relocation is done or the address space covers it, we also add the the reserved HT e820 range as reserved. Default phys-bits on Qemu is TCG_PHYS_ADDR_BITS (40) which is enough to address 1Tb (0xff ffff ffff). On AMD platforms, if a ram-above-4g relocation may be desired and the CPU wasn't configured with a big enough phys-bits, print an error message to the user and do not make the relocation of the above-4g-region if phys-bits is too low. Suggested-by: Igor Mammedov Signed-off-by: Joao Martins --- hw/i386/pc.c | 101 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index a79fa1b6beeb..07025b510540 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -907,6 +907,87 @@ static uint64_t pc_get_cxl_range_end(PCMachineState *p= cms) return start; } =20 +static hwaddr pc_max_used_gpa(PCMachineState *pcms, + hwaddr above_4g_mem_start, + uint64_t pci_hole64_size) +{ + X86MachineState *x86ms =3D X86_MACHINE(pcms); + + if (!x86ms->above_4g_mem_size) { + /* + * 32-bit pci hole goes from + * end-of-low-ram (@below_4g_mem_size) to IOAPIC. + */ + return IO_APIC_DEFAULT_ADDRESS - 1; + } + + return pc_pci_hole64_start() + pci_hole64_size; +} + +/* + * AMD systems with an IOMMU have an additional hole close to the + * 1Tb, which are special GPAs that cannot be DMA mapped. Depending + * on kernel version, VFIO may or may not let you DMA map those ranges. + * Starting Linux v5.4 we validate it, and can't create guests on AMD mach= ines + * with certain memory sizes. It's also wrong to use those IOVA ranges + * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. + * The ranges reserved for Hyper-Transport are: + * + * FD_0000_0000h - FF_FFFF_FFFFh + * + * The ranges represent the following: + * + * Base Address Top Address Use + * + * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space + * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl + * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK + * FD_F910_0000h FD_F91F_FFFFh System Management + * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables + * FD_FB00_0000h FD_FBFF_FFFFh Address Translation + * FD_FC00_0000h FD_FDFF_FFFFh I/O Space + * FD_FE00_0000h FD_FFFF_FFFFh Configuration + * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages + * FE_2000_0000h FF_FFFF_FFFFh Reserved + * + * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", + * Table 3: Special Address Controls (GPA) for more information. + */ +#define AMD_HT_START 0xfd00000000UL +#define AMD_HT_END 0xffffffffffUL +#define AMD_ABOVE_1TB_START (AMD_HT_END + 1) +#define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) + +static void pc_set_amd_above_4g_mem_start(PCMachineState *pcms, + uint64_t pci_hole64_size) +{ + X86MachineState *x86ms =3D X86_MACHINE(pcms); + hwaddr start =3D x86ms->above_4g_mem_start; + hwaddr maxphysaddr, maxusedaddr; + + /* Bail out if max possible address does not cross HT range */ + if (pc_max_used_gpa(pcms, start, pci_hole64_size) < AMD_HT_START) { + return; + } + + /* + * Relocating ram-above-4G requires more than TCG_PHYS_ADDR_BITS (40). + * So make sure phys-bits is required to be appropriately sized in ord= er + * to proceed with the above-4g-region relocation and thus boot. + */ + start =3D AMD_ABOVE_1TB_START; + maxphysaddr =3D ((hwaddr)1 << X86_CPU(first_cpu)->phys_bits) - 1; + maxusedaddr =3D pc_max_used_gpa(pcms, start, pci_hole64_size); + if (maxphysaddr < maxusedaddr) { + error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 + " phys-bits too low (%u) cannot avoid AMD HT range", + maxphysaddr, maxusedaddr, X86_CPU(first_cpu)->phys_bi= ts); + exit(EXIT_FAILURE); + } + + x86ms->above_4g_mem_start =3D start; +} + void pc_memory_init(PCMachineState *pcms, MemoryRegion *system_memory, MemoryRegion *rom_memory, @@ -922,12 +1003,31 @@ void pc_memory_init(PCMachineState *pcms, PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); X86MachineState *x86ms =3D X86_MACHINE(pcms); hwaddr cxl_base, cxl_resv_end =3D 0; + X86CPU *cpu =3D X86_CPU(first_cpu); =20 assert(machine->ram_size =3D=3D x86ms->below_4g_mem_size + x86ms->above_4g_mem_size); =20 linux_boot =3D (machine->kernel_filename !=3D NULL); =20 + /* + * The HyperTransport range close to the 1T boundary is unique to AMD + * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation + * to above 1T to AMD vCPUs only. + */ + if (IS_AMD_CPU(&cpu->env)) { + pc_set_amd_above_4g_mem_start(pcms, pci_hole64_size); + + /* + * Advertise the HT region if address space covers the reserved + * region or if we relocate. + */ + if (x86ms->above_4g_mem_start =3D=3D AMD_ABOVE_1TB_START || + cpu->phys_bits >=3D 40) { + e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); + } + } + /* * Split single memory region and use aliases to address portions of i= t, * done for backwards compatibility with older qemus. @@ -938,6 +1038,7 @@ void pc_memory_init(PCMachineState *pcms, 0, x86ms->below_4g_mem_size); memory_region_add_subregion(system_memory, 0, ram_below_4g); e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); + if (x86ms->above_4g_mem_size > 0) { ram_above_4g =3D g_malloc(sizeof(*ram_above_4g)); memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", --=20 2.17.2 From nobody Mon Feb 9 14:37:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 01 Jul 2022 16:11:20 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=corp-2021-07-09; bh=JtTZj78qZfJWXFuI6YbnT1BrSL5MCgQvekdrVAfcxHY=; b=vGZf8B7sgEHNOxaQApPsWZNRA3LahxUFfodwSVGy3UmQcNENgK/hh+JxfauuCKfB+TEa VWUkgtglw315iXjP7fSGIOKISOO6t6nGZAx8RNojDRfhOkHFiPxXzi5POXcAeuiMZRsl U5/sOxGBzi21SbU9oyJMnzNhiLxHh2dnNUjj+wze4zl+5oX2fEppr5JqXrJNGx04QZqt tHNGfW2vFM3FmuJOSpkYekf6OdYfheEr1C7IERC2rK53XID8n+crq5HDFnFB3XIB390j gzj7M9BkGHvpOrmAbT1Up+hLcJKHNflWh8cThN1m8fR+mzo41r/fzG/dlZ/eIsLm6Hfv Ig== From: Joao Martins To: qemu-devel@nongnu.org Cc: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit , Joao Martins Subject: [PATCH v6 10/10] i386/pc: restrict AMD only enforcing of valid IOVAs to new machine type Date: Fri, 1 Jul 2022 17:10:14 +0100 Message-Id: <20220701161014.3850-11-joao.m.martins@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220701161014.3850-1-joao.m.martins@oracle.com> References: <20220701161014.3850-1-joao.m.martins@oracle.com> X-Proofpoint-ORIG-GUID: slaVK0ojxF6EsPcISsSsp62a88znC-Gb X-Proofpoint-GUID: slaVK0ojxF6EsPcISsSsp62a88znC-Gb Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.165.32; envelope-from=joao.m.martins@oracle.com; helo=mx0a-00069f02.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @oracle.com) X-ZM-MESSAGEID: 1656693164565100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The added enforcing is only relevant in the case of AMD where the range right before the 1TB is restricted and cannot be DMA mapped by the kernel consequently leading to IOMMU INVALID_DEVICE_REQUEST or possibly other kinds of IOMMU events in the AMD IOMMU. Although, there's a case where it may make sense to disable the IOVA relocation/validation when migrating from a non-valid-IOVA-aware qemu to one that supports it. Relocating RAM regions to after the 1Tb hole has consequences for guest ABI because we are changing the memory mapping, so make sure that only new machine enforce but not older ones. Signed-off-by: Joao Martins Acked-by: Dr. David Alan Gilbert Acked-by: Igor Mammedov --- hw/i386/pc.c | 6 ++++-- hw/i386/pc_piix.c | 2 ++ hw/i386/pc_q35.c | 2 ++ include/hw/i386/pc.h | 1 + 4 files changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 07025b510540..f99e16a5db4b 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1013,9 +1013,10 @@ void pc_memory_init(PCMachineState *pcms, /* * The HyperTransport range close to the 1T boundary is unique to AMD * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation - * to above 1T to AMD vCPUs only. + * to above 1T to AMD vCPUs only. @enforce_valid_iova is only false in + * older machine types (<=3D 7.0) for compatibility purposes. */ - if (IS_AMD_CPU(&cpu->env)) { + if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_valid_iova) { pc_set_amd_above_4g_mem_start(pcms, pci_hole64_size); =20 /* @@ -1950,6 +1951,7 @@ static void pc_machine_class_init(ObjectClass *oc, vo= id *data) pcmc->has_reserved_memory =3D true; pcmc->kvmclock_enabled =3D true; pcmc->enforce_aligned_dimm =3D true; + pcmc->enforce_valid_iova =3D true; /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K rep= orted * to be used at the moment, 32K should be enough for a while. */ pcmc->acpi_data_size =3D 0x20000 + 0x8000; diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index f3c726e42400..504ddd0deece 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -444,9 +444,11 @@ DEFINE_I440FX_MACHINE(v7_1, "pc-i440fx-7.1", NULL, =20 static void pc_i440fx_7_0_machine_options(MachineClass *m) { + PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); pc_i440fx_7_1_machine_options(m); m->alias =3D NULL; m->is_default =3D false; + pcmc->enforce_valid_iova =3D false; compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len); compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len); } diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 5a4a737fe203..4b747c59c19a 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -381,8 +381,10 @@ DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL, =20 static void pc_q35_7_0_machine_options(MachineClass *m) { + PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); pc_q35_7_1_machine_options(m); m->alias =3D NULL; + pcmc->enforce_valid_iova =3D false; compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len); compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len); } diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 568c226d3034..3a873ff69499 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -118,6 +118,7 @@ struct PCMachineClass { bool has_reserved_memory; bool enforce_aligned_dimm; bool broken_reserved_end; + bool enforce_valid_iova; =20 /* generate legacy CPU hotplug AML */ bool legacy_cpu_hotplug; --=20 2.17.2