From nobody Mon Feb 9 20:13:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1656618380; cv=none; d=zohomail.com; s=zohoarc; b=VsPZgCp4gr7dBDj0XMz/s8u7bZu2cCjpLV7qRsTDG6KkX6Ri5CzxyagBYPQGdNRQa4FOilzsVBSXOLkn5+lh5OQlPnZYQwxNO4b8QQNYYFCktoiaONl1OQpJV7ukioukmCvsoNdA+uy4EXRAGJ06SEEjiZ7Gg4vIPd75cMo06a4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1656618380; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VgPb1Tkc0n0TFxZ2n6JlaR4U9pn5OgDJfIFcTGqpVVU=; b=hIkqbPHucr4QgELcLupPl6j44a4AMZziXv3bXQx/kbNyVInkOb3I2mYzSD0fKfDVt23IwjTTL/ezU61NYesYIW2rd+DvCeMkNKX4KIGjOez1telVK0heTXurhR1m8oHuVrQQHDGX1A+rGqWytZTZe3fHxxFuAE2Ai9N9+VCvy1A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165661838058287.34943858958195; Thu, 30 Jun 2022 12:46:20 -0700 (PDT) Received: from localhost ([::1]:47098 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o707H-0005zB-BA for importer@patchew.org; Thu, 30 Jun 2022 15:46:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55154) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o702f-00031r-63 for qemu-devel@nongnu.org; Thu, 30 Jun 2022 15:41:33 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:40507) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o702W-0005ao-Fw for qemu-devel@nongnu.org; Thu, 30 Jun 2022 15:41:30 -0400 Received: by mail-wr1-x432.google.com with SMTP id v9so61571wrp.7 for ; Thu, 30 Jun 2022 12:41:22 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m2-20020adffa02000000b0021d163daeb0sm13200228wrr.108.2022.06.30.12.41.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jun 2022 12:41:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=VgPb1Tkc0n0TFxZ2n6JlaR4U9pn5OgDJfIFcTGqpVVU=; b=iiZPMUCfuULaPfn5Gj0GdlAZd76N2XAtBuqBflMrIHyY9ljoJsNEVJw3MQtiyBFjdv 7tvQ5yXgx1vjvjRSm38tGu4CgRjZVx0gld7zdV1sL7P0+MRrFI0MYrU2cAv8bi86mBdk uyMaoovd5z7yzwIgWIlTypUyhbH5HxObngAJc7fiMn6pD4EslCrjHoWWUnQzZIucSKTg HQtz+7vzIjXx/x/FwJVTGRyTLO8fkKZbjjO1dmGXPD+GcXomJTmNS4X84giH8MUWJ0Bj xq0CRb2jPNk5cdGvommC/xqg2ADMjHVEmYcPXddmZgfvUp48NaalugDwXBCPPlshDRSf nuzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VgPb1Tkc0n0TFxZ2n6JlaR4U9pn5OgDJfIFcTGqpVVU=; b=1C5fOp+WzEvpFVSGcWlbC1kDHvK81Dm4kCsEdSNctQoiN+34Ia6cQ9wXuKaNYiR/0z lvRSC1m6aodbXYs0qAyodpmYd6zCeZUsiN/6tP1duF3cq3Q+gQ2nyAVxjwDl4Ld7dH0H L+D9xqE02ZTDWYL7hewRN23igEIlFlfgQ8K02Pr46K4mkyTLC0uE5ljys6PBnyOBvAnJ 4J0emCMOyVJezpogQNM/3z8qrpQWPP4ML0KdWw5ZHJUuZZV+z+VepYJFKCMd1pXJ/yRN eW4j4YztmYNVUHeNijACRllnu/aMiXZALZEAIERbTi16s8nWq43rzubT3fjcbCZiUkhg bg3g== X-Gm-Message-State: AJIora9A3p7F/9Grvwibu2flKWKxMD6qTt4WsOeg9Etp1vVfS6v+BM4L JyQrjubN7Mrpv6UCxCaaxE4K8w== X-Google-Smtp-Source: AGRyM1uNxeiiPEz+zJaBfmdGKqppBhPKNSn27+3aLmREwjsVXQexkduLcEO0ZRMkuPbosNEpVyMhZg== X-Received: by 2002:a05:6000:1705:b0:21b:bcff:39d3 with SMTP id n5-20020a056000170500b0021bbcff39d3mr10032630wrc.502.1656618081340; Thu, 30 Jun 2022 12:41:21 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/5] target/arm: Fix code style issues in debug helper functions Date: Thu, 30 Jun 2022 20:41:12 +0100 Message-Id: <20220630194116.3438513-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220630194116.3438513-1-peter.maydell@linaro.org> References: <20220630194116.3438513-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656618382088100003 Content-Type: text/plain; charset="utf-8" Before moving debug system register helper functions to a different file, fix the code style issues (mostly block comment syntax) so checkpatch doesn't complain about the code-motion patch. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 58 +++++++++++++++++++++++++++++---------------- 1 file changed, 38 insertions(+), 20 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f6dcb1a1152..1c7ec2f8678 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -307,7 +307,8 @@ static uint64_t arm_mdcr_el2_eff(CPUARMState *env) return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0; } =20 -/* Check for traps to "powerdown debug" registers, which are controlled +/* + * Check for traps to "powerdown debug" registers, which are controlled * by MDCR.TDOSA */ static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -327,7 +328,8 @@ static CPAccessResult access_tdosa(CPUARMState *env, co= nst ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 -/* Check for traps to "debug ROM" registers, which are controlled +/* + * Check for traps to "debug ROM" registers, which are controlled * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. */ static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, @@ -347,7 +349,8 @@ static CPAccessResult access_tdra(CPUARMState *env, con= st ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 -/* Check for traps to general debug registers, which are controlled +/* + * Check for traps to general debug registers, which are controlled * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. */ static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, @@ -5982,7 +5985,8 @@ static CPAccessResult ctr_el0_access(CPUARMState *env= , const ARMCPRegInfo *ri, static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Writes to OSLAR_EL1 may update the OS lock status, which can be + /* + * Writes to OSLAR_EL1 may update the OS lock status, which can be * read via a bit in OSLSR_EL1. */ int oslock; @@ -5997,7 +6001,8 @@ static void oslar_write(CPUARMState *env, const ARMCP= RegInfo *ri, } =20 static const ARMCPRegInfo debug_cp_reginfo[] =3D { - /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped + /* + * DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; * unlike DBGDRAR it is never accessible from EL0. * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AAr= ch64 @@ -6052,21 +6057,24 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 = =3D 4, .access =3D PL1_RW, .accessfn =3D access_tdosa, .type =3D ARM_CP_NOP }, - /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't + /* + * Dummy DBGVCR: Linux wants to clear this on startup, but we don't * implement vector catch debug events yet. */ { .name =3D "DBGVCR", .cp =3D 14, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tda, .type =3D ARM_CP_NOP }, - /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor + /* + * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor * to save and restore a 32-bit guest's DBGVCR) */ { .name =3D "DBGVCR32_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 2, .opc1 =3D 4, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, .access =3D PL2_RW, .accessfn =3D access_tda, .type =3D ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, - /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications + /* + * Dummy MDCCINT_EL1, since we don't implement the Debug Communications * Channel but Linux may try to access this register. The 32-bit * alias is DBGDCCINT. */ @@ -6079,9 +6087,9 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D { /* 64 bit access versions of the (dummy) debug registers */ { .name =3D "DBGDRAR", .cp =3D 14, .crm =3D 1, .opc1 =3D 0, - .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, + .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalu= e =3D 0 }, { .name =3D "DBGDSAR", .cp =3D 14, .crm =3D 2, .opc1 =3D 0, - .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, + .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalu= e =3D 0 }, }; =20 /* @@ -6496,13 +6504,15 @@ void hw_watchpoint_update(ARMCPU *cpu, int n) break; } =20 - /* Attempts to use both MASK and BAS fields simultaneously are + /* + * Attempts to use both MASK and BAS fields simultaneously are * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, * thus generating a watchpoint for every byte in the masked region. */ mask =3D FIELD_EX64(wcr, DBGWCR, MASK); if (mask =3D=3D 1 || mask =3D=3D 2) { - /* Reserved values of MASK; we must act as if the mask value was + /* + * Reserved values of MASK; we must act as if the mask value was * some non-reserved value, or as if the watchpoint were disabled. * We choose the latter. */ @@ -6510,7 +6520,8 @@ void hw_watchpoint_update(ARMCPU *cpu, int n) } else if (mask) { /* Watchpoint covers an aligned area up to 2GB in size */ len =3D 1ULL << mask; - /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTAB= LE + /* + * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTAB= LE * whether the watchpoint fires when the unmasked bits match; we o= pt * to generate the exceptions. */ @@ -6521,7 +6532,8 @@ void hw_watchpoint_update(ARMCPU *cpu, int n) int basstart; =20 if (extract64(wvr, 2, 1)) { - /* Deprecated case of an only 4-aligned address. BAS[7:4] are + /* + * Deprecated case of an only 4-aligned address. BAS[7:4] are * ignored, and BAS[3:0] define which bytes to watch. */ bas &=3D 0xf; @@ -6532,7 +6544,8 @@ void hw_watchpoint_update(ARMCPU *cpu, int n) return; } =20 - /* The BAS bits are supposed to be programmed to indicate a contig= uous + /* + * The BAS bits are supposed to be programmed to indicate a contig= uous * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE wheth= er * we fire for each byte in the word/doubleword addressed by the W= VR. * We choose to ignore any non-zero bits after the first range of = 1s. @@ -6551,7 +6564,8 @@ void hw_watchpoint_update_all(ARMCPU *cpu) int i; CPUARMState *env =3D &cpu->env; =20 - /* Completely clear out existing QEMU watchpoints and our array, to + /* + * Completely clear out existing QEMU watchpoints and our array, to * avoid possible stale entries following migration load. */ cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); @@ -6669,7 +6683,8 @@ void hw_breakpoint_update(ARMCPU *cpu, int n) case 11: /* linked context ID and VMID match (reserved if no EL2) */ case 3: /* linked context ID match */ default: - /* We must generate no events for Linked context matches (unless + /* + * We must generate no events for Linked context matches (unless * they are linked to by some other bp/wp, which is handled in * updates for the linking bp/wp). We choose to also generate no e= vents * for reserved values. @@ -6685,7 +6700,8 @@ void hw_breakpoint_update_all(ARMCPU *cpu) int i; CPUARMState *env =3D &cpu->env; =20 - /* Completely clear out existing QEMU breakpoints and our array, to + /* + * Completely clear out existing QEMU breakpoints and our array, to * avoid possible stale entries following migration load. */ cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); @@ -6712,7 +6728,8 @@ static void dbgbcr_write(CPUARMState *env, const ARMC= PRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); int i =3D ri->crm; =20 - /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only + /* + * BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only * copy of BAS[0]. */ value =3D deposit64(value, 6, 1, extract64(value, 5, 1)); @@ -6724,7 +6741,8 @@ static void dbgbcr_write(CPUARMState *env, const ARMC= PRegInfo *ri, =20 static void define_debug_regs(ARMCPU *cpu) { - /* Define v7 and v8 architectural debug registers. + /* + * Define v7 and v8 architectural debug registers. * These are just dummy implementations for now. */ int i; --=20 2.25.1