From nobody Tue Feb 10 02:54:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656589759914567.7370448763837; Thu, 30 Jun 2022 04:49:19 -0700 (PDT) Received: from localhost ([::1]:55480 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o6sfd-00041G-FU for importer@patchew.org; Thu, 30 Jun 2022 07:49:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34674) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o6sIh-0000xM-29; Thu, 30 Jun 2022 07:25:35 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:44713 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o6sIa-0002dg-Cm; Thu, 30 Jun 2022 07:25:33 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LYbbn3Snvz4xDB; Thu, 30 Jun 2022 21:25:25 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LYbbl38N3z4xD5; Thu, 30 Jun 2022 21:25:23 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Richard Henderson , Klaus Jensen , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 25/27] hw/i2c/aspeed: add slave device in old register mode Date: Thu, 30 Jun 2022 13:24:09 +0200 Message-Id: <20220630112411.1474431-26-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220630112411.1474431-1-clg@kaod.org> References: <20220630112411.1474431-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=N4Bw=XF=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1656589760254100001 From: Klaus Jensen Add slave mode functionality for the Aspeed I2C controller in old register mode. This is implemented by realizing an I2C slave device owned by the I2C controller and attached to its own bus. The I2C slave device only implements asynchronous sends on the bus, so slaves not supporting that will not be able to communicate with it. Signed-off-by: Klaus Jensen [ clg: checkpatch fixes ] Message-Id: <20220601210831.67259-6-its@irrelevant.dk> Signed-off-by: C=C3=A9dric Le Goater Message-Id: <20220630045133.32251-7-me@pjd.dev> Signed-off-by: C=C3=A9dric Le Goater --- include/hw/i2c/aspeed_i2c.h | 8 ++++ hw/i2c/aspeed_i2c.c | 89 +++++++++++++++++++++++++++++++++---- 2 files changed, 88 insertions(+), 9 deletions(-) diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index 1398befc104d..ba148b2f6d7e 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -223,6 +223,9 @@ struct AspeedI2CBus { =20 struct AspeedI2CState *controller; =20 + /* slave mode */ + I2CSlave *slave; + MemoryRegion mr; =20 I2CBus *bus; @@ -249,6 +252,11 @@ struct AspeedI2CState { AddressSpace dram_as; }; =20 +#define TYPE_ASPEED_I2C_BUS_SLAVE "aspeed.i2c.slave" +OBJECT_DECLARE_SIMPLE_TYPE(AspeedI2CBusSlave, ASPEED_I2C_BUS_SLAVE) +struct AspeedI2CBusSlave { + I2CSlave i2c; +}; =20 struct AspeedI2CClass { SysBusDeviceClass parent_class; diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 71e2ebc63c84..4d055806cdd1 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -696,9 +696,7 @@ static void aspeed_i2c_bus_old_write(AspeedI2CBus *bus,= hwaddr offset, switch (offset) { case A_I2CD_FUN_CTRL: if (SHARED_FIELD_EX32(value, SLAVE_EN)) { - qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", - __func__); - break; + i2c_slave_set_address(bus->slave, bus->regs[R_I2CD_DEV_ADDR]); } bus->regs[R_I2CD_FUN_CTRL] =3D value & 0x0071C3FF; break; @@ -719,12 +717,15 @@ static void aspeed_i2c_bus_old_write(AspeedI2CBus *bu= s, hwaddr offset, bus->controller->intr_status &=3D ~(1 << bus->id); qemu_irq_lower(aic->bus_get_irq(bus)); } - if (handle_rx && (SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, - M_RX_CMD) || - SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, - M_S_RX_CMD_LAST))) { - aspeed_i2c_handle_rx_cmd(bus); - aspeed_i2c_bus_raise_interrupt(bus); + if (handle_rx) { + if (SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, M_RX_CMD) || + SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CD_CMD, + M_S_RX_CMD_LAST)) { + aspeed_i2c_handle_rx_cmd(bus); + aspeed_i2c_bus_raise_interrupt(bus); + } else if (aspeed_i2c_get_state(bus) =3D=3D I2CD_STXD) { + i2c_ack(bus->bus); + } } break; case A_I2CD_DEV_ADDR: @@ -1036,6 +1037,73 @@ static const TypeInfo aspeed_i2c_info =3D { .abstract =3D true, }; =20 +static int aspeed_i2c_bus_slave_event(I2CSlave *slave, enum i2c_event even= t) +{ + BusState *qbus =3D qdev_get_parent_bus(DEVICE(slave)); + AspeedI2CBus *bus =3D ASPEED_I2C_BUS(qbus->parent); + uint32_t reg_intr_sts =3D aspeed_i2c_bus_intr_sts_offset(bus); + uint32_t reg_byte_buf =3D aspeed_i2c_bus_byte_buf_offset(bus); + uint32_t value; + + switch (event) { + case I2C_START_SEND_ASYNC: + value =3D SHARED_ARRAY_FIELD_EX32(bus->regs, reg_byte_buf, TX_BUF); + SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, value << = 1); + + ARRAY_FIELD_DP32(bus->regs, I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH, 1); + SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1); + + aspeed_i2c_set_state(bus, I2CD_STXD); + + break; + + case I2C_FINISH: + SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, NORMAL_STOP, 1); + + aspeed_i2c_set_state(bus, I2CD_IDLE); + + break; + + default: + return -1; + } + + aspeed_i2c_bus_raise_interrupt(bus); + + return 0; +} + +static void aspeed_i2c_bus_slave_send_async(I2CSlave *slave, uint8_t data) +{ + BusState *qbus =3D qdev_get_parent_bus(DEVICE(slave)); + AspeedI2CBus *bus =3D ASPEED_I2C_BUS(qbus->parent); + uint32_t reg_intr_sts =3D aspeed_i2c_bus_intr_sts_offset(bus); + uint32_t reg_byte_buf =3D aspeed_i2c_bus_byte_buf_offset(bus); + + SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, data); + SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1); + + aspeed_i2c_bus_raise_interrupt(bus); +} + +static void aspeed_i2c_bus_slave_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + I2CSlaveClass *sc =3D I2C_SLAVE_CLASS(klass); + + dc->desc =3D "Aspeed I2C Bus Slave"; + + sc->event =3D aspeed_i2c_bus_slave_event; + sc->send_async =3D aspeed_i2c_bus_slave_send_async; +} + +static const TypeInfo aspeed_i2c_bus_slave_info =3D { + .name =3D TYPE_ASPEED_I2C_BUS_SLAVE, + .parent =3D TYPE_I2C_SLAVE, + .instance_size =3D sizeof(AspeedI2CBusSlave), + .class_init =3D aspeed_i2c_bus_slave_class_init, +}; + static void aspeed_i2c_bus_reset(DeviceState *dev) { AspeedI2CBus *s =3D ASPEED_I2C_BUS(dev); @@ -1060,6 +1128,8 @@ static void aspeed_i2c_bus_realize(DeviceState *dev, = Error **errp) sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); =20 s->bus =3D i2c_init_bus(dev, name); + s->slave =3D i2c_slave_create_simple(s->bus, TYPE_ASPEED_I2C_BUS_SLAVE, + 0xff); =20 memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i2c_bus_ops, s, name, aic->reg_size); @@ -1219,6 +1289,7 @@ static const TypeInfo aspeed_1030_i2c_info =3D { static void aspeed_i2c_register_types(void) { type_register_static(&aspeed_i2c_bus_info); + type_register_static(&aspeed_i2c_bus_slave_info); type_register_static(&aspeed_i2c_info); type_register_static(&aspeed_2400_i2c_info); type_register_static(&aspeed_2500_i2c_info); --=20 2.35.3