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From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>
To: qemu-arm@nongnu.org,
qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Richard Henderson <richard.henderson@linaro.org>,
Jae Hyun Yoo <quic_jaehyoo@quicinc.com>,
=?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>
Subject: [PULL 19/27] hw/arm/aspeed: firework: add I2C MUXes for VR channels
Date: Thu, 30 Jun 2022 13:24:03 +0200
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X-ZM-MESSAGEID: 1656588918904100001
From: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Add 2-level cascaded I2C MUXes for SOC VR channels into the Firework
machine.
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Reviewed-by: C=C3=A9dric Le Goater <clg@kaod.org>
Message-Id: <20220627154703.148943-8-quic_jaehyoo@quicinc.com>
Signed-off-by: C=C3=A9dric Le Goater <clg@kaod.org>
---
hw/arm/aspeed.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index e8c565c9adf5..6fe9b1354804 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -965,13 +965,21 @@ static void qcom_dc_scm_bmc_i2c_init(AspeedMachineSta=
te *bmc)
static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
{
AspeedSoCState *soc =3D &bmc->soc;
- I2CSlave *therm_mux;
+ I2CSlave *therm_mux, *cpuvr_mux;
=20
/* Create the generic DC-SCM hardware */
qcom_dc_scm_bmc_i2c_init(bmc);
=20
/* Now create the Firework specific hardware */
=20
+ /* I2C7 CPUVR MUX */
+ cpuvr_mux =3D i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
+ "pca9546", 0x70);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", =
0x72);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", =
0x72);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", =
0x72);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", =
0x72);
+
/* I2C8 Thermal Diodes*/
therm_mux =3D i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
"pca9548", 0x70);
--=20
2.35.3