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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.22.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:22:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=asVIVIoowKUhkyzxDq1stWKniA6O4cXXCtHWZbtFt2Q=; b=Ao/eB+e5FFFqh27hPkQrx/LIlq2Ca6tVIwX7ae33mY84ib+/BsB1Xqe4wcLVr6DjE2 fSJwZBkjhjr29nzvBbhGKerDEOkRX8QO3QEOviE+kIsLn2X3pORH6L2COpe9PRn60KNf Ivqc1ZTSj9pGnpNNiqOHWckSddaKyvAVSI4lGxlRpY2Arg/I/AkEtOYFlYLWB7NxmUHZ frucMkKKqpHodFrQ9ePW57H3x8wGEOr8EGpbF7NSkNbvUtFLXL+JDBis4Zl3d5Mjgh0o puyeOFOTvqY7iq+5iMKe3PHMLXY6GxFPGtTNpP6ne1+U3eCzThTxvI1OaztodgumU0vM M9/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=asVIVIoowKUhkyzxDq1stWKniA6O4cXXCtHWZbtFt2Q=; b=NvWBdaUh3I0Lk2KIfbrsnVWspOtb6fMO6n6j9jrWo311Sa58Umiy099X+ulWu/6Nxl 8cLzaG61//g49VJx6oIC2cEFXasOowXwoe9O07RPeWmoFWgRKW23yBvi6A4iC1X4ZtbQ npJ4btcn47pNyds4KQx3ZRjIAcS20u3zXR+W8n6k2nxu1akpRql25dXpxgJdp5trhBS0 cdwBKXnB2XT6oWHK0UKltqAF7u/zRJjlGMLnKcsL4vl3hRVDnqCJh2/uEiXsyD70jH1e 4iFBb2q0IwggwiRU2MoeLOJVC3Ww04IPwWgM1hHoFGE5rK1FZpOA0HN6JRyGC0vAwRl8 Qlbw== X-Gm-Message-State: AJIora+YkJPWJTCzGhfrLDwctYhBpGY0Bf/HIqAM7u41KGB3u2VtSxpc vTI8iM1NnS2+YNxUavUPDytuLvJZFHpgEQ== X-Google-Smtp-Source: AGRyM1tafMU8PaLVUf8kM2QudlO1Y6YK9Ti+lQtut2tr9Khc2d1XFnKexofIvPp14bBMpHoR2f9Wlg== X-Received: by 2002:aa7:90c4:0:b0:521:2cd6:bd3e with SMTP id k4-20020aa790c4000000b005212cd6bd3emr2659317pfk.19.1656390159201; Mon, 27 Jun 2022 21:22:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v4 32/45] target/arm: Enable SME for -cpu max Date: Tue, 28 Jun 2022 09:51:04 +0530 Message-Id: <20220628042117.368549-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656393518762100001 Content-Type: text/plain; charset="utf-8" Note that SME remains effectively disabled for user-only, because we do not yet set CPACR_EL1.SMEN. This needs to wait until the kernel ABI is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 4 ++++ target/arm/cpu64.c | 11 +++++++++++ 2 files changed, 15 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 83b4410065..8e494c8bea 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -65,6 +65,10 @@ the following architecture extensions: - FEAT_SHA512 (Advanced SIMD SHA512 instructions) - FEAT_SM3 (Advanced SIMD SM3 instructions) - FEAT_SM4 (Advanced SIMD SM4 instructions) +- FEAT_SME (Scalable Matrix Extension) +- FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode) +- FEAT_SME_F64F64 (Double-precision floating-point outer product instructi= ons) +- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instruc= tions) - FEAT_SPECRES (Speculation restriction instructions) - FEAT_SSBS (Speculative Store Bypass Safe) - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 19188d6cc2..40a0f043d0 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1018,6 +1018,7 @@ static void aarch64_max_initfn(Object *obj) */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ t =3D FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT= _DoubleFault */ + t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr1 =3D t; =20 @@ -1068,6 +1069,16 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 + t =3D cpu->isar.id_aa64smfr0; + t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ + cpu->isar.id_aa64smfr0 =3D t; + /* Replicate the same data to the 32-bit id registers. */ aa32_max_features(cpu); =20 --=20 2.34.1