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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.21.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:21:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PGqw0sxa6NjptPHDaNA2dvYv/+Ms1B8A00v4y3WH0Pc=; b=YedXqtbOcueLJpv1nlhqQBHEoDo7moGeUJAAO9TBdRYClIowsNiM7cuRnhDk+ESOj0 DvFmTZpCwqbwW8IZ8z20tWNPZbku4Mh1oD3A7btb0MGeGEDZVm6MLY+uxYWwxnAoRDmD lCOzhplMMCZ5CBMDI2JNqW29+hzjsOZ5ubGV5oBclp5HhbRzfYKV4XpmI9/ZosG0V4j/ 9l+u2QKH80TU3pohhwY0VhXKWrP297zZYA06IIIbiwtfHy+6jIp1x6Uc9aQ3r4jqRyKX dnC6dZImPoH+jmBkdXN8V447zxjsLzC9pnQAw70htbLB4szUcIgrEugVSboH5CVy1s4m JDvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PGqw0sxa6NjptPHDaNA2dvYv/+Ms1B8A00v4y3WH0Pc=; b=UBtZlqSZxR1f42rvy2E5gf+f05WoI5MQ8CAqAhKPuwpsV0HgRQw6/FcnVfOnB6ur9u hc9STLuRy51daFZgTQiN+/O9YkRvXbvuue1Awb1wisot2lyauXgRvAnBu7a1glQTzO2/ sZiRTZUwa45sRqHauvObzSWDnWix1YiZbEVAiD/Qm8iBT7ybjhucElVCm8vIfIAy7XwA Sca6qSq4FfKTkc980LzYSW5Olv4RMVgC1vvwLVQvZToodxq1PRXM0rkhTKIecJhU/JhT 4QhpEzKbg+olafHsmmsGOs8Vz1HO/lrAkgbZY9ebQcbDqexPyFkhv9V57hzYAciME2bE 4UIg== X-Gm-Message-State: AJIora923ldC+L+zSxXvjBiu9u4q9OJl1f7flSIfo+wKMg3px6xOpb/G JpmrUTgFiJWUrpOY96HyYrjx8db5kdS77Q== X-Google-Smtp-Source: AGRyM1sGBUQx0Z68q+b6BHSDKZP3VFFL72R83cruMbzHedtUT/CcmdU4n+07Iw2JLEmSyvA97R/bBg== X-Received: by 2002:a65:604a:0:b0:3f9:f423:b474 with SMTP id a10-20020a65604a000000b003f9f423b474mr15397374pgp.527.1656390085093; Mon, 27 Jun 2022 21:21:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 01/45] target/arm: Handle SME in aarch64_cpu_dump_state Date: Tue, 28 Jun 2022 09:50:33 +0530 Message-Id: <20220628042117.368549-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656390326186100001 Content-Type: text/plain; charset="utf-8" Dump SVCR, plus use the correct access check for Streaming Mode. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index bb44ad45aa..4a35890853 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -885,6 +885,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *= f, int flags) int i; int el =3D arm_current_el(env); const char *ns_status; + bool sve; =20 qemu_fprintf(f, " PC=3D%016" PRIx64 " ", env->pc); for (i =3D 0; i < 32; i++) { @@ -911,6 +912,12 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE = *f, int flags) el, psr & PSTATE_SP ? 'h' : 't'); =20 + if (cpu_isar_feature(aa64_sme, cpu)) { + qemu_fprintf(f, " SVCR=3D%08" PRIx64 " %c%c", + env->svcr, + (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), + (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); + } if (cpu_isar_feature(aa64_bti, cpu)) { qemu_fprintf(f, " BTYPE=3D%d", (psr & PSTATE_BTYPE) >> 10); } @@ -925,7 +932,15 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE = *f, int flags) qemu_fprintf(f, " FPCR=3D%08x FPSR=3D%08x\n", vfp_get_fpcr(env), vfp_get_fpsr(env)); =20 - if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) =3D= =3D 0) { + if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)= ) { + sve =3D sme_exception_el(env, el) =3D=3D 0; + } else if (cpu_isar_feature(aa64_sve, cpu)) { + sve =3D sve_exception_el(env, el) =3D=3D 0; + } else { + sve =3D false; + } + + if (sve) { int j, zcr_len =3D sve_vqm1_for_el(env, el); =20 for (i =3D 0; i <=3D FFR_PRED_NUM; i++) { --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656390313154707.4323866583552; Mon, 27 Jun 2022 21:25:13 -0700 (PDT) Received: from localhost ([::1]:52446 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o62ml-0004dB-Jb for importer@patchew.org; Tue, 28 Jun 2022 00:25:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62jG-0001Hf-U8 for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:35 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:45914) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jD-0003de-2w for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:34 -0400 Received: by mail-pj1-x102c.google.com with SMTP id g20-20020a17090a579400b001ed52939d72so5960541pji.4 for ; Mon, 27 Jun 2022 21:21:28 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.21.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:21:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Zt0iFWR3qz21z3bSyJ1iuT1OyELXtc2hbyVwv56j1M4=; b=CxlH52+qXuplkB1/KC0KLwGqbORfNtZNuTrOSWH6SE//XbXV+jBuIN/Qx5bU47WVkY B6gCnJQuJyqOcB0OzNHzAERU9co25y38RjOuYL+Xx8G05DNXc7p0LMh1zcFpfRvic35q c9i4Um8CUTo+4ODBeWLSNlz6MjjNhch9Pc2wUizvzyyV+w+jXmbmJz4KEp6xMJU/IT5e 4WzdBClnzT2J9ANCujBIe4GZFQFw8HETk4ieQ6LzB7z25tD8Ued4EH+YF7S7wtWXuE3s WMujIseUG12vkYZsxy8FQN+Ef6H3F+zOEyCi5Ucl+lc2DNvdHyODCeNvavOASeQ2v6Bb QxIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Zt0iFWR3qz21z3bSyJ1iuT1OyELXtc2hbyVwv56j1M4=; b=guSkIc14vTGSIYaBsUAyjx+HOezyCH4ZoO+RVGDiLmuz7TJPu5fWMY64uwOIN2g811 WGBGjw9YbwN+NrAiVDVhweGDW9GpCI9fjLd+Iq9WmkysoosGF7oQ5yUT2LwpnhOs93cY 7JNuQ0IaD+FI7MdDSxfHDGYqREGRoZyvQZ+Z5wQOkDDX9YmDezeDtJkExLPKMfilQR8V epGPgY9lcoVj2MYT70QvSz/lnSfi+IGmMOXpaPIpoUjdZKcrbbddBnoU/TOZdaGZ7j2H 0zoTg8vT+0aw9MqGhOJSDgF8lt+KbZbKIdOHgvPwTb2O+Njy2efFnldVsXtKVXWxhLi5 +t1w== X-Gm-Message-State: AJIora8C2w94qg1HFs/2xBQarZhcchmGX8HG0Q/r+E7LgJPJubcyMLQr YAaF3mo5X3tWOpDM5VcDIbkgJWnkdY4dUw== X-Google-Smtp-Source: AGRyM1s5o43TBKpRB7m1CCs0zatfrUZ8APSJ6eC+3giaSYykzkYH3qmpFLHfMrOjyZAUgK/DmE5uWg== X-Received: by 2002:a17:903:2488:b0:163:b2c0:7efe with SMTP id p8-20020a170903248800b00163b2c07efemr3010957plw.164.1656390087559; Mon, 27 Jun 2022 21:21:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v4 02/45] target/arm: Add infrastructure for disas_sme Date: Tue, 28 Jun 2022 09:50:34 +0530 Message-Id: <20220628042117.368549-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656390314412100001 Content-Type: text/plain; charset="utf-8" This includes the build rules for the decoder, and the new file for translation, but excludes any instructions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 1 + target/arm/sme.decode | 20 ++++++++++++++++++++ target/arm/translate-a64.c | 7 ++++++- target/arm/translate-sme.c | 35 +++++++++++++++++++++++++++++++++++ target/arm/meson.build | 2 ++ 5 files changed, 64 insertions(+), 1 deletion(-) create mode 100644 target/arm/sme.decode create mode 100644 target/arm/translate-sme.c diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index f0970c6b8c..789b6e8e78 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -146,6 +146,7 @@ static inline int pred_gvec_reg_size(DisasContext *s) } =20 bool disas_sve(DisasContext *, uint32_t); +bool disas_sme(DisasContext *, uint32_t); =20 void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); diff --git a/target/arm/sme.decode b/target/arm/sme.decode new file mode 100644 index 0000000000..c25c031a71 --- /dev/null +++ b/target/arm/sme.decode @@ -0,0 +1,20 @@ +# AArch64 SME instruction descriptions +# +# Copyright (c) 2022 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c86b97b1d4..a5f8a6c771 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14806,7 +14806,12 @@ static void aarch64_tr_translate_insn(DisasContext= Base *dcbase, CPUState *cpu) } =20 switch (extract32(insn, 25, 4)) { - case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ + case 0x0: + if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) { + unallocated_encoding(s); + } + break; + case 0x1: case 0x3: /* UNALLOCATED */ unallocated_encoding(s); break; case 0x2: diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c new file mode 100644 index 0000000000..786c93fb2d --- /dev/null +++ b/target/arm/translate-sme.c @@ -0,0 +1,35 @@ +/* + * AArch64 SME translation + * + * Copyright (c) 2022 Linaro, Ltd + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" +#include "tcg/tcg-gvec-desc.h" +#include "translate.h" +#include "exec/helper-gen.h" +#include "translate-a64.h" +#include "fpu/softfloat.h" + + +/* + * Include the generated decoder. + */ + +#include "decode-sme.c.inc" diff --git a/target/arm/meson.build b/target/arm/meson.build index 43dc600547..6dd7e93643 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,5 +1,6 @@ gen =3D [ decodetree.process('sve.decode', extra_args: '--decode=3Ddisas_sve'), + decodetree.process('sme.decode', extra_args: '--decode=3Ddisas_sme'), decodetree.process('neon-shared.decode', extra_args: '--decode=3Ddisas_n= eon_shared'), decodetree.process('neon-dp.decode', extra_args: '--decode=3Ddisas_neon_= dp'), decodetree.process('neon-ls.decode', extra_args: '--decode=3Ddisas_neon_= ls'), @@ -50,6 +51,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'sme_helper.c', 'translate-a64.c', 'translate-sve.c', + 'translate-sme.c', )) =20 arm_softmmu_ss =3D ss.source_set() --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656390503984479.20899518336046; Mon, 27 Jun 2022 21:28:23 -0700 (PDT) Received: from localhost ([::1]:33838 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o62pq-0002mV-KZ for importer@patchew.org; Tue, 28 Jun 2022 00:28:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36826) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62jH-0001Ii-Lm for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:35 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:43654) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jE-0003e6-5o for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:35 -0400 Received: by mail-pf1-x436.google.com with SMTP id 136so5772169pfy.10 for ; Mon, 27 Jun 2022 21:21:31 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.21.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:21:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4MGzl5Bqm41V1vcrQyG0m+KeU8wwAt/tgTS4HQgJdyw=; b=leBbhMaQIwacFK6RyE8R7tWUMAhDKyQKIQCfoceL+33/diZC79Fa1osmUkAtFODxHY LuEdk8lhi+PPEOarPBDriVPbgndDiZg4ylo4G+chMKnOBqilb+VXcDVdHj0VP6JBxyYu 97bOWPcwsiHTAoeOXSiqpu3joXrIob4jShYMREJgeE23YRp51XLE4LT+Cm3sdt9ITLJy I28fY1njDTFlJiJ861mFMDTvDrg6WhMTSo0XHHO3ucQB8c2Hyy+cH/VrVY36UKhso1bo 0L3jrbNVNl4Dwh5e6spbJgBkUMWjxGVtMvxJIDtg8lBtE6yQo/P88w0CqgsvARDjkYre MaGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4MGzl5Bqm41V1vcrQyG0m+KeU8wwAt/tgTS4HQgJdyw=; b=Ae/BGPu0CSAwQx8VIHg6WpyuEtN1KYlURxBbuO3OxDLsD8t/0NfRCaMBaU+uSrva2e ViGmDER0v55il9QdBlTZb7EmEvqAeAWdhYIH63gwSdw7fBq8FGecuTQ428niQB+uFW6p TSr5bh8GZG2AT4vg6mOXD76d7ZWykl0xg7wia+WSt9FdW7RkYCQV+XDQcBh9fE3rS+7E w4EALJ7UD98Cn2PfioE6nOLVjt7Fw8S9/gZprJxBC9j9NVRyrzRa1xgcLskdjTdEQTHs GOIl4uXXIZ08CAs9GjKnsqCiwSdST25MeT8pLYkhslQBWpTM2GbISFykJ/TUvuA+4R8M 8EEQ== X-Gm-Message-State: AJIora8sfuKP5YlmilNt6G59PiPNmoS0lsrJ12vXa6rpHTx302AA9jkI 7CvcjFI9EMN4tn0MYh92n1P0j/VvYToULw== X-Google-Smtp-Source: AGRyM1vqAcjlB+81tjZpEYafpCiOemHlOACTI+Lcym6LCiqw/0QvkeodxqkAEON9yqj4Zt8r1inn3Q== X-Received: by 2002:a63:b34d:0:b0:40c:76b2:b725 with SMTP id x13-20020a63b34d000000b0040c76b2b725mr15756084pgt.440.1656390090103; Mon, 27 Jun 2022 21:21:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active Date: Tue, 28 Jun 2022 09:50:35 +0530 Message-Id: <20220628042117.368549-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656390505189100001 Content-Type: text/plain; charset="utf-8" This new behaviour is in the ARM pseudocode function AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32 via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which the trap would be delivered is in AArch64 mode. Given that ARMv9 drops support for AArch32 outside EL0, the trap EL detection ought to be trivially true, but the pseudocode still contains a number of conditions, and QEMU has not yet committed to dropping A32 support for EL[12] when v9 features are present. Since the computation of SME_TRAP_NONSTREAMING is necessarily different for the two modes, we might as well preserve bits within TBFLAG_ANY and allocate separate bits within TBFLAG_A32 and TBFLAG_A64 instead. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 7 +++ target/arm/translate.h | 4 ++ target/arm/sme-fa64.decode | 89 ++++++++++++++++++++++++++++++++++++++ target/arm/helper.c | 42 ++++++++++++++++++ target/arm/translate-a64.c | 40 ++++++++++++++++- target/arm/translate-vfp.c | 12 +++++ target/arm/translate.c | 2 + target/arm/meson.build | 1 + 8 files changed, 195 insertions(+), 2 deletions(-) create mode 100644 target/arm/sme-fa64.decode diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4a4342f262..9e12669c12 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3146,6 +3146,11 @@ FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) * the same thing as the current security state of the processor! */ FIELD(TBFLAG_A32, NS, 10, 1) +/* + * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. + * This requires an SME trap from AArch32 mode when using NEON. + */ +FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) =20 /* * Bit usage when in AArch32 state, for M-profile only. @@ -3183,6 +3188,8 @@ FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) FIELD(TBFLAG_A64, SVL, 24, 4) +/* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. = */ +FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) =20 /* * Helpers for using the above. diff --git a/target/arm/translate.h b/target/arm/translate.h index 22fd882368..cbc907c751 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -102,6 +102,10 @@ typedef struct DisasContext { bool pstate_sm; /* True if PSTATE.ZA is set. */ bool pstate_za; + /* True if non-streaming insns should raise an SME Streaming exception= . */ + bool sme_trap_nonstreaming; + /* True if the current instruction is non-streaming. */ + bool is_nonstreaming; /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ bool mve_no_pred; /* diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode new file mode 100644 index 0000000000..4c2569477d --- /dev/null +++ b/target/arm/sme-fa64.decode @@ -0,0 +1,89 @@ +# AArch64 SME allowed instruction decoding +# +# Copyright (c) 2022 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# + +# These patterns are taken from Appendix E1.1 of DDI0616 A.a, +# Arm Architecture Reference Manual Supplement, +# The Scalable Matrix Extension (SME), for Armv9-A + +{ + [ + OK 0-00 1110 0000 0001 0010 11-- ---- ---- # SMOV W|Xd,Vn.B[0] + OK 0-00 1110 0000 0010 0010 11-- ---- ---- # SMOV W|Xd,Vn.H[0] + OK 0100 1110 0000 0100 0010 11-- ---- ---- # SMOV Xd,Vn.S[0] + OK 0000 1110 0000 0001 0011 11-- ---- ---- # UMOV Wd,Vn.B[0] + OK 0000 1110 0000 0010 0011 11-- ---- ---- # UMOV Wd,Vn.H[0] + OK 0000 1110 0000 0100 0011 11-- ---- ---- # UMOV Wd,Vn.S[0] + OK 0100 1110 0000 1000 0011 11-- ---- ---- # UMOV Xd,Vn.D[0] + ] + FAIL 0--0 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD vector o= perations +} + +{ + [ + OK 0101 1110 --1- ---- 11-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (= scalar) + OK 0101 1110 -10- ---- 00-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (= scalar, FP16) + OK 01-1 1110 1-10 0001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX = (scalar) + OK 01-1 1110 1111 1001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX = (scalar, FP16) + ] + FAIL 01-1 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD single-e= lement operations +} + +FAIL 0-00 110- ---- ---- ---- ---- ---- ---- # Advanced SIMD structur= e load/store +FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptogr= aphy extensions + +# These are the "avoidance of doubt" final table of Illegal Advanced SIMD = instructions +# We don't actually need to include these, as the default is OK. +# -001 111- ---- ---- ---- ---- ---- ---- # Scalar floating-point = operations +# --10 110- ---- ---- ---- ---- ---- ---- # Load/store pair of FP = registers +# --01 1100 ---- ---- ---- ---- ---- ---- # Load FP register (PC-r= elative literal) +# --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register= (unscaled imm) +# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) +# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) + +FAIL 0000 0100 --1- ---- 1010 ---- ---- ---- # ADR +FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA +FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT +FAIL 0010 0101 --01 100- 1111 000- ---0 ---- # RDFFR, RDFFRS +FAIL 0010 0101 --10 1--- 1001 ---- ---- ---- # WRFFR, SETFFR +FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP +FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b r= esult) +FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA +FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL +FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD +FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA +FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA +FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/cryp= to instructions +FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT = load (vector+scalar) +FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather pref= etch (vector+imm) +FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather pref= etch (scalar+vector) +FAIL 1000 010- -01- ---- 1--- ---- ---- ---- # SVE 32-bit gather load= (vector+imm) +FAIL 1000 0100 0-0- ---- 0--- ---- ---- ---- # SVE 32-bit gather load= byte (scalar+vector) +FAIL 1000 0100 1--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load= half (scalar+vector) +FAIL 1000 0101 0--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load= word (scalar+vector) +FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load= (scalar+scalar) +FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load= (scalar+imm) +FAIL 1010 010- -10- ---- 000- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+scalar) +FAIL 1010 010- -100 ---- 001- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+imm) +FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load= /prefetch +FAIL 1110 010- -00- ---- 001- ---- ---- ---- # SVE2 64-bit scatter NT= store (vector+scalar) +FAIL 1110 010- -10- ---- 001- ---- ---- ---- # SVE2 32-bit scatter NT= store (vector+scalar) +FAIL 1110 010- ---- ---- 1-0- ---- ---- ---- # SVE scatter store (sca= lar+32-bit vector) +FAIL 1110 010- ---- ---- 101- ---- ---- ---- # SVE scatter store (mis= c) diff --git a/target/arm/helper.c b/target/arm/helper.c index d2886a123a..976e414eda 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6269,6 +6269,32 @@ int sme_exception_el(CPUARMState *env, int el) return 0; } =20 +/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */ +static bool sme_fa64(CPUARMState *env, int el) +{ + if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) { + return false; + } + + if (el <=3D 1 && !el_is_in_host(env, el)) { + if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) { + return false; + } + } + if (el <=3D 2 && arm_is_el2_enabled(env)) { + if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) { + return false; + } + } + if (arm_feature(env, ARM_FEATURE_EL3)) { + if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) { + return false; + } + } + + return true; +} + /* * Given that SVE is enabled, return the vector length for EL. */ @@ -11312,6 +11338,21 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMStat= e *env, int fp_el, DP_TBFLAG_ANY(flags, PSTATE__IL, 1); } =20 + /* + * The SME exception we are testing for is raised via + * AArch64.CheckFPAdvSIMDEnabled(), and for AArch32 this is called + * when EL1 is using A64 or EL2 using A64 and !TGE. + * See AArch32.CheckAdvSIMDOrFPEnabled(). + */ + if (el =3D=3D 0 + && FIELD_EX64(env->svcr, SVCR, SM) + && (!arm_is_el2_enabled(env) + || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE))) + && arm_el_is_aa64(env, 1) + && !sme_fa64(env, el)) { + DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1); + } + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } =20 @@ -11361,6 +11402,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState= *env, int el, int fp_el, } if (FIELD_EX64(env->svcr, SVCR, SM)) { DP_TBFLAG_A64(flags, PSTATE_SM, 1); + DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el)= ); } DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a5f8a6c771..7fab7f64f8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1155,7 +1155,7 @@ static void do_vec_ld(DisasContext *s, int destidx, i= nt element, * unallocated-encoding checks (otherwise the syndrome information * for the resulting exception will be incorrect). */ -static bool fp_access_check(DisasContext *s) +static bool fp_access_check_only(DisasContext *s) { if (s->fp_excp_el) { assert(!s->fp_access_checked); @@ -1170,6 +1170,19 @@ static bool fp_access_check(DisasContext *s) return true; } =20 +static bool fp_access_check(DisasContext *s) +{ + if (!fp_access_check_only(s)) { + return false; + } + if (s->sme_trap_nonstreaming && s->is_nonstreaming) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_Streaming, false)); + return false; + } + return true; +} + /* Check that SVE access is enabled. If it is, return true. * If not, emit code to generate an appropriate exception and return false. */ @@ -1994,7 +2007,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, default: g_assert_not_reached(); } - if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { + if ((ri->type & ARM_CP_FPU) && !fp_access_check_only(s)) { return; } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { return; @@ -14530,6 +14543,23 @@ static void disas_data_proc_simd_fp(DisasContext *= s, uint32_t insn) } } =20 +/* + * Include the generated SME FA64 decoder. + */ + +#include "decode-sme-fa64.c.inc" + +static bool trans_OK(DisasContext *s, arg_OK *a) +{ + return true; +} + +static bool trans_FAIL(DisasContext *s, arg_OK *a) +{ + s->is_nonstreaming =3D true; + return true; +} + /** * is_guarded_page: * @env: The cpu environment @@ -14657,6 +14687,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->mte_active[1] =3D EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE); dc->pstate_sm =3D EX_TBFLAG_A64(tb_flags, PSTATE_SM); dc->pstate_za =3D EX_TBFLAG_A64(tb_flags, PSTATE_ZA); + dc->sme_trap_nonstreaming =3D EX_TBFLAG_A64(tb_flags, SME_TRAP_NONSTRE= AMING); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; @@ -14805,6 +14836,11 @@ static void aarch64_tr_translate_insn(DisasContext= Base *dcbase, CPUState *cpu) } } =20 + s->is_nonstreaming =3D false; + if (s->sme_trap_nonstreaming) { + disas_sme_fa64(s, insn); + } + switch (extract32(insn, 25, 4)) { case 0x0: if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) { diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 82fdbcae53..bd5ae27d09 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -234,6 +234,18 @@ static bool vfp_access_check_a(DisasContext *s, bool i= gnore_vfp_enabled) return false; } =20 + /* + * Note that rebuild_hflags_a32 has already accounted for being in EL0 + * and the higher EL in A64 mode, etc. Unlike A64 mode, there do not + * appear to be any insns which touch VFP which are allowed. + */ + if (s->sme_trap_nonstreaming) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_Streaming, + s->base.pc_next - s->pc_curr =3D=3D= 2)); + return false; + } + if (!s->vfp_enabled && !ignore_vfp_enabled) { assert(!arm_dc_feature(s, ARM_FEATURE_M)); unallocated_encoding(s); diff --git a/target/arm/translate.c b/target/arm/translate.c index 6617de775f..4ffb095c73 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9378,6 +9378,8 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) dc->vec_len =3D EX_TBFLAG_A32(tb_flags, VECLEN); dc->vec_stride =3D EX_TBFLAG_A32(tb_flags, VECSTRIDE); } + dc->sme_trap_nonstreaming =3D + EX_TBFLAG_A32(tb_flags, SME_TRAP_NONSTREAMING); } dc->cp_regs =3D cpu->cp_regs; dc->features =3D env->features; diff --git a/target/arm/meson.build b/target/arm/meson.build index 6dd7e93643..87e911b27f 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,6 +1,7 @@ gen =3D [ decodetree.process('sve.decode', extra_args: '--decode=3Ddisas_sve'), decodetree.process('sme.decode', extra_args: '--decode=3Ddisas_sme'), + decodetree.process('sme-fa64.decode', extra_args: '--static-decode=3Ddis= as_sme_fa64'), decodetree.process('neon-shared.decode', extra_args: '--decode=3Ddisas_n= eon_shared'), decodetree.process('neon-dp.decode', extra_args: '--decode=3Ddisas_neon_= dp'), decodetree.process('neon-ls.decode', extra_args: '--decode=3Ddisas_neon_= ls'), --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656390757458579.2861271919128; Mon, 27 Jun 2022 21:32:37 -0700 (PDT) Received: from localhost ([::1]:42746 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o62tw-0000UT-7k for importer@patchew.org; Tue, 28 Jun 2022 00:32:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36830) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62jH-0001Il-NK for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:35 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:33375) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jF-0003eG-QE for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:35 -0400 Received: by mail-pl1-x636.google.com with SMTP id n10so10025066plp.0 for ; Mon, 27 Jun 2022 21:21:33 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.21.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:21:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BrRYGwzjzVwnaJEo7+6hrwlrxFObfEt4K9E/YNerK6s=; b=mBFY84eSCfdHPekN0KwQG3dADRKUWO2WmhWFvGbHUbji+F9BpLBUp5lDidJkss3W94 YExJFpfhX/BuXVD+J9XRkNDYTtUsUUA1kOsknNkzZuzp15ebq5rbbSotdJ5R/tDFq5j2 Gb8ZDlktNsOvjDwYCzXc+XIS8Qvj9q9eiEammff2DgpPStGi3XN4J18+oR1oSNv+qNZX 30Y0FBT4jr7a9FwhVYSrVL8AAzRUf6Khf073mHJpng/Qt6w/hhHYgs6McwcGz3Y3N68d 2gIJI2ZhKXGFtn4gja6TgkGSt+mJK+tS5NSpUad2JPSmgYuIuhOjbTi8SXbBVvbvn6yK Gqwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BrRYGwzjzVwnaJEo7+6hrwlrxFObfEt4K9E/YNerK6s=; b=oDv75gI02POCCUY+UD+LVwUMQ8oMHddyeQu8xcgTY8ohvjDQ+ZHb68mL6ogf84LhBo 5nOzJ7FG1eMSvLcfQGht3ML+plWk/p1Q5wwBmdyftD6l2EpWTYyCsc53ZRG860PfYFuK vj6UxycNkOF8YP4POePAHtwSBIJkV2F3mjxWKaUcxa4tJQiImDITlrbyCwySfwInQ0rG 8mkWSAz9GEjxj6gbrXznliwGTkE4ssemMSnoy79tJ837kyHvzPPtOHUO+XHAxBwzvp++ wQ54tq+aIhV4IHeK3GQ0cNtwluBUg6urxKRKEGEE42utHhR1SmzYexuul7OKBxPKj3wH P2yw== X-Gm-Message-State: AJIora8AvwvKl7jaMSI8oPmZmrtu0BFNsjNH01WkvDqEW5MamMpFHLa1 LAPh8BTHehNLqBDEYg/KE5eYGptYnDWFEQ== X-Google-Smtp-Source: AGRyM1vtYpK4qTqiUAxaaj13fiZRP6Lt6rpEv9p7eJ2xwImREPgZIXOz5QY1pgxCrHDtWcs4PVEtFQ== X-Received: by 2002:a17:902:f2d3:b0:169:77a:2e82 with SMTP id h19-20020a170902f2d300b00169077a2e82mr1699122plc.146.1656390092459; Mon, 27 Jun 2022 21:21:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 04/45] target/arm: Mark ADR as non-streaming Date: Tue, 28 Jun 2022 09:50:36 +0530 Message-Id: <20220628042117.368549-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656390758859100001 Content-Type: text/plain; charset="utf-8" Mark ADR as a non-streaming instruction, which should trap if full a64 support is not enabled in streaming mode. Removing entries from sme-fa64.decode is an easy way to see what remains to be done. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.h | 7 +++++++ target/arm/sme-fa64.decode | 1 - target/arm/translate-sve.c | 8 ++++---- 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index cbc907c751..e2e619dab2 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -566,4 +566,11 @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int = op); static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); } =20 +#define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...) \ + static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ + { \ + s->is_nonstreaming =3D true; \ + return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \ + } + #endif /* TARGET_ARM_TRANSLATE_H */ diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 4c2569477d..bce717ae5f 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -58,7 +58,6 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advan= ced SIMD cryptography e # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) =20 -FAIL 0000 0100 --1- ---- 1010 ---- ---- ---- # ADR FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT FAIL 0010 0101 --01 100- 1111 000- ---0 ---- # RDFFR, RDFFRS diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 62b5f3040c..5d1db0d3ff 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1320,10 +1320,10 @@ static bool do_adr(DisasContext *s, arg_rrri *a, ge= n_helper_gvec_3 *fn) return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm); } =20 -TRANS_FEAT(ADR_p32, aa64_sve, do_adr, a, gen_helper_sve_adr_p32) -TRANS_FEAT(ADR_p64, aa64_sve, do_adr, a, gen_helper_sve_adr_p64) -TRANS_FEAT(ADR_s32, aa64_sve, do_adr, a, gen_helper_sve_adr_s32) -TRANS_FEAT(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u32) +TRANS_FEAT_NONSTREAMING(ADR_p32, aa64_sve, do_adr, a, gen_helper_sve_adr_p= 32) +TRANS_FEAT_NONSTREAMING(ADR_p64, aa64_sve, do_adr, a, gen_helper_sve_adr_p= 64) +TRANS_FEAT_NONSTREAMING(ADR_s32, aa64_sve, do_adr, a, gen_helper_sve_adr_s= 32) +TRANS_FEAT_NONSTREAMING(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u= 32) =20 /* *** SVE Integer Misc - Unpredicated Group --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16563910179947.590144327789403; Mon, 27 Jun 2022 21:36:57 -0700 (PDT) Received: from localhost ([::1]:51430 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o62y8-0006YF-Vb for importer@patchew.org; Tue, 28 Jun 2022 00:36:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62jK-0001Np-PZ for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:38 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:40797) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jH-0003em-Vk for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:37 -0400 Received: by mail-pg1-x529.google.com with SMTP id 9so11009565pgd.7 for ; Mon, 27 Jun 2022 21:21:35 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:21:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1GgZc9nURd8Ki/xGkxNJXDBbrbUEmb8e2LeVeo/xY5Y=; b=ftzrPRJOXPNLUS1dzYc+neLQ9r1o+tLefWD+Jbqsdw1VUFuQ8I+iMFE7UtAXn6NJ9y AVGe4feLBC1pD4MGJd7sqNz0xbvUMG0TENMMwW4Pot13eDRz7Xql/3sQjZe04kDUcERZ 2NqU8QRH+MgNdzI4yXzisByRZ5GXhLzbenfTvdoUJ9Jsb7q/7byjyhRRTOQDlEbbh2ir 2tnyIYPYl1orOmFDHxW+VS6j7tHGE316Kev25aJx8m8BPAkgVFZeu9nUbvAVRJMVxztW xQkktUcaLt/cVJeomdvp1BK6I/YW9HsGQt9mVBSIaJAKZyw/ovM4dhS7wXMO5+L9+QmH iRvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1GgZc9nURd8Ki/xGkxNJXDBbrbUEmb8e2LeVeo/xY5Y=; b=HSMq6eEmvN7LLb/fo2vMhq+xxsoyXoksuQ7rQ2jDrc/NT7R6zrHrmmAexPgkBBmoEL jbUwVGxsaEBOAW8qSUR8bxNsu+g5T4KAwjiqdUOjzfxktKTu9TkEJEnubtC88QVvYdnk vPfncVIXS3VKRBKhlXcoFyblHjAdoHgwItzIpLHjj9XxbfzLMF9MPhDxToNalvx27ia4 ri3jv6NC6x6fjvx76uNCQtqzevO2Zlq+2R8m4SajIwju81n2lwwMtbZad7fk0E8O6z/r lgby3R46BoAOC7Fu5wX1rs1xv0jT56PpAq/BDkCVtbb8jKuPppPNljn5RLBoQ5gw9laS H6ww== X-Gm-Message-State: AJIora9CK4F82zD0vVi8ngf+C2/XFyttn876Fcp3YJ+m2U6z+rpY4COB VECa4z1J/MADdQypdMxli/4PtRKXfbjFrw== X-Google-Smtp-Source: AGRyM1u/33IP7xQIAgzkaGU+o/fAuCcTW7EzIxhHi9aXdwSKWErqzXQDlFwwi/ciZkN1xMv5A32eZw== X-Received: by 2002:a63:8848:0:b0:40d:e25:dd99 with SMTP id l69-20020a638848000000b0040d0e25dd99mr15640890pgd.603.1656390094499; Mon, 27 Jun 2022 21:21:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 05/45] target/arm: Mark RDFFR, WRFFR, SETFFR as non-streaming Date: Tue, 28 Jun 2022 09:50:37 +0530 Message-Id: <20220628042117.368549-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656391020008100003 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/sme-fa64.decode | 2 -- target/arm/translate-sve.c | 9 ++++++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index bce717ae5f..a48f164ed4 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -60,8 +60,6 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advan= ced SIMD cryptography e =20 FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT -FAIL 0010 0101 --01 100- 1111 000- ---0 ---- # RDFFR, RDFFRS -FAIL 0010 0101 --10 1--- 1001 ---- ---- ---- # WRFFR, SETFFR FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b r= esult) FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 5d1db0d3ff..d6faec15fe 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1785,7 +1785,8 @@ static bool do_predset(DisasContext *s, int esz, int = rd, int pat, bool setflag) TRANS_FEAT(PTRUE, aa64_sve, do_predset, a->esz, a->rd, a->pat, a->s) =20 /* Note pat =3D=3D 31 is #all, to set all elements. */ -TRANS_FEAT(SETFFR, aa64_sve, do_predset, 0, FFR_PRED_NUM, 31, false) +TRANS_FEAT_NONSTREAMING(SETFFR, aa64_sve, + do_predset, 0, FFR_PRED_NUM, 31, false) =20 /* Note pat =3D=3D 32 is #unimp, to set no elements. */ TRANS_FEAT(PFALSE, aa64_sve, do_predset, 0, a->rd, 32, false) @@ -1799,11 +1800,13 @@ static bool trans_RDFFR_p(DisasContext *s, arg_RDFF= R_p *a) .rd =3D a->rd, .pg =3D a->pg, .s =3D a->s, .rn =3D FFR_PRED_NUM, .rm =3D FFR_PRED_NUM, }; + + s->is_nonstreaming =3D true; return trans_AND_pppp(s, &alt_a); } =20 -TRANS_FEAT(RDFFR, aa64_sve, do_mov_p, a->rd, FFR_PRED_NUM) -TRANS_FEAT(WRFFR, aa64_sve, do_mov_p, FFR_PRED_NUM, a->rn) +TRANS_FEAT_NONSTREAMING(RDFFR, aa64_sve, do_mov_p, a->rd, FFR_PRED_NUM) +TRANS_FEAT_NONSTREAMING(WRFFR, aa64_sve, do_mov_p, FFR_PRED_NUM, a->rn) =20 static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a, void (*gen_fn)(TCGv_i32, TCGv_ptr, --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656390525856718.7917789959881; Mon, 27 Jun 2022 21:28:45 -0700 (PDT) Received: from localhost ([::1]:35674 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o62qC-0003zJ-Po for importer@patchew.org; Tue, 28 Jun 2022 00:28:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36906) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62jM-0001RH-SJ for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:40 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:44803) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jK-0003fP-QA for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:40 -0400 Received: by mail-pg1-x532.google.com with SMTP id v126so6846324pgv.11 for ; Mon, 27 Jun 2022 21:21:37 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.21.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:21:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h76SjsaX+1rVxX8KDTWd9JukUhZC70d2S6ar++qWxxM=; b=tK3NSonzpdYbaCx8Dt9bz38Gf0QjJN3f2bcqCUiXBeoKLtryImD+FpaxKjFBCf6apR n/sQBW8Yxc6rqVy34jgEiToZRNe13tgtpUquXT0oZmv/5dNAOp6KZOoImtY5hPgtdMkC jc/CVVfkbmKpVaellB0+13/lCiY6qck0bcTWV0vakP+HAMuvyyp9rsDqIu4Ih06A0eyl PnZI1SNG1w2df2YRKwdHsrFPzt2PaqJJb/TbebnVTFX5TRBjq7PCJ18kIZADWhJ8IV3u K1GtLxqJW5C8cpZVa9ia3B9IsDgxnk4cUpnEojGOy/VVd3ucEUj5Fdl1mwnv2rslSooI oA2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h76SjsaX+1rVxX8KDTWd9JukUhZC70d2S6ar++qWxxM=; b=kh7/6SspPDFK2snfdakPQSWBpMxT2bJhLbbiRAkWrQz7Tgk6Mrl2t3/F5Mx8+s/wKf ovg/Ks6tuGGo6aLLZV7zwm+GGTFZdwDZajeFmu5CZhYp0BJU3XVJ3KY723W08Sh5hp7E fkPhsxZKXOeWMY6lyFRBXU4I60MP4rNFSVoRGUn4r8oQZGw+wIQ67Mm/l/pdKdZhBvLH EqXBADCvx7uQaSop3ZETtKeGArhOxVmHRvBOoQOFffrbZx9SjfX8i6MZuj65BCHLsItP iLB0hMVZXvoXqlQStx21FWYJlvDnnSjn3zupdWkPqhh6XN8wBCGC1FS3NvMYBuNyQ5a8 eJkw== X-Gm-Message-State: AJIora9jzog6i0Y+sNdd7NWmys3ETuQl/sq0D7tEb4TEjvoIW9B781mn zOS5fFESSKLCmVz4CRDJDsF/fLXenSF88A== X-Google-Smtp-Source: AGRyM1tJljGcjpy15NSa1CrgomZzeDH91Ma0v3jHS78ATbq7cVDFYqBJIpW93tWFg1y4Tgbv4/Tg5Q== X-Received: by 2002:a05:6a00:1a46:b0:525:82e2:a0d3 with SMTP id h6-20020a056a001a4600b0052582e2a0d3mr2612299pfv.48.1656390096570; Mon, 27 Jun 2022 21:21:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streaming Date: Tue, 28 Jun 2022 09:50:38 +0530 Message-Id: <20220628042117.368549-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656390527293100001 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 22 ++++++++++++---------- 2 files changed, 12 insertions(+), 13 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index a48f164ed4..c25bad5ee5 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -58,9 +58,6 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advan= ced SIMD cryptography e # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) =20 -FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA -FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT -FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b r= esult) FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index d6faec15fe..ae48040aa4 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1333,14 +1333,15 @@ static gen_helper_gvec_2 * const fexpa_fns[4] =3D { NULL, gen_helper_sve_fexpa_h, gen_helper_sve_fexpa_s, gen_helper_sve_fexpa_d, }; -TRANS_FEAT(FEXPA, aa64_sve, gen_gvec_ool_zz, - fexpa_fns[a->esz], a->rd, a->rn, 0) +TRANS_FEAT_NONSTREAMING(FEXPA, aa64_sve, gen_gvec_ool_zz, + fexpa_fns[a->esz], a->rd, a->rn, 0) =20 static gen_helper_gvec_3 * const ftssel_fns[4] =3D { NULL, gen_helper_sve_ftssel_h, gen_helper_sve_ftssel_s, gen_helper_sve_ftssel_d, }; -TRANS_FEAT(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz, ftssel_fns[a->esz], a, = 0) +TRANS_FEAT_NONSTREAMING(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz, + ftssel_fns[a->esz], a, 0) =20 /* *** SVE Predicate Logical Operations Group @@ -2536,7 +2537,8 @@ TRANS_FEAT(TRN2_q, aa64_sve_f64mm, gen_gvec_ool_arg_z= zz, static gen_helper_gvec_3 * const compact_fns[4] =3D { NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d }; -TRANS_FEAT(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz, compact_fns[a->esz], a= , 0) +TRANS_FEAT_NONSTREAMING(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz, + compact_fns[a->esz], a, 0) =20 /* Call the helper that computes the ARM LastActiveElement pseudocode * function, scaled by the element size. This includes the not found @@ -6374,22 +6376,22 @@ static gen_helper_gvec_3 * const bext_fns[4] =3D { gen_helper_sve2_bext_b, gen_helper_sve2_bext_h, gen_helper_sve2_bext_s, gen_helper_sve2_bext_d, }; -TRANS_FEAT(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, - bext_fns[a->esz], a, 0) +TRANS_FEAT_NONSTREAMING(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, + bext_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const bdep_fns[4] =3D { gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h, gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d, }; -TRANS_FEAT(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, - bdep_fns[a->esz], a, 0) +TRANS_FEAT_NONSTREAMING(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, + bdep_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const bgrp_fns[4] =3D { gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h, gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d, }; -TRANS_FEAT(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, - bgrp_fns[a->esz], a, 0) +TRANS_FEAT_NONSTREAMING(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz, + bgrp_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const cadd_fns[4] =3D { gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h, --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656390788435218.60900237607984; Mon, 27 Jun 2022 21:33:08 -0700 (PDT) Received: from localhost ([::1]:44560 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o62uR-0001qD-D2 for importer@patchew.org; Tue, 28 Jun 2022 00:33:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36926) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62jO-0001Ti-9Y for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:43 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:43813) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jM-0003fe-3F for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:41 -0400 Received: by mail-pj1-x1035.google.com with SMTP id dw10-20020a17090b094a00b001ed00a16eb4so11432400pjb.2 for ; Mon, 27 Jun 2022 21:21:39 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.21.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:21:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2QmVLtbyxFuao4V1znU2cRG0WtNL/n+crCqH//cwECY=; b=QAHVBfyxYinr1OKMHpdZIu3Jmf9BNDUYbrVCkbdHleuEC/eMGrCBN6zN8x6vazhrU1 AP/oniKlxOegD4z6D6RZ+aOJscJYqtNqj3BpMmg/YbZqGQgg3aL5A4RvrJR3I/BBFJDy bev/+DHMkqcwdqOpmf9sL7mZohmkMTY5Ip4y5gluOHRjyNSjaME9eiGzsESAohIudUx/ GznGeoAdvpyr1c0e3SKxqxgvQ2YlXCSZ81EZwsctrgwZK4vtR9MvXKm/mAHeRf2k1Nf4 WMbHF1/cqjf2wqBljsSum1CjDgT4N1EWYP/0NYq6NE7Puj8uh+A42Avrv20CkaW0jroz 2dNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2QmVLtbyxFuao4V1znU2cRG0WtNL/n+crCqH//cwECY=; b=bv0rAvHGqp0yik/cUJo/HHkF20+85W/JP0Sq1XS9EndsFbxk/R/we8VWQzQOex2qMm PdXXxhZmwtIrI2SkFd6k+NsDV9BbAvtLLl+Hg08tjuglcX061C1svMwq8F81YT7nXuCL juNiPWjq0C51uhRBhq/qEUOgs1lnMqf6I+kXu23AWKJ1Ttx4/nHcAxovIkPCquwhh9Py vWPd7Tk4NYSzIawSWsjT5WrglGp9xSbo9nBliEp1Qyh2IK/fofBJ7hU3L9jR70jvmpN1 pm74X3+T5TYNQg2lzHfoMRWjILtupZRN3PJCQcoU/Xq6uT8QJQNuq0PqkMm0MrC6OJzG 6/Ug== X-Gm-Message-State: AJIora+K/SatU/vCmPSan6/Qf9Zno42isXjDYW0TkOwRh0YP1MNWob/V SNHX/bmuWFcjM8WNIyhwjiEjLGNM7ZExAA== X-Google-Smtp-Source: AGRyM1sa7ZaL4x2Wy5oTxzKUmhbza8omRoaZY++CQ2a/QPEjyXT6NRcScqygubFQjFOiXG/j0mjwWQ== X-Received: by 2002:a17:902:ef92:b0:16a:1ef1:22db with SMTP id iz18-20020a170902ef9200b0016a1ef122dbmr1653841plb.2.1656390098754; Mon, 27 Jun 2022 21:21:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 07/45] target/arm: Mark PMULL, FMMLA as non-streaming Date: Tue, 28 Jun 2022 09:50:39 +0530 Message-Id: <20220628042117.368549-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656390788944100001 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson --- target/arm/sme-fa64.decode | 2 -- target/arm/translate-sve.c | 18 ++++++++++-------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index c25bad5ee5..c75a94e0fc 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -58,8 +58,6 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advan= ced SIMD cryptography e # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) =20 -FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b r= esult) -FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index ae48040aa4..130432654e 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -6194,8 +6194,8 @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_e= sz *a, bool sel) return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel); } =20 -TRANS_FEAT(PMULLB, aa64_sve2, do_trans_pmull, a, false) -TRANS_FEAT(PMULLT, aa64_sve2, do_trans_pmull, a, true) +TRANS_FEAT_NONSTREAMING(PMULLB, aa64_sve2, do_trans_pmull, a, false) +TRANS_FEAT_NONSTREAMING(PMULLT, aa64_sve2, do_trans_pmull, a, true) =20 static gen_helper_gvec_3 * const saddw_fns[4] =3D { NULL, gen_helper_sve2_saddw_h, @@ -7125,10 +7125,12 @@ DO_ZPZZ_FP(FMINP, aa64_sve2, sve2_fminp_zpzz) * SVE Integer Multiply-Add (unpredicated) */ =20 -TRANS_FEAT(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_s, - a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR) -TRANS_FEAT(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_d, - a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR) +TRANS_FEAT_NONSTREAMING(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, + gen_helper_fmmla_s, a->rd, a->rn, a->rm, a->ra, + 0, FPST_FPCR) +TRANS_FEAT_NONSTREAMING(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, + gen_helper_fmmla_d, a->rd, a->rn, a->rm, a->ra, + 0, FPST_FPCR) =20 static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] =3D { NULL, gen_helper_sve2_sqdmlal_zzzw_h, @@ -7301,8 +7303,8 @@ TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_ar= g_zzzz, TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_ool_arg_zzxz, gen_helper_gvec_bfdot_idx, a) =20 -TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, - gen_helper_gvec_bfmmla, a, 0) +TRANS_FEAT_NONSTREAMING(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, + gen_helper_gvec_bfmmla, a, 0) =20 static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) { --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165639075442266.96704466027586; Mon, 27 Jun 2022 21:32:34 -0700 (PDT) Received: from localhost ([::1]:42472 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o62tt-0000JA-CO for importer@patchew.org; Tue, 28 Jun 2022 00:32:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36976) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62jR-0001VW-0e for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:45 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:51719) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jO-0003g2-Dn for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:44 -0400 Received: by mail-pj1-x102a.google.com with SMTP id l2so10192691pjf.1 for ; Mon, 27 Jun 2022 21:21:41 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.21.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:21:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SksqHNC/l5yANeknCXnVaq3xFh4B6hnCEdNlTHjrkLE=; b=j4S5+zkenHHxqZGQczeQSz/c/aCaKpjxjusfdX+FeL79pSwkrG+T8Im82Ua2LX4aJj qhrje18BiWb7HBenSuhMtOliiAQ42aPxwn2X0NWE+M42wPEuxhcO1qcWTmC1LIEV2caC KQ+D0qfx9D8cxcwDZaSc9Q/+M3GcrTayzd2IkgjOsZz9z55km7SHuZqgmL6739HPgs3f /ZHzxwqUYKAfli6kByERe2mmYVE4HN6LM5MuiwBOXYw3WwbGp94ABVTuuNrG8d4znyBv EQqJjYo8ppur75LT3jT5nfyf/9Od2jtKmZ7TbGg6lZuqGqGT9YmB6y7j7Xt9CQghANJ5 e4yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SksqHNC/l5yANeknCXnVaq3xFh4B6hnCEdNlTHjrkLE=; b=Z7svg/VgI/Lx72qZSoNbRUWYyImI9S6MDJ03tCFqmWQXLiHMNa5oqT9Q1eccMZ8yVm HIUDTJMOxPlSfbD7FrCL/Ui16eutFmbIak3WBNR3nvbRr90Whw1KlywMhbK8D7f276sC w8Je9MsXIBHWL86RkgZMS8Gg169m4d/veZwJZdFHIFnsNOj7YhU1qxzo8BK2FoX4SMkP ehe6rB5Fo6J8hh2Ajik58roKHTeXj/To/Uh/7n6amdmBuBl3desrz9Mj220JN+cmdKVB 0tYouJb+poznV5KWru7+kkx7Bt95Fb5i9a+XQqd+EzLrxd+/2Qk+u38mOLtDJItFP6Kq B8+w== X-Gm-Message-State: AJIora/apiQZeeCk23uz2HAm7ZU8flzXKZxUZxkUj2COj9JWXKc2wc0J dz/LRpdfz9zLJMQhJlE3xBFnCQn4DYV4lg== X-Google-Smtp-Source: AGRyM1uSAw2gaWNIX9nYnzccDBNDI2pCWllbqneL4g7rQtRhicyiORA/E5joRf1ehNy6y1B+ftnakQ== X-Received: by 2002:a17:90b:503:b0:1e2:f129:5135 with SMTP id r3-20020a17090b050300b001e2f1295135mr19321010pjz.22.1656390101040; Mon, 27 Jun 2022 21:21:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 08/45] target/arm: Mark FTSMUL, FTMAD, FADDA as non-streaming Date: Tue, 28 Jun 2022 09:50:40 +0530 Message-Id: <20220628042117.368549-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656390754807100001 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 15 +++++++++++---- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index c75a94e0fc..f6e10e4bbe 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -58,9 +58,6 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advan= ced SIMD cryptography e # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) =20 -FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL -FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD -FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/cryp= to instructions FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT = load (vector+scalar) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 130432654e..9d0a89215c 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3861,9 +3861,9 @@ static gen_helper_gvec_3_ptr * const ftmad_fns[4] =3D= { NULL, gen_helper_sve_ftmad_h, gen_helper_sve_ftmad_s, gen_helper_sve_ftmad_d, }; -TRANS_FEAT(FTMAD, aa64_sve, gen_gvec_fpst_zzz, - ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm, - a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_FPCR) +TRANS_FEAT_NONSTREAMING(FTMAD, aa64_sve, gen_gvec_fpst_zzz, + ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm, + a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_FPCR) =20 /* *** SVE Floating Point Accumulating Reduction Group @@ -3886,6 +3886,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz= *a) if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming =3D true; if (!sve_access_check(s)) { return true; } @@ -3923,12 +3924,18 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_e= sz *a) DO_FP3(FADD_zzz, fadd) DO_FP3(FSUB_zzz, fsub) DO_FP3(FMUL_zzz, fmul) -DO_FP3(FTSMUL, ftsmul) DO_FP3(FRECPS, recps) DO_FP3(FRSQRTS, rsqrts) =20 #undef DO_FP3 =20 +static gen_helper_gvec_3_ptr * const ftsmul_fns[4] =3D { + NULL, gen_helper_gvec_ftsmul_h, + gen_helper_gvec_ftsmul_s, gen_helper_gvec_ftsmul_d +}; +TRANS_FEAT_NONSTREAMING(FTSMUL, aa64_sve, gen_gvec_fpst_arg_zzz, + ftsmul_fns[a->esz], a, 0) + /* *** SVE Floating Point Arithmetic - Predicated Group */ --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656390317724450.25489493422924; Mon, 27 Jun 2022 21:25:17 -0700 (PDT) Received: from localhost ([::1]:52632 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o62mq-0004ke-N0 for importer@patchew.org; Tue, 28 Jun 2022 00:25:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37010) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62jS-0001XZ-Q7 for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:46 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:39493) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jQ-0003gU-KR for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:46 -0400 Received: by mail-pl1-x632.google.com with SMTP id x20so4370438plx.6 for ; Mon, 27 Jun 2022 21:21:44 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.21.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:21:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/Hax6yB4716XxH/pP7eizCJLrlEm4CvxdVgM8qrNTVI=; b=k1ZWGrkLf+SL3rEPFJOhJLtLJgvEuTsNtosdLJaNb5onPm6jPJ8SxBoa/j7CDutylV W+SZWNEQ013+oLwAyS4Mmg4wh90Q7wX2Hgh3c2yerllIXbhc0YAEOewlBmR6q+oCpU0Q E991g14lAHrJsjALs7pLoyeblRGw7rvVDLR+uMW1fMiDLZo+EhV5YiRy2zLGWcB6QBgL /M1/oMySkQ5tvaaQIKTLxs3WO6ZdUh2lao3pOLOnAEARX+VfBwFl1YGrs2tcGV+zlKRX jACR0rnpULltW8CIY0O0O0iLzLZHFvn0zNShDsojUEPYw1boPESDwtZtfmsG0Xm6R5e8 YLCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/Hax6yB4716XxH/pP7eizCJLrlEm4CvxdVgM8qrNTVI=; b=sz69D8RlzR1eNGLbR3s9iWpcno/atI2HcHQmDZj10Y8jZolBZg6SW2Ae1QzxIv9QUM w3nNygeM1Sez9Hdtwwx4mo5oSaJRvivIlS3b1sJySHCab/DQqP8B67UKmKGzZBkbljGt mFNllOGN33MTXUDBgHrHiAAbiDCJHrjtiPSE0eP6NZUl6+kSZfdmrLkU3TtkTpNhKPVd WTJxGiLSamvR93FO+m6QyK8SlMlUJZHLOyXx4WOIdTNCr38e4YVRFJkMF/Jz1wJJ84D8 eZYRqK17RqJZB+fd6LutGCPNIKuZWYD9la7pEt1tDu7FJh5l2FH5i6mJXFcJBXuAGwyo DmCA== X-Gm-Message-State: AJIora8erwGUjwSbcb5ORIoF2wlLk0RJ4yo9l4NbCRcW5+ltX2ZKRBw0 szU5cxEwLi4Zdve4Bxs/hxpvkYgGqH7/Bg== X-Google-Smtp-Source: AGRyM1t7wfTisuP9+6vJI6liu/8MgW49mzD8yV4Fo6hv1UoJUiIjfXlFBq8sXBXM8R4/3u89VX4KTw== X-Received: by 2002:a17:902:c2c7:b0:16a:3132:bc53 with SMTP id c7-20020a170902c2c700b0016a3132bc53mr1731692pla.90.1656390103202; Mon, 27 Jun 2022 21:21:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 09/45] target/arm: Mark SMMLA, UMMLA, USMMLA as non-streaming Date: Tue, 28 Jun 2022 09:50:41 +0530 Message-Id: <20220628042117.368549-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656390318095100001 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/sme-fa64.decode | 1 - target/arm/translate-sve.c | 12 ++++++------ 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index f6e10e4bbe..d3039a8bb2 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -58,7 +58,6 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advan= ced SIMD cryptography e # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) =20 -FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/cryp= to instructions FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT = load (vector+scalar) FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather pref= etch (vector+imm) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 9d0a89215c..7524d713ab 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7298,12 +7298,12 @@ TRANS_FEAT(FMLALT_zzxw, aa64_sve2, do_FMLAL_zzxw, a= , false, true) TRANS_FEAT(FMLSLB_zzxw, aa64_sve2, do_FMLAL_zzxw, a, true, false) TRANS_FEAT(FMLSLT_zzxw, aa64_sve2, do_FMLAL_zzxw, a, true, true) =20 -TRANS_FEAT(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, - gen_helper_gvec_smmla_b, a, 0) -TRANS_FEAT(USMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, - gen_helper_gvec_usmmla_b, a, 0) -TRANS_FEAT(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, - gen_helper_gvec_ummla_b, a, 0) +TRANS_FEAT_NONSTREAMING(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, + gen_helper_gvec_smmla_b, a, 0) +TRANS_FEAT_NONSTREAMING(USMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, + gen_helper_gvec_usmmla_b, a, 0) +TRANS_FEAT_NONSTREAMING(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, + gen_helper_gvec_ummla_b, a, 0) =20 TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz, gen_helper_gvec_bfdot, a, 0) --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656391015692164.31716077843714; Mon, 27 Jun 2022 21:36:55 -0700 (PDT) Received: from localhost ([::1]:51130 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o62y6-0006Kb-CS for importer@patchew.org; Tue, 28 Jun 2022 00:36:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62jU-0001Zz-Ju for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:48 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:36576) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jS-0003gy-Qc for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:48 -0400 Received: by mail-pj1-x102a.google.com with SMTP id c6-20020a17090abf0600b001eee794a478so3905963pjs.1 for ; Mon, 27 Jun 2022 21:21:46 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.21.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:21:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Olqir63f5/Kf497Jw21bcj1fKrQr3VFFu+FKw75pZwk=; b=bfYhMfmL4GOvEmNB83NFv7ZbJn2xG2jPRxrvf1Ex9XozX66c1VdDWvm3QbDm9OxsEB F+C4EaQeg/NjWGq3wQPZIx9qdO5RvjiC5JvRkliREU4nzcf/tUBnHfAKl7tsHsmXfMYz vfygeQty2mWCRBKtCYPFNBiwCFCekmOsBrteKfY23RwffBxYCluMLXUdUPAaFc0DcnIr NWBegp7XJ8pPJ0XZ4wM8e4XU4obUkXcmCxn7qDKzO3G91gl3QLQsYK6gFlyIYKhY3T1Q yBwqn0B1ZuhuXy3ku2ki1VFSh17q/4m9IrM0Is1hZ/0ug+tn5RVA1axyRIqSKPW61ouc upUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Olqir63f5/Kf497Jw21bcj1fKrQr3VFFu+FKw75pZwk=; b=sZDzqccdpMb6xK3y63WAUPc2oeE2JoMwzTQOpYUb73+JNU+yKOMGWjCfDsBfyk4w9g v9qgYLW4JzyB+HoRMrd2o99E9Fq1uY1gbJbQWz0PXZ+dnDC0xB7O6fp9jlguHJdKRFI6 uEKDkAC2qvNsEeKNe0WHXygIKW1Xt4Z5UUBDFKRe691dj3BQB5XfSTMMH7mhgWIS924/ 9d0//EpnJyCqYXk85h+DXNgb4Y/4wbh95/QkF1PhYAsPwBAtYoJqdr+V3K3/o7JEmGas hAJX8RSHHKiyeYgWaYQBSq6a7PJtb7GAen5vvDrkvnlPAj8bISfhRhll6F0pj3X81q9V Ma3g== X-Gm-Message-State: AJIora92bG8eIjloxIroSH1MBCSgFO9znwLeU3HJ+6uhKrApNTCCfaJT 7LTUzkbreA+R46jkvcHrwbIu4vSXMIX3zg== X-Google-Smtp-Source: AGRyM1tXOsS54Y1goUNlkBsvJVLrd3FXeQvLLl73UvGD1+cT969usfjpbHOM3imqJYrE16YuJWMX4A== X-Received: by 2002:a17:90b:4f41:b0:1ed:712:fd80 with SMTP id pj1-20020a17090b4f4100b001ed0712fd80mr24306641pjb.224.1656390105386; Mon, 27 Jun 2022 21:21:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 10/45] target/arm: Mark string/histo/crypto as non-streaming Date: Tue, 28 Jun 2022 09:50:42 +0530 Message-Id: <20220628042117.368549-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656391017967100001 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/sme-fa64.decode | 1 - target/arm/translate-sve.c | 35 ++++++++++++++++++----------------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index d3039a8bb2..4683850fa5 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -58,7 +58,6 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advan= ced SIMD cryptography e # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) =20 -FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/cryp= to instructions FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT = load (vector+scalar) FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather pref= etch (vector+imm) FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather pref= etch (scalar+vector) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 7524d713ab..4c28cc9200 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7106,21 +7106,21 @@ DO_SVE2_ZZZ_NARROW(RSUBHNT, rsubhnt) static gen_helper_gvec_flags_4 * const match_fns[4] =3D { gen_helper_sve2_match_ppzz_b, gen_helper_sve2_match_ppzz_h, NULL, NULL }; -TRANS_FEAT(MATCH, aa64_sve2, do_ppzz_flags, a, match_fns[a->esz]) +TRANS_FEAT_NONSTREAMING(MATCH, aa64_sve2, do_ppzz_flags, a, match_fns[a->e= sz]) =20 static gen_helper_gvec_flags_4 * const nmatch_fns[4] =3D { gen_helper_sve2_nmatch_ppzz_b, gen_helper_sve2_nmatch_ppzz_h, NULL, NU= LL }; -TRANS_FEAT(NMATCH, aa64_sve2, do_ppzz_flags, a, nmatch_fns[a->esz]) +TRANS_FEAT_NONSTREAMING(NMATCH, aa64_sve2, do_ppzz_flags, a, nmatch_fns[a-= >esz]) =20 static gen_helper_gvec_4 * const histcnt_fns[4] =3D { NULL, NULL, gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d }; -TRANS_FEAT(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz, - histcnt_fns[a->esz], a, 0) +TRANS_FEAT_NONSTREAMING(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz, + histcnt_fns[a->esz], a, 0) =20 -TRANS_FEAT(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz, - a->esz =3D=3D 0 ? gen_helper_sve2_histseg : NULL, a, 0) +TRANS_FEAT_NONSTREAMING(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz, + a->esz =3D=3D 0 ? gen_helper_sve2_histseg : NULL, = a, 0) =20 DO_ZPZZ_FP(FADDP, aa64_sve2, sve2_faddp_zpzz) DO_ZPZZ_FP(FMAXNMP, aa64_sve2, sve2_fmaxnmp_zpzz) @@ -7234,20 +7234,21 @@ TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sve2, gen_gvec_ool_= zzzz, TRANS_FEAT(USDOT_zzzz, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, a->esz =3D=3D 2 ? gen_helper_gvec_usdot_b : NULL, a, 0) =20 -TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz, - gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt) +TRANS_FEAT_NONSTREAMING(AESMC, aa64_sve2_aes, gen_gvec_ool_zz, + gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt) =20 -TRANS_FEAT(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz, - gen_helper_crypto_aese, a, false) -TRANS_FEAT(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz, - gen_helper_crypto_aese, a, true) +TRANS_FEAT_NONSTREAMING(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz, + gen_helper_crypto_aese, a, false) +TRANS_FEAT_NONSTREAMING(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz, + gen_helper_crypto_aese, a, true) =20 -TRANS_FEAT(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, - gen_helper_crypto_sm4e, a, 0) -TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, - gen_helper_crypto_sm4ekey, a, 0) +TRANS_FEAT_NONSTREAMING(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, + gen_helper_crypto_sm4e, a, 0) +TRANS_FEAT_NONSTREAMING(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, + gen_helper_crypto_sm4ekey, a, 0) =20 -TRANS_FEAT(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a) +TRANS_FEAT_NONSTREAMING(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, + gen_gvec_rax1, a) =20 TRANS_FEAT(FCVTNT_sh, aa64_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_sh, a, 0, FPST_FPCR) --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656391234315912.2206050377289; Mon, 27 Jun 2022 21:40:34 -0700 (PDT) Received: from localhost ([::1]:59602 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o631c-0003p0-Jk for importer@patchew.org; Tue, 28 Jun 2022 00:40:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37088) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62jW-0001dO-V0 for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:51 -0400 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]:46025) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jU-0003hL-NI for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:50 -0400 Received: by mail-pg1-x52e.google.com with SMTP id 184so10986344pga.12 for ; Mon, 27 Jun 2022 21:21:48 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.21.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:21:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LkdgUQ+JvOvBJ2qAkFuSD3rXAe1IkZmBYBBm8jukjA4=; b=QbggUhIktc0UPG9RF7U2SEGR4WhLywA5SjCbibXV+ZHv2ay0YJEVb06xg7sW0BKFr1 Bshux9D3k419xa3WJdYsCXkFVxw5/L0Aeuh1lwvd3QC+D40AUIBCEOQSZuiLizuu6j1h 4YTCDKLMWQVqkX972L4rcT4KJgofLbwZWEE1YHZ/ELBQSBU0Kg8njfMAchkn8qhnMf1H PU+WI7Lja9MqjBiYX11J5P5YXrme7KckpILfis/4dx+5wS68LkFlAMSTqtNsNC5e4HAc gRmzg414/YlGTIleOkTNbqLu9gIxdcbXgtYe8SsifdC94wWlZ6FS1NF2QT+1CZW57mw6 HglA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LkdgUQ+JvOvBJ2qAkFuSD3rXAe1IkZmBYBBm8jukjA4=; b=iu52dLh06nXq/P/fYtRzI23Trhd98uKCUV0LfZp10oLGSjs1X9L5uJI7HipynDal5v ZAevlm8hsXiL/RoBkoh9/y2/EkBsAJRo1rBRnKy1VkluZPflxOH/ZVF62BN84sVfwnmH CZIWyVqmb4LqN7tddJiU9DkQLNJFhxFaSCJIRuhslDJ34gU8M51LbnW3pHV5D1/fql/m KXe/A14LkLXhtFXSb9uVDwetOih1eELxL/sw+HdCnXAdJ38+yPbRery2m0V0Ya+Ra0Iz i2Q9YE7m/XsJG4wTT/74ltoxEce43SPMAA7+hobeftaQkPqhETKuDPgniMoEyfjqSWW1 6OMQ== X-Gm-Message-State: AJIora8E7gu3o95z9fscKY/ti49hVrtGPRQGtZgsaxaTHhsWTOp0rVyS /xzU1yQuuF66VJVwu8bbKZ9zHiR7A/aU1Q== X-Google-Smtp-Source: AGRyM1s/87mdDczgQatotnePdMd83v7jk6eb95nfNnS8/m6e9WOYr51+yZnSlpuJWQnFHojPUMM9OA== X-Received: by 2002:a63:2b8c:0:b0:3fe:2062:c14b with SMTP id r134-20020a632b8c000000b003fe2062c14bmr15655533pgr.345.1656390107477; Mon, 27 Jun 2022 21:21:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 11/45] target/arm: Mark gather/scatter load/store as non-streaming Date: Tue, 28 Jun 2022 09:50:43 +0530 Message-Id: <20220628042117.368549-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656391234854100001 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/sme-fa64.decode | 9 --------- target/arm/translate-sve.c | 6 ++++++ 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 4683850fa5..711636ed30 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -58,19 +58,10 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Adv= anced SIMD cryptography e # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) =20 -FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT = load (vector+scalar) FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather pref= etch (vector+imm) FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather pref= etch (scalar+vector) -FAIL 1000 010- -01- ---- 1--- ---- ---- ---- # SVE 32-bit gather load= (vector+imm) -FAIL 1000 0100 0-0- ---- 0--- ---- ---- ---- # SVE 32-bit gather load= byte (scalar+vector) -FAIL 1000 0100 1--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load= half (scalar+vector) -FAIL 1000 0101 0--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load= word (scalar+vector) FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load= (scalar+scalar) FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load= (scalar+imm) FAIL 1010 010- -10- ---- 000- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+scalar) FAIL 1010 010- -100 ---- 001- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+imm) FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load= /prefetch -FAIL 1110 010- -00- ---- 001- ---- ---- ---- # SVE2 64-bit scatter NT= store (vector+scalar) -FAIL 1110 010- -10- ---- 001- ---- ---- ---- # SVE2 32-bit scatter NT= store (vector+scalar) -FAIL 1110 010- ---- ---- 1-0- ---- ---- ---- # SVE scatter store (sca= lar+32-bit vector) -FAIL 1110 010- ---- ---- 101- ---- ---- ---- # SVE scatter store (mis= c) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 4c28cc9200..a50b2f485b 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5669,6 +5669,7 @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1_z= prz *a) if (!dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming =3D true; if (!sve_access_check(s)) { return true; } @@ -5700,6 +5701,7 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_z= piz *a) if (!dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming =3D true; if (!sve_access_check(s)) { return true; } @@ -5734,6 +5736,7 @@ static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1= _zprz *a) if (!dc_isar_feature(aa64_sve2, s)) { return false; } + s->is_nonstreaming =3D true; if (!sve_access_check(s)) { return true; } @@ -5857,6 +5860,7 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_z= prz *a) if (!dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming =3D true; if (!sve_access_check(s)) { return true; } @@ -5887,6 +5891,7 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_z= piz *a) if (!dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming =3D true; if (!sve_access_check(s)) { return true; } @@ -5921,6 +5926,7 @@ static bool trans_STNT1_zprz(DisasContext *s, arg_ST1= _zprz *a) if (!dc_isar_feature(aa64_sve2, s)) { return false; } + s->is_nonstreaming =3D true; if (!sve_access_check(s)) { return true; } --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656391518513818.8213103673594; Mon, 27 Jun 2022 21:45:18 -0700 (PDT) Received: from localhost ([::1]:40854 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o636D-0002Gm-Dm for importer@patchew.org; Tue, 28 Jun 2022 00:45:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37114) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62jZ-0001fl-18 for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:53 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:36584) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jW-0003gT-HZ for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:52 -0400 Received: by mail-pj1-x1033.google.com with SMTP id c6-20020a17090abf0600b001eee794a478so3905893pjs.1 for ; Mon, 27 Jun 2022 21:21:49 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.21.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:21:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bb+2dMpalHOyt59eNEFEmGtiWYzqBzkHlaHMi62ekZ0=; b=p1NewcHOgtlm/r5U6mlZ/izOW7DbqNS9H0S6Bxg6QlRtmzSDoLMAQWAAABWEowMIfR n/TU1ytbPpC5o1Nk+OIfhjDLAuOCZ3G4PVVJqaw8RFyfip+gRn2IlOa7Dint62sIWIrA ApBnP+K5d+JLrYogivVsjprbw2u9RxTSndm0X+EGJLABZScwv0aewopRHVTpxNVcEf1f 6aCNIeYZ9aiHaJCXX4eJuUaynW3xKdVYLpl7rbdBmnE/PwPFqQFloFGgBda5wpH6iolp Y4QveIl7iXjD0elvtmEHyexqqf3ZiXOfDAR3lj3tgIGxJ32otM45rKJs8SuvdDH8GRTR Lz/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bb+2dMpalHOyt59eNEFEmGtiWYzqBzkHlaHMi62ekZ0=; b=BPCGZE9uCNTileuzjGE9pljtVNmQC+HAZ+uuiBUaWYeA/omG36qe4bZ7XZfLf1CUrg q717syFxKj5xLD4xqLfe4j41U1whaapdCtHTdABIxV1dXO5gkJgdnUH4JCFWMi9FDonr duIpCwa1QIVVaiLe54sx9t3UM9pDV/6pJW9frgD1kqriXqk/HGlB3q2iWUah6ZbwQlw/ Es1cH2KHU1NM+HucvH07ta27nuwrmBIPzBQ2rSzKearJkMHkWfARMeOy6yakRw2eYCn9 cy6X4a2Xm98WuSqDj0Puqw1mfTtC53CMPoQH5PWIdUoYWxOQXGoyi073cKGSIH3g72W5 /wZQ== X-Gm-Message-State: AJIora9PB9SFxlJ8rm/2cLN/8wWFmb6ELNQcbmY3ULB2vIo/9T8zIDw2 xaSzZUa/n8KeneXfOkn5LOqvFxUWNXRqgA== X-Google-Smtp-Source: AGRyM1ufkHIl8S47G3sNGF9pus9PSIlKu4BxECJ8lDjp11Fuc15u6ZmpdQFmnV1mW7IYwKjWA8zK6Q== X-Received: by 2002:a17:903:2281:b0:16a:6604:d1d8 with SMTP id b1-20020a170903228100b0016a6604d1d8mr1654916plh.78.1656390109639; Mon, 27 Jun 2022 21:21:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 12/45] target/arm: Mark gather prefetch as non-streaming Date: Tue, 28 Jun 2022 09:50:44 +0530 Message-Id: <20220628042117.368549-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656391520136100001 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. In this case, introduce PRF_ns (prefetch non-streaming) to handle the checks. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/sme-fa64.decode | 3 --- target/arm/sve.decode | 10 +++++----- target/arm/translate-sve.c | 11 +++++++++++ 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 711636ed30..bc41aa2e2a 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -58,10 +58,7 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Adva= nced SIMD cryptography e # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) =20 -FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather pref= etch (vector+imm) -FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather pref= etch (scalar+vector) FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load= (scalar+scalar) FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load= (scalar+imm) FAIL 1010 010- -10- ---- 000- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+scalar) FAIL 1010 010- -100 ---- 001- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+imm) -FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load= /prefetch diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a54feb2f61..908643d7d9 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1183,10 +1183,10 @@ LD1RO_zpri 1010010 .. 01 0.... 001 ... ..... .= .... \ @rpri_load_msz nreg=3D0 =20 # SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets) -PRF 1000010 00 -1 ----- 0-- --- ----- 0 ---- +PRF_ns 1000010 00 -1 ----- 0-- --- ----- 0 ---- =20 # SVE 32-bit gather prefetch (vector plus immediate) -PRF 1000010 -- 00 ----- 111 --- ----- 0 ---- +PRF_ns 1000010 -- 00 ----- 111 --- ----- 0 ---- =20 # SVE contiguous prefetch (scalar plus immediate) PRF 1000010 11 1- ----- 0-- --- ----- 0 ---- @@ -1223,13 +1223,13 @@ LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... .= .... \ @rpri_g_load esz=3D3 =20 # SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets) -PRF 1100010 00 11 ----- 1-- --- ----- 0 ---- +PRF_ns 1100010 00 11 ----- 1-- --- ----- 0 ---- =20 # SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets) -PRF 1100010 00 -1 ----- 0-- --- ----- 0 ---- +PRF_ns 1100010 00 -1 ----- 0-- --- ----- 0 ---- =20 # SVE 64-bit gather prefetch (vector plus immediate) -PRF 1100010 -- 00 ----- 111 --- ----- 0 ---- +PRF_ns 1100010 -- 00 ----- 111 --- ----- 0 ---- =20 ### SVE Memory Store Group =20 diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index a50b2f485b..9c58902b6e 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5971,6 +5971,17 @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr= *a) return true; } =20 +static bool trans_PRF_ns(DisasContext *s, arg_PRF_ns *a) +{ + if (!dc_isar_feature(aa64_sve, s)) { + return false; + } + /* Prefetch is a nop within QEMU. */ + s->is_nonstreaming =3D true; + (void)sve_access_check(s); + return true; +} + /* * Move Prefix * --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165639049727041.63745640810714; Mon, 27 Jun 2022 21:28:17 -0700 (PDT) Received: from localhost ([::1]:33288 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o62pk-0002Mq-8e for importer@patchew.org; Tue, 28 Jun 2022 00:28:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37168) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62jb-0001n2-Tb for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:55 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:33530) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jZ-0003i0-FK for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:55 -0400 Received: by mail-pf1-x42a.google.com with SMTP id n12so10953124pfq.0 for ; Mon, 27 Jun 2022 21:21:53 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.21.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:21:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ewoMQrcRLuqtJpk7AHvndmHZpifGgijfN++hOt6mk5U=; b=hmlhXEz7ZlaZDgoZZ/fyNZGKrln05fNAtB6JQFL79YkQduFR2UDup2d0b73YQsqYpk DsS0KxIGMHNY2v0V+hHPFK1m8HHnKt56tFYBnCVg33NLn/OKZag2YmWu+KDyrZccH9nw v0EsfCTmgLOlNdKgAZe3Zj2R069MSbvY0RIDLcmTJP1G0nH5V/iXI5OajD2Tm5b9L9mP yHm1Powygo2Sbhxi4hFEcUS3QE8RBSotykokwitYupV9WT9AEtB3spVvwtH/sZ/Eho9y 6JNzV239weLm6lunpA57z8u9IsuOZLtFX+gImnxlNKU+j+PwcfvmOGUwZ76ObBpd2EgJ v7eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ewoMQrcRLuqtJpk7AHvndmHZpifGgijfN++hOt6mk5U=; b=oa+Cb+u/CmCWgJVs22eRh2aaEYsfyJ/ZnvqDDupVTPoVtz4md5Zh8gO4Cg3EZywIIj ddgNGNL6LDBU1QlMcWRa3/8rmS7pMK4QrL3cVHaXheFk5nAl16jULLw4JNSfUD2ZpjqQ s5BuVx5OiL5GUuVFOqixcYOjW5oUrEokVpKhMjGzswBoRWoyDSTiat/pbTzpjszlKSe2 CWrWRb8eY6Q/6As8XeswR9Oo3U7/0t/vKUg5HsZkSVXPYEl7bg3Z3/rgpJfyWhesqrAR kizBS8hcDwitPu1/A9OuhIn8Fd5Foiv5Jhz4SCTJ8LUmopUmz1v5p1WjcxrUSOPWzQPn uxyg== X-Gm-Message-State: AJIora/55NIuz1rCAfnjcd2sHWn48B+v/WtVQupZBipUX+puIgEpMl+r HI8mGohYGlDpxjbXq0atWUBdc37TgSc6YQ== X-Google-Smtp-Source: AGRyM1vII4zuEeO76qDxUO2BCIH/dsPGc6nUB5HsuD9VPWeE4i4wJDm8RX3sJrgSWrlBZXw4/55sKQ== X-Received: by 2002:a63:b91c:0:b0:40c:9df7:400f with SMTP id z28-20020a63b91c000000b0040c9df7400fmr15295001pge.509.1656390112098; Mon, 27 Jun 2022 21:21:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 13/45] target/arm: Mark LDFF1 and LDNF1 as non-streaming Date: Tue, 28 Jun 2022 09:50:45 +0530 Message-Id: <20220628042117.368549-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656390499974100001 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/sme-fa64.decode | 2 -- target/arm/translate-sve.c | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index bc41aa2e2a..7a0b05cf2c 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -58,7 +58,5 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advan= ced SIMD cryptography e # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) =20 -FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load= (scalar+scalar) -FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load= (scalar+imm) FAIL 1010 010- -10- ---- 000- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+scalar) FAIL 1010 010- -100 ---- 001- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+imm) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 9c58902b6e..11874a8e77 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4805,6 +4805,7 @@ static bool trans_LDFF1_zprr(DisasContext *s, arg_rpr= r_load *a) if (!dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming =3D true; if (sve_access_check(s)) { TCGv_i64 addr =3D new_tmp_a64(s); tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); @@ -4906,6 +4907,7 @@ static bool trans_LDNF1_zpri(DisasContext *s, arg_rpr= i_load *a) if (!dc_isar_feature(aa64_sve, s)) { return false; } + s->is_nonstreaming =3D true; if (sve_access_check(s)) { int vsz =3D vec_full_reg_size(s); int elements =3D vsz >> dtype_esz[a->dtype]; --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656391747179204.78694465148806; Mon, 27 Jun 2022 21:49:07 -0700 (PDT) Received: from localhost ([::1]:49048 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o639t-00081D-FW for importer@patchew.org; Tue, 28 Jun 2022 00:49:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37186) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62jd-0001p1-8B for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:57 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:36505) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jb-0003iR-Fg for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:56 -0400 Received: by mail-pf1-x432.google.com with SMTP id x138so8214397pfc.3 for ; Mon, 27 Jun 2022 21:21:55 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.21.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:21:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1W2nx43eQtlEr+hd9bLz6u8JUHPhhCcdUN7L+wJEirI=; b=dEGfj5fB0JuJF7UN7ntfnt5aUuO1X6L33rdohsLBvHpI/FzvJgfUJncNjOW1KQhBjQ JzHuwmJwbmhoABao2LwMHoZTPU1iqILppYO+W7zqf7pXKwDQminB5n6Kvf7qY3obzsqR skdzq8tndK/wF6pSR4lxXd4qoFUFCoJZZ23X6LFr/dhKDpChZcE58UIBYZhHuzZEv8Za j5AFm6ow5gK6pkkkiDPxqnvFxeFuFaOMpFk9tIErpq4gwoRJjpARyZYPb5dV3HVlCT9x 8sBICPIodiZw4ynLSfKPDpC7xP54U9hri9QRVlsuVI0x4tlRfgsmY3lwwsdYr/aCa2dH lY+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1W2nx43eQtlEr+hd9bLz6u8JUHPhhCcdUN7L+wJEirI=; b=mww3Qayg80hlHqu1Ht+Oa9XA+HksbFkTpDqh7iiZPZEfNodSXMksr2t3Epwm17fxoP IHOoNAksGU8/+03u3tKgdXsfCgrQaHql2GFzvuD4hv0CZZId/IP4c85f1t81wY8I3QbA uXNfGfVuzAt99l5WBpLJXJacEEuG6Zn421W1v9NdeFuH77nWsOgEIc2fgoWELnjuAFc6 qboQkyiZvQuNtc9yz5zpkvL9h07xbHQQ52R5G49M0byvvilJdg1EGytFdXdYW/Z9MHUr g+EZyqHB9Fh96hKr28t0tdEJlpOkL+gsnP3RsfHGdHVmQvGvNXCKjgXGPDcVmpTgv0Qg ptlQ== X-Gm-Message-State: AJIora9fl8ErfaZ/9rxMSt/Me6WrnX6cyqxdQUoAAflOPy1Wy6ECYtlI PlbgtthPrs1JvKDMWmH90z3UExWAop1hgw== X-Google-Smtp-Source: AGRyM1s4VZmf83AETh+PTjMz3wzppsJNtOV83FNb6y+0n+zyN8kiO681mDHokgBFACO3xSsuK9SwvA== X-Received: by 2002:a63:2254:0:b0:40d:d291:7710 with SMTP id t20-20020a632254000000b0040dd2917710mr11713975pgm.269.1656390114229; Mon, 27 Jun 2022 21:21:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 14/45] target/arm: Mark LD1RO as non-streaming Date: Tue, 28 Jun 2022 09:50:46 +0530 Message-Id: <20220628042117.368549-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656391747752100001 Content-Type: text/plain; charset="utf-8" Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/sme-fa64.decode | 3 --- target/arm/translate-sve.c | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode index 7a0b05cf2c..33bbd13bcb 100644 --- a/target/arm/sme-fa64.decode +++ b/target/arm/sme-fa64.decode @@ -57,6 +57,3 @@ FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advan= ced SIMD cryptography e # --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register= (unscaled imm) # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) - -FAIL 1010 010- -10- ---- 000- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+scalar) -FAIL 1010 010- -100 ---- 001- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+imm) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 11874a8e77..e5e9e1e0ca 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5062,6 +5062,7 @@ static bool trans_LD1RO_zprr(DisasContext *s, arg_rpr= r_load *a) if (a->rm =3D=3D 31) { return false; } + s->is_nonstreaming =3D true; if (sve_access_check(s)) { TCGv_i64 addr =3D new_tmp_a64(s); tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); @@ -5076,6 +5077,7 @@ static bool trans_LD1RO_zpri(DisasContext *s, arg_rpr= i_load *a) if (!dc_isar_feature(aa64_sve_f64mm, s)) { return false; } + s->is_nonstreaming =3D true; if (sve_access_check(s)) { TCGv_i64 addr =3D new_tmp_a64(s); tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 32); --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656390734388679.016807595392; Mon, 27 Jun 2022 21:32:14 -0700 (PDT) Received: from localhost ([::1]:42054 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o62tY-0008P2-Tu for importer@patchew.org; Tue, 28 Jun 2022 00:32:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37222) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62jf-0001qy-7a for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:59 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:55177) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jd-0003gw-8r for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:21:58 -0400 Received: by mail-pj1-x1034.google.com with SMTP id cv13so11357044pjb.4 for ; Mon, 27 Jun 2022 21:21:56 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.21.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:21:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mlCVT85toSdHrRWejOQM9lSkLy9gos1+nWc5fKuZS4Q=; b=IjfE0EVFsi9fLS+mbQEHGlgDaeeVkQ1lmYOyth1YVao78E2w/Bi2fMPB2SiDXBjJpY pbkhn3dzCF/UziS6lsE5w8DA+xDrOOljAc/ctweGPPvam2elAuwh2yNSQ7uYQt3zm/kE no/PRIoF5Qfj+Ovm0r3LwndaK5DnOcdwDq5OJymRFzOYPLj8dCIw3PCgtz2kU31YkkKF VLMp5h0ULkEWNnXb2IG4uLhLmthQrrVCiqB+dFfKFwqIM7xTr/S/LWkZa7eOhJwSd5kG 5i+c05HNUGIb9cUNbqTNcTaxNkQ+UZYFKPvbD6TQQB3HPVlR8IGVhccAUX18gqpYxWSB 7Xag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mlCVT85toSdHrRWejOQM9lSkLy9gos1+nWc5fKuZS4Q=; b=ZvKNLXNGp3QlmchBjWOpiptuY3cyqe7JKVI19z9WJmbzgZPLYuNOFyTqD/oj1JGQVt ienLWrw3WvvrBjGdfqxDszhhg2cn18vqLriA64m+KGxo/+xE2DCV3rl+zmz8zG+YcnEe yGzg/+6LuulVo6UYBO48gdu+nfUHDQDhodW3+bSl+y+9U3a6rD/rKg+hB2I79+HVoqmy BtpltlEL2wx3tLrN2HcX49M42klztLlUEZ1fweGZVVgf56qV4JfJakdfyFkJKclIQGUQ sh8j4A1JHp0IvvXhUi42ZZooDOyHbHYMsTT0Chud0mOlCpDPzpua+Lmpph/ZuimXHhJS dZGw== X-Gm-Message-State: AJIora8bEtzjdj9E+RSjYua1oQIZvH0HNuuV/GgajjAYky8ACpB0/D8k r9KN8BcPScZH6CYgSRkxgWbqnCkYJIgKQg== X-Google-Smtp-Source: AGRyM1uti2E0io5KSRNjIqz3cAErB7hlqK+KbXG9SdlyDh7AIgQc+nDpaeQTzPslPzhI6ssm8bGGxQ== X-Received: by 2002:a17:90b:1d0c:b0:1ed:54c3:dcaf with SMTP id on12-20020a17090b1d0c00b001ed54c3dcafmr14088801pjb.217.1656390116436; Mon, 27 Jun 2022 21:21:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 15/45] target/arm: Add SME enablement checks Date: Tue, 28 Jun 2022 09:50:47 +0530 Message-Id: <20220628042117.368549-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656390736893100001 Content-Type: text/plain; charset="utf-8" These functions will be used to verify that the cpu is in the correct state for a given instruction. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.h | 21 +++++++++++++++++++++ target/arm/translate-a64.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 789b6e8e78..02fb95e019 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -29,6 +29,27 @@ void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v); bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, unsigned int imms, unsigned int immr); bool sve_access_check(DisasContext *s); +bool sme_enabled_check(DisasContext *s); +bool sme_enabled_check_with_svcr(DisasContext *s, unsigned); + +/* This function corresponds to CheckStreamingSVEEnabled. */ +static inline bool sme_sm_enabled_check(DisasContext *s) +{ + return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK); +} + +/* This function corresponds to CheckSMEAndZAEnabled. */ +static inline bool sme_za_enabled_check(DisasContext *s) +{ + return sme_enabled_check_with_svcr(s, R_SVCR_ZA_MASK); +} + +/* Note that this function corresponds to CheckStreamingSVEAndZAEnabled. */ +static inline bool sme_smza_enabled_check(DisasContext *s) +{ + return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK | R_SVCR_ZA_MASK); +} + TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, int log2_size); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7fab7f64f8..b16d81bf19 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1216,6 +1216,40 @@ static bool sme_access_check(DisasContext *s) return true; } =20 +/* This function corresponds to CheckSMEEnabled. */ +bool sme_enabled_check(DisasContext *s) +{ + /* + * Note that unlike sve_excp_el, we have not constrained sme_excp_el + * to be zero when fp_excp_el has priority. This is because we need + * sme_excp_el by itself for cpregs access checks. + */ + if (!s->fp_excp_el || s->sme_excp_el < s->fp_excp_el) { + s->fp_access_checked =3D true; + return sme_access_check(s); + } + return fp_access_check_only(s); +} + +/* Common subroutine for CheckSMEAnd*Enabled. */ +bool sme_enabled_check_with_svcr(DisasContext *s, unsigned req) +{ + if (!sme_enabled_check(s)) { + return false; + } + if (FIELD_EX64(req, SVCR, SM) && !s->pstate_sm) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_NotStreaming, false)); + return false; + } + if (FIELD_EX64(req, SVCR, ZA) && !s->pstate_za) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_InactiveZA, false)); + return false; + } + return true; +} + /* * This utility function is for doing register extension with an * optional shift. You will likely want to pass a temporary for the --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656391116663673.4049899439901; Mon, 27 Jun 2022 21:38:36 -0700 (PDT) Received: from localhost ([::1]:55988 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o62zj-0001JP-IN for importer@patchew.org; Tue, 28 Jun 2022 00:38:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37292) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62jl-0001wY-EP for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:05 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:46943) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jh-0003j6-A3 for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:04 -0400 Received: by mail-pj1-x102f.google.com with SMTP id h9-20020a17090a648900b001ecb8596e43so11396492pjj.5 for ; Mon, 27 Jun 2022 21:21:59 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.21.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:21:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R7wsrrOG/moJG3/AyHVAH2nF72RkKaiwNup9jQ+gf28=; b=QlpHo7GUMngIANSW8myXBzjun6bvnZiidvTVdH27+9FTJlI5MCPdDC33OPVp7s+QPq PR6XlQVs0Wh8+xFzw5OO/jlleFgUErS+i7vcXla3KJwBZtyVGXTMEy8cUbajYDaOGeqa Fq057mASlrJo7BC7GdwEEsNd9nw6MY45nMyvKt+zgluuTljcSjxOhH4PE5Ej9hHTtDVj muW1cN5jC9gCNqo3conDO396aLRngg9YjlSDr8ygPhGx0KOoKDe+DRY42Sj/C70X9WVN 873APSxl2kAhevV5nyo+Tl6Kg7QW8DMx4Fml3Zue0TA5fV3SZhaIr+q1GSfcPZ3+RTZW LXBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R7wsrrOG/moJG3/AyHVAH2nF72RkKaiwNup9jQ+gf28=; b=k1efdLteTnjm1U5Hhqgt1Eb1wkUncbw1E64ZBGrauCF+nivqZLQU1Iz2ZiCRQXj+MY Ci3gRRcXrwuzJTQA5+4OayS4U/TZ+SbQ14vcv6GVi2RnwDbR1UYQetTgbbQwTr+x1tXE 7ZgR7Luqq1eKYqDZFHJUTmoC3ulDvHvzyDA1AiWMxH2d7biYoHlob2eygjH3vebRuaFL +A/+3OnVmoAFeJIzpAkpHyCYx5SIdpKg98v5GandNjS+2m43zLg0CJ++d9J9PkbJp47l Jmn6hqurzkeSVYYLl45P96N44PYxzjhxyUlwdSb0AdHEliLCvIQqgs1IlDoQD5Iuvi8W CQew== X-Gm-Message-State: AJIora9jdWxCgQRLE2aCY69Ll3VjP11GZ930mdnJKb0fVEAZO1yY9+4v O/qc5iuIF7o/3/kc0tUivjevyjDdsvF32Q== X-Google-Smtp-Source: AGRyM1tQ9us4Hsln9Q1/d1XiWecvGI2w+Hv8qCXsHXhsU3D39cE/DqijJ2G/lMo87hQKRgPWI/dQIw== X-Received: by 2002:a17:90a:8914:b0:1dc:20c0:40f4 with SMTP id u20-20020a17090a891400b001dc20c040f4mr24775886pjn.11.1656390118986; Mon, 27 Jun 2022 21:21:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 16/45] target/arm: Handle SME in sve_access_check Date: Tue, 28 Jun 2022 09:50:48 +0530 Message-Id: <20220628042117.368549-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656391118459100001 Content-Type: text/plain; charset="utf-8" The pseudocode for CheckSVEEnabled gains a check for Streaming SVE mode, and for SME present but SVE absent. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b16d81bf19..b7b64f7358 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1183,21 +1183,31 @@ static bool fp_access_check(DisasContext *s) return true; } =20 -/* Check that SVE access is enabled. If it is, return true. +/* + * Check that SVE access is enabled. If it is, return true. * If not, emit code to generate an appropriate exception and return false. + * This function corresponds to CheckSVEEnabled(). */ bool sve_access_check(DisasContext *s) { - if (s->sve_excp_el) { - assert(!s->sve_access_checked); - s->sve_access_checked =3D true; - + if (s->pstate_sm || !dc_isar_feature(aa64_sve, s)) { + assert(dc_isar_feature(aa64_sme, s)); + if (!sme_sm_enabled_check(s)) { + goto fail_exit; + } + } else if (s->sve_excp_el) { gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn_sve_access_trap(), s->sve_excp_el); - return false; + goto fail_exit; } s->sve_access_checked =3D true; return fp_access_check(s); + + fail_exit: + /* Assert that we only raise one exception per instruction. */ + assert(!s->sve_access_checked); + s->sve_access_checked =3D true; + return false; } =20 /* --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656391982644772.8463982828986; Mon, 27 Jun 2022 21:53:02 -0700 (PDT) Received: from localhost ([::1]:59698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o63Dh-0006yJ-JV for importer@patchew.org; Tue, 28 Jun 2022 00:53:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37312) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62jo-0001yv-Ve for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:09 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:42509) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jj-0003jF-ET for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:05 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d17so10864851pfq.9 for ; Mon, 27 Jun 2022 21:22:02 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.21.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:22:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pNURgSuocVgs5B8bRGEZVrFEdfi62ntOnXeVG2Z7Cdk=; b=Tc357iJ/cSiAv52LDxS0geb4wr/RZzdp9+4I08ZdlmoofyjUaVhLbL0o5BrbDZv9ck otRBUmzCGu93vQk4a1QVTWub/O85vMSKbpoMmk4MwBZ+LGKMHqgY5AVZVNia73uGH6df 0kvaFu+k4mx+kvapou72Z/zq6sqizGjC/E3FAsbkXwjLfoQPhvwVGb2zSjh3UX8wqwGo pxs1YPxy4+y/LDTWyMN/GoJuBAwNM3fsL504sjP2jrnRT/HCYgWYMYNs5i21LMMac/Oy s+8GJW5bbsuVcPXonMvSxOGGe1Q27DwBXepzcl1/N4VMGH/m0L7b5U57OIfU6AuonfVU jfzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pNURgSuocVgs5B8bRGEZVrFEdfi62ntOnXeVG2Z7Cdk=; b=6kvbOCuG+8/5zs6jgHO/wVskK0SBZ5/uevugzwZkE9CFWvYoUCciDu+EtarL7ox3s3 dysOs9F2Q/2a3CVksGtz8NJVN9EaQXRgZAcGMBqs80wizu+1oPiO4OQG4J5jUztO38RO w431yVw6nZrjd3/6KvcVU+MHmlcIoJGbrrJIedzwJV+opoVUbljOYJlBk7k/4GC9E1sO azIy59MmrIkC/VB5nCozC27WGCEJIq4ayxkAXJZUQUrbmVwJ7cAYx2ohHZAbx/3xyYtK ZSs8GYhxOJ4MprrqJIP+LRln2u/syO499hu2E53UVL71dCKA1CUIGjrSDHqJVZ7+sqxf Dc+A== X-Gm-Message-State: AJIora9T2IiCfF/1ruzebXG+GYMw1eNjTjGjcxsiprLiZKu52tLgwoIW G/9idtHdeheDMwbN1/HSmDMasuwRsI08sQ== X-Google-Smtp-Source: AGRyM1vJgCjh/O6VB5IujIoFTFPa9e5UHrB4btMTUa/oE8g5pGCRKMHX9iY47l97I/m0o931rX+t7w== X-Received: by 2002:a05:6a00:1a15:b0:527:d02b:29c6 with SMTP id g21-20020a056a001a1500b00527d02b29c6mr6067pfv.23.1656390121959; Mon, 27 Jun 2022 21:22:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v4 17/45] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL Date: Tue, 28 Jun 2022 09:50:49 +0530 Message-Id: <20220628042117.368549-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656391984370100001 Content-Type: text/plain; charset="utf-8" These SME instructions are nominally within the SVE decode space, so we add them to sve.decode and translate-sve.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v4: Add streaming_{vec,pred}_reg_size. --- target/arm/translate-a64.h | 12 ++++++++++++ target/arm/sve.decode | 5 ++++- target/arm/translate-sve.c | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 54 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 02fb95e019..099d3d11d6 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -128,6 +128,12 @@ static inline int vec_full_reg_size(DisasContext *s) return s->vl; } =20 +/* Return the byte size of the vector register, SVL / 8. */ +static inline int streaming_vec_reg_size(DisasContext *s) +{ + return s->svl; +} + /* * Return the offset info CPUARMState of the predicate vector register Pn. * Note for this purpose, FFR is P16. @@ -143,6 +149,12 @@ static inline int pred_full_reg_size(DisasContext *s) return s->vl >> 3; } =20 +/* Return the byte size of the predicate register, SVL / 64. */ +static inline int streaming_pred_reg_size(DisasContext *s) +{ + return s->svl >> 3; +} + /* * Round up the size of a register to a size allowed by * the tcg vector infrastructure. Any operation which uses this diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 908643d7d9..95af08c139 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -449,14 +449,17 @@ INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 r= d:5 # SVE index generation (register start, register increment) INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm =20 -### SVE Stack Allocation Group +### SVE / Streaming SVE Stack Allocation Group =20 # SVE stack frame adjustment ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 +ADDSVL 00000100 001 ..... 01011 ...... ..... @rd_rn_i6 ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 +ADDSPL 00000100 011 ..... 01011 ...... ..... @rd_rn_i6 =20 # SVE stack frame size RDVL 00000100 101 11111 01010 imm:s6 rd:5 +RDSVL 00000100 101 11111 01011 imm:s6 rd:5 =20 ### SVE Bitwise Shift - Unpredicated Group =20 diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index e5e9e1e0ca..9e304f78bc 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1286,6 +1286,19 @@ static bool trans_ADDVL(DisasContext *s, arg_ADDVL *= a) return true; } =20 +static bool trans_ADDSVL(DisasContext *s, arg_ADDSVL *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_enabled_check(s)) { + TCGv_i64 rd =3D cpu_reg_sp(s, a->rd); + TCGv_i64 rn =3D cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(rd, rn, a->imm * streaming_vec_reg_size(s)); + } + return true; +} + static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) { if (!dc_isar_feature(aa64_sve, s)) { @@ -1299,6 +1312,19 @@ static bool trans_ADDPL(DisasContext *s, arg_ADDPL *= a) return true; } =20 +static bool trans_ADDSPL(DisasContext *s, arg_ADDSPL *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_enabled_check(s)) { + TCGv_i64 rd =3D cpu_reg_sp(s, a->rd); + TCGv_i64 rn =3D cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(rd, rn, a->imm * streaming_pred_reg_size(s)); + } + return true; +} + static bool trans_RDVL(DisasContext *s, arg_RDVL *a) { if (!dc_isar_feature(aa64_sve, s)) { @@ -1311,6 +1337,18 @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a) return true; } =20 +static bool trans_RDSVL(DisasContext *s, arg_RDSVL *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_enabled_check(s)) { + TCGv_i64 reg =3D cpu_reg(s, a->rd); + tcg_gen_movi_i64(reg, a->imm * streaming_vec_reg_size(s)); + } + return true; +} + /* *** SVE Compute Vector Address Group */ --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656392808147189.00909478383608; Mon, 27 Jun 2022 22:06:48 -0700 (PDT) Received: from localhost ([::1]:59062 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o63R0-00010D-LL for importer@patchew.org; Tue, 28 Jun 2022 01:06:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37512) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62k1-00028F-Ka for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:21 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:46940) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jm-0003jj-UD for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:21 -0400 Received: by mail-pj1-x102b.google.com with SMTP id h9-20020a17090a648900b001ecb8596e43so11396656pjj.5 for ; Mon, 27 Jun 2022 21:22:05 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656392809013100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v4: Fix ZA[] comment in helper_sme_zero. --- target/arm/helper-sme.h | 2 ++ target/arm/sme.decode | 4 ++++ target/arm/sme_helper.c | 25 +++++++++++++++++++++++++ target/arm/translate-sme.c | 13 +++++++++++++ 4 files changed, 44 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 3bd48c235f..c4ee1f09e4 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -19,3 +19,5 @@ =20 DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32) + +DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index c25c031a71..6e4483fdce 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -18,3 +18,7 @@ # # This file is processed by scripts/decodetree.py # + +### SME Misc + +ZERO 11000000 00 001 00000000000 imm:8 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index b215725594..eef2df73e1 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -59,3 +59,28 @@ void helper_set_pstate_za(CPUARMState *env, uint32_t i) memset(env->zarray, 0, sizeof(env->zarray)); } } + +void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl) +{ + uint32_t i; + + /* + * Special case clearing the entire ZA space. + * This falls into the CONSTRAINED UNPREDICTABLE zeroing of any + * parts of the ZA storage outside of SVL. + */ + if (imm =3D=3D 0xff) { + memset(env->zarray, 0, sizeof(env->zarray)); + return; + } + + /* + * Recall that ZAnH.D[m] is spread across ZA[n+8*m], + * so each row is discontiguous within ZA[]. + */ + for (i =3D 0; i < svl; i++) { + if (imm & (1 << (i % 8))) { + memset(&env->zarray[i], 0, svl); + } + } +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 786c93fb2d..971504559b 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -33,3 +33,16 @@ */ =20 #include "decode-sme.c.inc" + + +static bool trans_ZERO(DisasContext *s, arg_ZERO *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_za_enabled_check(s)) { + gen_helper_sme_zero(cpu_env, tcg_constant_i32(a->imm), + tcg_constant_i32(streaming_vec_reg_size(s))); + } + return true; +} --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16563914581723.378883719325131; Mon, 27 Jun 2022 21:44:18 -0700 (PDT) Received: from localhost ([::1]:38358 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o635E-0000TY-75 for importer@patchew.org; Tue, 28 Jun 2022 00:44:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37382) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62jt-000244-Ad for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:14 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:33530) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jo-0003k6-LQ for qemu-devel@nongnu.org; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.22.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:22:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OCpZTwYRKjmhDta+uw08I335v7NtcU6c85SQuAKXnpU=; b=MvY/AxW12VTwmXJXh1aGEW/53xbcm5M5+WJ9F2yi+BUmChy/xEWB77+h7YPtZCH7cN 3AxKrIjhFFN0S6O0PAUIgWlcSE/bjrJkZYM2A62HPg196wEpJ6c6UqpO33vZ75UlNLfF jFgOsoRDUbW9YqS3sY+5HSEp3zr/dXH5wdJ3p5pbaRB0qRRQvEzM/cixRfoWuP5ydzgH dwCiKXPn34eMKaHGiKdPMjTwC9EmfQKJLG4Ca0X6xC9GxN7ehmrUbxUzhoWQsqDDyNGq zDGaAIUn2O0Ksk3DKUsLiG/pz/ZFp79NOvSkfZujJXaIvFod7CinKbIXCack+T4/aecJ m7Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OCpZTwYRKjmhDta+uw08I335v7NtcU6c85SQuAKXnpU=; b=6SYemqT6Ml1vDzEIZlAg005nQFmDWNPRqFDmVuYbqBFqswQOzYdpIISu+A0yimiPBk dyTlhenn8Jd8NVVofISv68kIazPbtl2dFE6bhphtWWBN6/v/BIxxpWUCD4rQZvDdykEY f40SjeS4SdRyloFLy8FYKBH0hXDqKKad1L3hlLl9XrC2/RdX+GShxnXeNriduwdcabrg EXkiJkksfSOOpJJF5TLoXaU9rOiseN+Y870HeONsm4AfUAulVryRWFUuJ4vxDbqhuVI3 FdEPeV/EFVkrSNzNDbsOreLreZ9RXGOODjRpVvbf/l86ycRiCNh/87b/BvNilTgy3CTu xwzw== X-Gm-Message-State: AJIora8LqqhyxD2EZMcJnljV7B1NMo9OCKePgUREVdh30KECQhnKM1H+ MgFkKePycsvcMfwB+d8Ao/cdjeqnVbZvNA== X-Google-Smtp-Source: AGRyM1ug0kK7/IOQa4lx8+7fXEjKc2Z5dr4TuWIkNnkYv3emrLmmbwJ3M1x6d5zIdRRGFaAIrGM4uQ== X-Received: by 2002:a63:b54c:0:b0:40c:7b84:4f7f with SMTP id u12-20020a63b54c000000b0040c7b844f7fmr15407834pgo.586.1656390126978; Mon, 27 Jun 2022 21:22:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 19/45] target/arm: Implement SME MOVA Date: Tue, 28 Jun 2022 09:50:51 +0530 Message-Id: <20220628042117.368549-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656391459852100001 Content-Type: text/plain; charset="utf-8" We can reuse the SVE functions for implementing moves to/from horizontal tile slices, but we need new ones for moves to/from vertical tile slices. Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 12 ++++ target/arm/helper-sve.h | 2 + target/arm/translate-a64.h | 8 +++ target/arm/translate.h | 5 ++ target/arm/sme.decode | 15 +++++ target/arm/sme_helper.c | 112 +++++++++++++++++++++++++++++++- target/arm/sve_helper.c | 12 ++++ target/arm/translate-sme.c | 130 +++++++++++++++++++++++++++++++++++++ 8 files changed, 295 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index c4ee1f09e4..154bc73d2e 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -21,3 +21,15 @@ DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void,= env, i32) DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32) =20 DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32) + +/* Move to/from vertical array slices, i.e. columns, so 'c'. */ +DEF_HELPER_FLAGS_4(sme_mova_cz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sme_mova_zc_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sme_mova_cz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sme_mova_zc_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sme_mova_cz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sme_mova_zc_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sme_mova_cz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sme_mova_zc_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sme_mova_cz_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) +DEF_HELPER_FLAGS_4(sme_mova_zc_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index dc629f851a..ab0333400f 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -325,6 +325,8 @@ DEF_HELPER_FLAGS_5(sve_sel_zpzz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve_sel_zpzz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_sel_zpzz_q, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_5(sve2_addp_zpzz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 099d3d11d6..2a7fe6e9e7 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -178,6 +178,14 @@ static inline int pred_gvec_reg_size(DisasContext *s) return size_for_gvec(pred_full_reg_size(s)); } =20 +/* Return a newly allocated pointer to the predicate register. */ +static inline TCGv_ptr pred_full_reg_ptr(DisasContext *s, int regno) +{ + TCGv_ptr ret =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ret, cpu_env, pred_full_reg_offset(s, regno)); + return ret; +} + bool disas_sve(DisasContext *, uint32_t); bool disas_sme(DisasContext *, uint32_t); =20 diff --git a/target/arm/translate.h b/target/arm/translate.h index e2e619dab2..af5d4a7086 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -156,6 +156,11 @@ static inline int plus_2(DisasContext *s, int x) return x + 2; } =20 +static inline int plus_12(DisasContext *s, int x) +{ + return x + 12; +} + static inline int times_2(DisasContext *s, int x) { return x * 2; diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 6e4483fdce..241b4895b7 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -22,3 +22,18 @@ ### SME Misc =20 ZERO 11000000 00 001 00000000000 imm:8 + +### SME Move into/from Array + +%mova_rs 13:2 !function=3Dplus_12 +&mova esz rs pg zr za_imm v:bool to_vec:bool + +MOVA 11000000 esz:2 00000 0 v:1 .. pg:3 zr:5 0 za_imm:4 \ + &mova to_vec=3D0 rs=3D%mova_rs +MOVA 11000000 11 00000 1 v:1 .. pg:3 zr:5 0 za_imm:4 \ + &mova to_vec=3D0 rs=3D%mova_rs esz=3D4 + +MOVA 11000000 esz:2 00001 0 v:1 .. pg:3 0 za_imm:4 zr:5 \ + &mova to_vec=3D1 rs=3D%mova_rs +MOVA 11000000 11 00001 1 v:1 .. pg:3 0 za_imm:4 zr:5 \ + &mova to_vec=3D1 rs=3D%mova_rs esz=3D4 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index eef2df73e1..95159862de 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -19,8 +19,10 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "internals.h" +#include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" +#include "qemu/int128.h" +#include "vec_internal.h" =20 /* ResetSVEState */ void arm_reset_sve_state(CPUARMState *env) @@ -84,3 +86,111 @@ void helper_sme_zero(CPUARMState *env, uint32_t imm, ui= nt32_t svl) } } } + +/* + * Move Zreg vector to ZArray column. + */ +#define DO_MOVA_C(NAME, TYPE, H) \ +void HELPER(NAME)(void *za, void *vn, void *vg, uint32_t desc) \ +{ \ + int i, oprsz =3D simd_oprsz(desc); \ + for (i =3D 0; i < oprsz; ) { \ + uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); \ + do { \ + if (pg & 1) { \ + *(TYPE *)za =3D *(TYPE *)(vn + H(i)); \ + } \ + za +=3D sizeof(ARMVectorReg) * sizeof(TYPE); \ + i +=3D sizeof(TYPE); \ + pg >>=3D sizeof(TYPE); \ + } while (i & 15); \ + } \ +} + +DO_MOVA_C(sme_mova_cz_b, uint8_t, H1) +DO_MOVA_C(sme_mova_cz_h, uint16_t, H2) +DO_MOVA_C(sme_mova_cz_s, uint32_t, H4) + +void HELPER(sme_mova_cz_d)(void *za, void *vn, void *vg, uint32_t desc) +{ + int i, oprsz =3D simd_oprsz(desc) / 8; + uint8_t *pg =3D vg; + uint64_t *n =3D vn; + uint64_t *a =3D za; + + for (i =3D 0; i < oprsz; i++) { + if (pg[H1_2(i)] & 1) { + a[i * sizeof(ARMVectorReg)] =3D n[i]; + } + } +} + +void HELPER(sme_mova_cz_q)(void *za, void *vn, void *vg, uint32_t desc) +{ + int i, oprsz =3D simd_oprsz(desc) / 16; + uint16_t *pg =3D vg; + Int128 *n =3D vn; + Int128 *a =3D za; + + for (i =3D 0; i < oprsz; i++) { + if (pg[H2(i)] & 1) { + a[i * sizeof(ARMVectorReg)] =3D n[i]; + } + } +} + +#undef DO_MOVA_C + +/* + * Move ZArray column to Zreg vector. + */ +#define DO_MOVA_Z(NAME, TYPE, H) \ +void HELPER(NAME)(void *vd, void *za, void *vg, uint32_t desc) \ +{ \ + int i, oprsz =3D simd_oprsz(desc); \ + for (i =3D 0; i < oprsz; ) { \ + uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); \ + do { \ + if (pg & 1) { \ + *(TYPE *)(vd + H(i)) =3D *(TYPE *)za; \ + } \ + za +=3D sizeof(ARMVectorReg) * sizeof(TYPE); \ + i +=3D sizeof(TYPE); \ + pg >>=3D sizeof(TYPE); \ + } while (i & 15); \ + } \ +} + +DO_MOVA_Z(sme_mova_zc_b, uint8_t, H1) +DO_MOVA_Z(sme_mova_zc_h, uint16_t, H2) +DO_MOVA_Z(sme_mova_zc_s, uint32_t, H4) + +void HELPER(sme_mova_zc_d)(void *vd, void *za, void *vg, uint32_t desc) +{ + int i, oprsz =3D simd_oprsz(desc) / 8; + uint8_t *pg =3D vg; + uint64_t *d =3D vd; + uint64_t *a =3D za; + + for (i =3D 0; i < oprsz; i++) { + if (pg[H1_2(i)] & 1) { + d[i] =3D a[i * sizeof(ARMVectorReg)]; + } + } +} + +void HELPER(sme_mova_zc_q)(void *vd, void *za, void *vg, uint32_t desc) +{ + int i, oprsz =3D simd_oprsz(desc) / 16; + uint16_t *pg =3D vg; + Int128 *d =3D vd; + Int128 *a =3D za; + + for (i =3D 0; i < oprsz; i++, za +=3D sizeof(ARMVectorReg)) { + if (pg[H2(i)] & 1) { + d[i] =3D a[i * sizeof(ARMVectorReg)]; + } + } +} + +#undef DO_MOVA_Z diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 1654c0bbf9..9a26f253e0 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -3565,6 +3565,18 @@ void HELPER(sve_sel_zpzz_d)(void *vd, void *vn, void= *vm, } } =20 +void HELPER(sve_sel_zpzz_q)(void *vd, void *vn, void *vm, + void *vg, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 16; + Int128 *d =3D vd, *n =3D vn, *m =3D vm; + uint16_t *pg =3D vg; + + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D (pg[H2(i)] & 1 ? n : m)[i]; + } +} + /* Two operand comparison controlled by a predicate. * ??? It is very tempting to want to be able to expand this inline * with x86 instructions, e.g. diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 971504559b..8e6881086b 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -35,6 +35,77 @@ #include "decode-sme.c.inc" =20 =20 +static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs, + int tile_index, bool vertical) +{ + int tile =3D tile_index >> (4 - esz); + int index =3D esz =3D=3D MO_128 ? 0 : extract32(tile_index, 0, 4 - esz= ); + int pos, len, offset; + TCGv_i32 t_index; + TCGv_ptr addr; + + /* Resolve tile.size[index] to an untyped ZA slice index. */ + t_index =3D tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t_index, cpu_reg(s, rs)); + tcg_gen_addi_i32(t_index, t_index, index); + + len =3D ctz32(streaming_vec_reg_size(s)) - esz; + + if (vertical) { + /* + * Compute the offset of the index within the tile: + * (index % (svl / size)) * size + * =3D (index % (svl >> esz)) << esz + * Perform the power-of-two modulo via extraction of the low @len = bits. + * Perform the multiply by shifting left by @pos bits. + * These two operations are performed simultaneously via deposit. + */ + pos =3D esz; + tcg_gen_deposit_z_i32(t_index, t_index, pos, len); + + /* The tile slice offset within env->zarray is the column offset. = */ + offset =3D tile; + + /* Include the offset of zarray to make this relative to env. */ + offset +=3D offsetof(CPUARMState, zarray); + tcg_gen_addi_i32(t_index, t_index, offset); + + /* + * For big-endian, adjust the column slice offset within + * the uint64_t host words that make up env->zarray. + * This must wait until index and offset are combined. + */ + if (HOST_BIG_ENDIAN && esz < MO_64) { + tcg_gen_xori_i32(t_index, t_index, 8 - (1 << esz)); + } + } else { + /* + * Compute the offset of the index within the tile: + * (index % (svl / size)) * (size * sizeof(row)) + * =3D (index % (svl >> esz)) << (esz + log2(sizeof(row))) + */ + pos =3D esz + ctz32(sizeof(ARMVectorReg)); + tcg_gen_deposit_z_i32(t_index, t_index, pos, len); + + /* The tile slice offset within env->zarray is the row offset. */ + offset =3D tile * sizeof(ARMVectorReg); + + /* Include the offset of zarray to make this relative to env. */ + offset +=3D offsetof(CPUARMState, zarray); + tcg_gen_addi_i32(t_index, t_index, offset); + + /* Row slices need no endian adjustment. */ + } + + /* Add the offset to env to produce the final pointer. */ + addr =3D tcg_temp_new_ptr(); + tcg_gen_ext_i32_ptr(addr, t_index); + tcg_temp_free_i32(t_index); + tcg_gen_add_ptr(addr, addr, cpu_env); + + return addr; +} + static bool trans_ZERO(DisasContext *s, arg_ZERO *a) { if (!dc_isar_feature(aa64_sme, s)) { @@ -46,3 +117,62 @@ static bool trans_ZERO(DisasContext *s, arg_ZERO *a) } return true; } + +static bool trans_MOVA(DisasContext *s, arg_MOVA *a) +{ + static gen_helper_gvec_4 * const h_fns[5] =3D { + gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h, + gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d, + gen_helper_sve_sel_zpzz_q + }; + static gen_helper_gvec_3 * const cz_fns[5] =3D { + gen_helper_sme_mova_cz_b, gen_helper_sme_mova_cz_h, + gen_helper_sme_mova_cz_s, gen_helper_sme_mova_cz_d, + gen_helper_sme_mova_cz_q, + }; + static gen_helper_gvec_3 * const zc_fns[5] =3D { + gen_helper_sme_mova_zc_b, gen_helper_sme_mova_zc_h, + gen_helper_sme_mova_zc_s, gen_helper_sme_mova_zc_d, + gen_helper_sme_mova_zc_q, + }; + + TCGv_ptr t_za, t_zr, t_pg; + TCGv_i32 t_desc; + int svl; + + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (!sme_smza_enabled_check(s)) { + return true; + } + + t_za =3D get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v); + t_zr =3D vec_full_reg_ptr(s, a->zr); + t_pg =3D pred_full_reg_ptr(s, a->pg); + + svl =3D streaming_vec_reg_size(s); + t_desc =3D tcg_constant_i32(simd_desc(svl, svl, 0)); + + if (a->v) { + /* Vertical slice -- use sme mova helpers. */ + if (a->to_vec) { + zc_fns[a->esz](t_zr, t_za, t_pg, t_desc); + } else { + cz_fns[a->esz](t_za, t_zr, t_pg, t_desc); + } + } else { + /* Horizontal slice -- reuse sve sel helpers. */ + if (a->to_vec) { + h_fns[a->esz](t_zr, t_za, t_zr, t_pg, t_desc); + } else { + h_fns[a->esz](t_za, t_zr, t_za, t_pg, t_desc); + } + } + + tcg_temp_free_ptr(t_za); + tcg_temp_free_ptr(t_zr); + tcg_temp_free_ptr(t_pg); + + return true; +} --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.22.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:22:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qKNA45Dd5fgO5fqiFv5yfge+fKjEpS18yDqVWxC/Oc8=; b=OGDhZvV8rJh3cJU2jds2XIi17UXbWjiID+AlSpJ8Q9ifXwIoyvCPEiWbb9D19DTg/O jpDOACVaFG2ZYUdW4wgBePDUWXAYAwxtvMDQL0ISczlGerKK+744rr5hipQcPhVeURbR emokoqt2ntDvqG5MC7qagap/whFj7iHHO3W0I2Rq5NrOYsGAtsll4mpGYI/epZkA9Em8 VaZrEWx84/reDjv/z/QlM4/h4A1TEbeSDxA3dBWuo5qqWdTkuQyyAL2GxLBdnvKVJa3Z E1HpciWTaTVjWr79CwkMNuvNiALv5eRmTI+zoTdmo4SoKDvI9PIQ5jw2xlDRGoibbTHh chPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qKNA45Dd5fgO5fqiFv5yfge+fKjEpS18yDqVWxC/Oc8=; b=byN7a8ynh8ShsGafKaP/tAc8NC71GQp8HF+y1GJKtgcIFhj6TeIzyoh/BUEVDIfNZK 90CKG2C0MR5WgeaBPwAQVe4xvNPnwMBJpedFsMhecR6dWhmKGQbLdWb+xk+Ccj9MNDkA /PBU275gIROPAewVwo6URSbKmwpN8no8VxnLELrvMJwhp/JUcPQ4cjwClgtoJXd/z1Tx 2lw5dQeDHWEi6t2vT0gc4kf3v4uTWKghQIR6ljwy+wjGNy6gWyFo2X1KK9iE653zgdmD L6G0a5MCghKIRHNi58Jy1nhl80IETj3pocwBAxeraSEH3M0sIVAI3OD91/1QXhIEu8qW CQrQ== X-Gm-Message-State: AJIora8uwmknRh3JU0e2hlVnJGxAsqKdGOMs5nQeVQ/dYkhCllYncpVa r9ovzHEP/kv4fGWETsw2hhgPbWn+2Ez+cg== X-Google-Smtp-Source: AGRyM1u0nO+ZqPM056CoFVNRKitC6aprJbKNLRjqxClypoCc8PdpbMtCPGKDZfcggXxAPHDVdga4PQ== X-Received: by 2002:a17:902:ebcb:b0:168:e3ba:4b5a with SMTP id p11-20020a170902ebcb00b00168e3ba4b5amr2991069plg.11.1656390129642; Mon, 27 Jun 2022 21:22:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 20/45] target/arm: Implement SME LD1, ST1 Date: Tue, 28 Jun 2022 09:50:52 +0530 Message-Id: <20220628042117.368549-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656392197379100001 Content-Type: text/plain; charset="utf-8" We cannot reuse the SVE functions for LD[1-4] and ST[1-4], because those functions accept only a Zreg register number. For SME, we want to pass a pointer into ZA storage. Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 82 +++++ target/arm/sme.decode | 9 + target/arm/sme_helper.c | 614 +++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 70 +++++ 4 files changed, 775 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 154bc73d2e..95f6e88bdd 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -33,3 +33,85 @@ DEF_HELPER_FLAGS_4(sme_mova_cz_d, TCG_CALL_NO_RWG, void,= ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sme_mova_zc_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) DEF_HELPER_FLAGS_4(sme_mova_cz_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) DEF_HELPER_FLAGS_4(sme_mova_zc_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i3= 2) + +DEF_HELPER_FLAGS_5(sme_ld1b_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_5(sme_ld1b_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_5(sme_ld1b_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl= , i32) +DEF_HELPER_FLAGS_5(sme_ld1b_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl= , i32) + +DEF_HELPER_FLAGS_5(sme_ld1h_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1h_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1h_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_ld1s_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1s_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1s_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_ld1d_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1d_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1d_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_ld1q_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1q_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1b_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_5(sme_st1b_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_5(sme_st1b_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl= , i32) +DEF_HELPER_FLAGS_5(sme_st1b_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl= , i32) + +DEF_HELPER_FLAGS_5(sme_st1h_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1h_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1h_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1s_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1s_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1s_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1d_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1d_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1d_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1q_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1q_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 241b4895b7..900e3f2a07 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -37,3 +37,12 @@ MOVA 11000000 esz:2 00001 0 v:1 .. pg:3 0 za_= imm:4 zr:5 \ &mova to_vec=3D1 rs=3D%mova_rs MOVA 11000000 11 00001 1 v:1 .. pg:3 0 za_imm:4 zr:5 \ &mova to_vec=3D1 rs=3D%mova_rs esz=3D4 + +### SME Memory + +&ldst esz rs pg rn rm za_imm v:bool st:bool + +LDST1 1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ + &ldst rs=3D%mova_rs +LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ + &ldst esz=3D4 rs=3D%mova_rs diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 95159862de..4ff4e22c2c 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -19,10 +19,14 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "internals.h" #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" +#include "exec/cpu_ldst.h" +#include "exec/exec-all.h" #include "qemu/int128.h" #include "vec_internal.h" +#include "sve_ldst_internal.h" =20 /* ResetSVEState */ void arm_reset_sve_state(CPUARMState *env) @@ -194,3 +198,613 @@ void HELPER(sme_mova_zc_q)(void *vd, void *za, void *= vg, uint32_t desc) } =20 #undef DO_MOVA_Z + +/* + * Clear elements in a tile slice comprising len bytes. + */ + +typedef void ClearFn(void *ptr, size_t off, size_t len); + +static void clear_horizontal(void *ptr, size_t off, size_t len) +{ + memset(ptr + off, 0, len); +} + +static void clear_vertical_b(void *vptr, size_t off, size_t len) +{ + uint8_t *ptr =3D vptr; + size_t i; + + for (i =3D 0; i < len; ++i) { + ptr[(i + off) * sizeof(ARMVectorReg)] =3D 0; + } +} + +static void clear_vertical_h(void *vptr, size_t off, size_t len) +{ + uint16_t *ptr =3D vptr; + size_t i; + + for (i =3D 0; i < len / 2; ++i) { + ptr[(i + off) * sizeof(ARMVectorReg)] =3D 0; + } +} + +static void clear_vertical_s(void *vptr, size_t off, size_t len) +{ + uint32_t *ptr =3D vptr; + size_t i; + + for (i =3D 0; i < len / 4; ++i) { + ptr[(i + off) * sizeof(ARMVectorReg)] =3D 0; + } +} + +static void clear_vertical_d(void *vptr, size_t off, size_t len) +{ + uint64_t *ptr =3D vptr; + size_t i; + + for (i =3D 0; i < len / 8; ++i) { + ptr[(i + off) * sizeof(ARMVectorReg)] =3D 0; + } +} + +static void clear_vertical_q(void *vptr, size_t off, size_t len) +{ + Int128 *ptr =3D vptr, zero =3D int128_zero(); + size_t i; + + for (i =3D 0; i < len / 16; ++i) { + ptr[(i + off) * sizeof(ARMVectorReg)] =3D zero; + } +} + +/* + * Copy elements from an array into a tile slice comprising len bytes. + */ + +typedef void CopyFn(void *dst, const void *src, size_t len); + +static void copy_horizontal(void *dst, const void *src, size_t len) +{ + memcpy(dst, src, len); +} + +static void copy_vertical_b(void *vdst, const void *vsrc, size_t len) +{ + const uint8_t *src =3D vsrc; + uint8_t *dst =3D vdst; + size_t i; + + for (i =3D 0; i < len; ++i) { + dst[i * sizeof(ARMVectorReg)] =3D src[i]; + } +} + +static void copy_vertical_h(void *vdst, const void *vsrc, size_t len) +{ + const uint16_t *src =3D vsrc; + uint16_t *dst =3D vdst; + size_t i; + + for (i =3D 0; i < len / 2; ++i) { + dst[i * sizeof(ARMVectorReg)] =3D src[i]; + } +} + +static void copy_vertical_s(void *vdst, const void *vsrc, size_t len) +{ + const uint32_t *src =3D vsrc; + uint32_t *dst =3D vdst; + size_t i; + + for (i =3D 0; i < len / 4; ++i) { + dst[i * sizeof(ARMVectorReg)] =3D src[i]; + } +} + +static void copy_vertical_d(void *vdst, const void *vsrc, size_t len) +{ + const uint64_t *src =3D vsrc; + uint64_t *dst =3D vdst; + size_t i; + + for (i =3D 0; i < len / 8; ++i) { + dst[i * sizeof(ARMVectorReg)] =3D src[i]; + } +} + +static void copy_vertical_q(void *vdst, const void *vsrc, size_t len) +{ + const Int128 *src =3D vsrc; + Int128 *dst =3D vdst; + size_t i; + + for (i =3D 0; i < len / 16; ++i) { + dst[i * sizeof(ARMVectorReg)] =3D src[i]; + } +} + +/* + * Host and TLB primitives for vertical tile slice addressing. + */ + +#define DO_LD(NAME, TYPE, HOST, TLB) = \ +static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host)= \ +{ = \ + TYPE val =3D HOST(host); = \ + *(TYPE *)(za + off * sizeof(ARMVectorReg)) =3D val; = \ +} = \ +static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za, = \ + intptr_t off, target_ulong addr, uintptr_t ra) = \ +{ = \ + TYPE val =3D TLB(env, useronly_clean_ptr(addr), ra); = \ + *(TYPE *)(za + off * sizeof(ARMVectorReg)) =3D val; = \ +} + +#define DO_ST(NAME, TYPE, HOST, TLB) = \ +static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host)= \ +{ = \ + TYPE val =3D *(TYPE *)(za + off * sizeof(ARMVectorReg)); = \ + HOST(host, val); = \ +} = \ +static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za, = \ + intptr_t off, target_ulong addr, uintptr_t ra) = \ +{ = \ + TYPE val =3D *(TYPE *)(za + off * sizeof(ARMVectorReg)); = \ + TLB(env, useronly_clean_ptr(addr), val, ra); = \ +} + +/* + * The ARMVectorReg elements are stored in host-endian 64-bit units. + * For 128-bit quantities, the sequence defined by the Elem[] pseudocode + * corresponds to storing the two 64-bit pieces in little-endian order. + */ +#define DO_LDQ(HNAME, VNAME, BE, HOST, TLB) = \ +static inline void HNAME##_host(void *za, intptr_t off, void *host) = \ +{ = \ + uint64_t val0 =3D HOST(host), val1 =3D HOST(host + 8); = \ + uint64_t *ptr =3D za + off; = \ + ptr[0] =3D BE ? val1 : val0, ptr[1] =3D BE ? val0 : val1; = \ +} = \ +static inline void VNAME##_v_host(void *za, intptr_t off, void *host) = \ +{ = \ + HNAME##_host(za, off * sizeof(ARMVectorReg), host); = \ +} = \ +static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, = \ + target_ulong addr, uintptr_t ra) = \ +{ = \ + uint64_t val0 =3D TLB(env, useronly_clean_ptr(addr), ra); = \ + uint64_t val1 =3D TLB(env, useronly_clean_ptr(addr + 8), ra); = \ + uint64_t *ptr =3D za + off; = \ + ptr[0] =3D BE ? val1 : val0, ptr[1] =3D BE ? val0 : val1; = \ +} = \ +static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off,= \ + target_ulong addr, uintptr_t ra) = \ +{ = \ + HNAME##_tlb(env, za, off * sizeof(ARMVectorReg), addr, ra); = \ +} + +#define DO_STQ(HNAME, VNAME, BE, HOST, TLB) = \ +static inline void HNAME##_host(void *za, intptr_t off, void *host) = \ +{ = \ + uint64_t *ptr =3D za + off; = \ + HOST(host, ptr[BE]); = \ + HOST(host + 1, ptr[!BE]); = \ +} = \ +static inline void VNAME##_v_host(void *za, intptr_t off, void *host) = \ +{ = \ + HNAME##_host(za, off * sizeof(ARMVectorReg), host); = \ +} = \ +static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, = \ + target_ulong addr, uintptr_t ra) = \ +{ = \ + uint64_t *ptr =3D za + off; = \ + TLB(env, useronly_clean_ptr(addr), ptr[BE], ra); = \ + TLB(env, useronly_clean_ptr(addr + 8), ptr[!BE], ra); = \ +} = \ +static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off,= \ + target_ulong addr, uintptr_t ra) = \ +{ = \ + HNAME##_tlb(env, za, off * sizeof(ARMVectorReg), addr, ra); = \ +} + +DO_LD(ld1b, uint8_t, ldub_p, cpu_ldub_data_ra) +DO_LD(ld1h_be, uint16_t, lduw_be_p, cpu_lduw_be_data_ra) +DO_LD(ld1h_le, uint16_t, lduw_le_p, cpu_lduw_le_data_ra) +DO_LD(ld1s_be, uint32_t, ldl_be_p, cpu_ldl_be_data_ra) +DO_LD(ld1s_le, uint32_t, ldl_le_p, cpu_ldl_le_data_ra) +DO_LD(ld1d_be, uint64_t, ldq_be_p, cpu_ldq_be_data_ra) +DO_LD(ld1d_le, uint64_t, ldq_le_p, cpu_ldq_le_data_ra) + +DO_LDQ(sve_ld1qq_be, sme_ld1q_be, 1, ldq_be_p, cpu_ldq_be_data_ra) +DO_LDQ(sve_ld1qq_le, sme_ld1q_le, 0, ldq_le_p, cpu_ldq_le_data_ra) + +DO_ST(st1b, uint8_t, stb_p, cpu_stb_data_ra) +DO_ST(st1h_be, uint16_t, stw_be_p, cpu_stw_be_data_ra) +DO_ST(st1h_le, uint16_t, stw_le_p, cpu_stw_le_data_ra) +DO_ST(st1s_be, uint32_t, stl_be_p, cpu_stl_be_data_ra) +DO_ST(st1s_le, uint32_t, stl_le_p, cpu_stl_le_data_ra) +DO_ST(st1d_be, uint64_t, stq_be_p, cpu_stq_be_data_ra) +DO_ST(st1d_le, uint64_t, stq_le_p, cpu_stq_le_data_ra) + +DO_STQ(sve_st1qq_be, sme_st1q_be, 1, stq_be_p, cpu_stq_be_data_ra) +DO_STQ(sve_st1qq_le, sme_st1q_le, 0, stq_le_p, cpu_stq_le_data_ra) + +#undef DO_LD +#undef DO_ST +#undef DO_LDQ +#undef DO_STQ + +/* + * Common helper for all contiguous predicated loads. + */ + +static inline QEMU_ALWAYS_INLINE +void sme_ld1(CPUARMState *env, void *za, uint64_t *vg, + const target_ulong addr, uint32_t desc, const uintptr_t ra, + const int esz, uint32_t mtedesc, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn, + ClearFn *clr_fn, + CopyFn *cpy_fn) +{ + const intptr_t reg_max =3D simd_oprsz(desc); + const intptr_t esize =3D 1 << esz; + intptr_t reg_off, reg_last; + SVEContLdSt info; + void *host; + int flags; + + /* Find the active elements. */ + if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, esize)) { + /* The entire predicate was false; no load occurs. */ + clr_fn(za, 0, reg_max); + return; + } + + /* Probe the page(s). Exit with exception for any invalid page. */ + sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, ra); + + /* Handle watchpoints for all active elements. */ + sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize, + BP_MEM_READ, ra); + + /* + * Handle mte checks for all active elements. + * Since TBI must be set for MTE, !mtedesc =3D> !mte_active. + */ + if (mtedesc) { + sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize, + mtedesc, ra); + } + + flags =3D info.page[0].flags | info.page[1].flags; + if (unlikely(flags !=3D 0)) { +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + /* + * At least one page includes MMIO. + * Any bus operation can fail with cpu_transaction_failed, + * which for ARM will raise SyncExternal. Perform the load + * into scratch memory to preserve register state until the end. + */ + ARMVectorReg scratch =3D { }; + + reg_off =3D info.reg_off_first[0]; + reg_last =3D info.reg_off_last[1]; + if (reg_last < 0) { + reg_last =3D info.reg_off_split; + if (reg_last < 0) { + reg_last =3D info.reg_off_last[0]; + } + } + + do { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + tlb_fn(env, &scratch, reg_off, addr + reg_off, ra); + } + reg_off +=3D esize; + } while (reg_off & 63); + } while (reg_off <=3D reg_last); + + cpy_fn(za, &scratch, reg_max); + return; +#endif + } + + /* The entire operation is in RAM, on valid pages. */ + + reg_off =3D info.reg_off_first[0]; + reg_last =3D info.reg_off_last[0]; + host =3D info.page[0].host; + + if (!vertical) { + memset(za, 0, reg_max); + } else if (reg_off) { + clr_fn(za, 0, reg_off); + } + + while (reg_off <=3D reg_last) { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } else if (vertical) { + clr_fn(za, reg_off, esize); + } + reg_off +=3D esize; + } while (reg_off <=3D reg_last && (reg_off & 63)); + } + + /* + * Use the slow path to manage the cross-page misalignment. + * But we know this is RAM and cannot trap. + */ + reg_off =3D info.reg_off_split; + if (unlikely(reg_off >=3D 0)) { + tlb_fn(env, za, reg_off, addr + reg_off, ra); + } + + reg_off =3D info.reg_off_first[1]; + if (unlikely(reg_off >=3D 0)) { + reg_last =3D info.reg_off_last[1]; + host =3D info.page[1].host; + + do { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } else if (vertical) { + clr_fn(za, reg_off, esize); + } + reg_off +=3D esize; + } while (reg_off & 63); + } while (reg_off <=3D reg_last); + } +} + +static inline QEMU_ALWAYS_INLINE +void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg, + target_ulong addr, uint32_t desc, uintptr_t ra, + const int esz, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn, + ClearFn *clr_fn, + CopyFn *cpy_fn) +{ + uint32_t mtedesc =3D desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + int bit55 =3D extract64(addr, 55, 1); + + /* Remove mtedesc from the normal sve descriptor. */ + desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + + /* Perform gross MTE suppression early. */ + if (!tbi_check(desc, bit55) || + tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { + mtedesc =3D 0; + } + + sme_ld1(env, za, vg, addr, desc, ra, esz, mtedesc, vertical, + host_fn, tlb_fn, clr_fn, cpy_fn); +} + +#define DO_LD(L, END, ESZ) = \ +void HELPER(sme_ld1##L##END##_h)(CPUARMState *env, void *za, void *vg, = \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_ld1(env, za, vg, addr, desc, GETPC(), ESZ, 0, false, = \ + sve_ld1##L##L##END##_host, sve_ld1##L##L##END##_tlb, = \ + clear_horizontal, copy_horizontal); = \ +} = \ +void HELPER(sme_ld1##L##END##_v)(CPUARMState *env, void *za, void *vg, = \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_ld1(env, za, vg, addr, desc, GETPC(), ESZ, 0, true, = \ + sme_ld1##L##END##_v_host, sme_ld1##L##END##_v_tlb, = \ + clear_vertical_##L, copy_vertical_##L); = \ +} = \ +void HELPER(sme_ld1##L##END##_h_mte)(CPUARMState *env, void *za, void *vg,= \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_ld1_mte(env, za, vg, addr, desc, GETPC(), ESZ, false, = \ + sve_ld1##L##L##END##_host, sve_ld1##L##L##END##_tlb, = \ + clear_horizontal, copy_horizontal); = \ +} = \ +void HELPER(sme_ld1##L##END##_v_mte)(CPUARMState *env, void *za, void *vg,= \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_ld1_mte(env, za, vg, addr, desc, GETPC(), ESZ, true, = \ + sme_ld1##L##END##_v_host, sme_ld1##L##END##_v_tlb, = \ + clear_vertical_##L, copy_vertical_##L); = \ +} + +DO_LD(b, , MO_8) +DO_LD(h, _be, MO_16) +DO_LD(h, _le, MO_16) +DO_LD(s, _be, MO_32) +DO_LD(s, _le, MO_32) +DO_LD(d, _be, MO_64) +DO_LD(d, _le, MO_64) +DO_LD(q, _be, MO_128) +DO_LD(q, _le, MO_128) + +#undef DO_LD + +/* + * Common helper for all contiguous predicated stores. + */ + +static inline QEMU_ALWAYS_INLINE +void sme_st1(CPUARMState *env, void *za, uint64_t *vg, + const target_ulong addr, uint32_t desc, const uintptr_t ra, + const int esz, uint32_t mtedesc, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn) +{ + const intptr_t reg_max =3D simd_oprsz(desc); + const intptr_t esize =3D 1 << esz; + intptr_t reg_off, reg_last; + SVEContLdSt info; + void *host; + int flags; + + /* Find the active elements. */ + if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, esize)) { + /* The entire predicate was false; no store occurs. */ + return; + } + + /* Probe the page(s). Exit with exception for any invalid page. */ + sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_STORE, ra); + + /* Handle watchpoints for all active elements. */ + sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize, + BP_MEM_WRITE, ra); + + /* + * Handle mte checks for all active elements. + * Since TBI must be set for MTE, !mtedesc =3D> !mte_active. + */ + if (mtedesc) { + sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize, + mtedesc, ra); + } + + flags =3D info.page[0].flags | info.page[1].flags; + if (unlikely(flags !=3D 0)) { +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + /* + * At least one page includes MMIO. + * Any bus operation can fail with cpu_transaction_failed, + * which for ARM will raise SyncExternal. We cannot avoid + * this fault and will leave with the store incomplete. + */ + reg_off =3D info.reg_off_first[0]; + reg_last =3D info.reg_off_last[1]; + if (reg_last < 0) { + reg_last =3D info.reg_off_split; + if (reg_last < 0) { + reg_last =3D info.reg_off_last[0]; + } + } + + do { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + tlb_fn(env, za, reg_off, addr + reg_off, ra); + } + reg_off +=3D esize; + } while (reg_off & 63); + } while (reg_off <=3D reg_last); + return; +#endif + } + + reg_off =3D info.reg_off_first[0]; + reg_last =3D info.reg_off_last[0]; + host =3D info.page[0].host; + + while (reg_off <=3D reg_last) { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } + reg_off +=3D 1 << esz; + } while (reg_off <=3D reg_last && (reg_off & 63)); + } + + /* + * Use the slow path to manage the cross-page misalignment. + * But we know this is RAM and cannot trap. + */ + reg_off =3D info.reg_off_split; + if (unlikely(reg_off >=3D 0)) { + tlb_fn(env, za, reg_off, addr + reg_off, ra); + } + + reg_off =3D info.reg_off_first[1]; + if (unlikely(reg_off >=3D 0)) { + reg_last =3D info.reg_off_last[1]; + host =3D info.page[1].host; + + do { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } + reg_off +=3D 1 << esz; + } while (reg_off & 63); + } while (reg_off <=3D reg_last); + } +} + +static inline QEMU_ALWAYS_INLINE +void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong ad= dr, + uint32_t desc, uintptr_t ra, int esz, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn) +{ + uint32_t mtedesc =3D desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + int bit55 =3D extract64(addr, 55, 1); + + /* Remove mtedesc from the normal sve descriptor. */ + desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + + /* Perform gross MTE suppression early. */ + if (!tbi_check(desc, bit55) || + tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { + mtedesc =3D 0; + } + + sme_st1(env, za, vg, addr, desc, ra, esz, mtedesc, + vertical, host_fn, tlb_fn); +} + +#define DO_ST(L, END, ESZ) = \ +void HELPER(sme_st1##L##END##_h)(CPUARMState *env, void *za, void *vg, = \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_st1(env, za, vg, addr, desc, GETPC(), ESZ, 0, false, = \ + sve_st1##L##L##END##_host, sve_st1##L##L##END##_tlb); = \ +} = \ +void HELPER(sme_st1##L##END##_v)(CPUARMState *env, void *za, void *vg, = \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_st1(env, za, vg, addr, desc, GETPC(), ESZ, 0, true, = \ + sme_st1##L##END##_v_host, sme_st1##L##END##_v_tlb); = \ +} = \ +void HELPER(sme_st1##L##END##_h_mte)(CPUARMState *env, void *za, void *vg,= \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_st1_mte(env, za, vg, addr, desc, GETPC(), ESZ, false, = \ + sve_st1##L##L##END##_host, sve_st1##L##L##END##_tlb); = \ +} = \ +void HELPER(sme_st1##L##END##_v_mte)(CPUARMState *env, void *za, void *vg,= \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_st1_mte(env, za, vg, addr, desc, GETPC(), ESZ, true, = \ + sme_st1##L##END##_v_host, sme_st1##L##END##_v_tlb); = \ +} + +DO_ST(b, , MO_8) +DO_ST(h, _be, MO_16) +DO_ST(h, _le, MO_16) +DO_ST(s, _be, MO_32) +DO_ST(s, _le, MO_32) +DO_ST(d, _be, MO_64) +DO_ST(d, _le, MO_64) +DO_ST(q, _be, MO_128) +DO_ST(q, _le, MO_128) + +#undef DO_ST diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 8e6881086b..f9846f137f 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -176,3 +176,73 @@ static bool trans_MOVA(DisasContext *s, arg_MOVA *a) =20 return true; } + +static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) +{ + typedef void GenLdSt1(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv, TCGv_i32); + + /* + * Indexed by [esz][be][v][mte][st], which is (except for load/store) + * also the order in which the elements appear in the function names, + * and so how we must concatenate the pieces. + */ + +#define FN_LS(F) { gen_helper_sme_ld1##F, gen_helper_sme_st1##F } +#define FN_MTE(F) { FN_LS(F), FN_LS(F##_mte) } +#define FN_HV(F) { FN_MTE(F##_h), FN_MTE(F##_v) } +#define FN_END(L, B) { FN_HV(L), FN_HV(B) } + + static GenLdSt1 * const fns[5][2][2][2][2] =3D { + FN_END(b, b), + FN_END(h_le, h_be), + FN_END(s_le, s_be), + FN_END(d_le, d_be), + FN_END(q_le, q_be), + }; + +#undef FN_LS +#undef FN_MTE +#undef FN_HV +#undef FN_END + + TCGv_ptr t_za, t_pg; + TCGv_i64 addr; + int svl, desc =3D 0; + bool be =3D s->be_data =3D=3D MO_BE; + bool mte =3D s->mte_active[0]; + + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (!sme_smza_enabled_check(s)) { + return true; + } + + t_za =3D get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v); + t_pg =3D pred_full_reg_ptr(s, a->pg); + addr =3D tcg_temp_new_i64(); + + tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz); + tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); + + if (mte) { + desc =3D FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); + desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); + desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); + desc =3D FIELD_DP32(desc, MTEDESC, WRITE, a->st); + desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1); + desc <<=3D SVE_MTEDESC_SHIFT; + } else { + addr =3D clean_data_tbi(s, addr); + } + svl =3D streaming_vec_reg_size(s); + desc =3D simd_desc(svl, svl, desc); + + fns[a->esz][be][a->v][mte][a->st](cpu_env, t_za, t_pg, addr, + tcg_constant_i32(desc)); + + tcg_temp_free_ptr(t_za); + tcg_temp_free_ptr(t_pg); + tcg_temp_free_i64(addr); + return true; +} --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656392435165838.9287209726724; Mon, 27 Jun 2022 22:00:35 -0700 (PDT) Received: from localhost ([::1]:49290 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o63Kz-0002Kj-Rp for importer@patchew.org; Tue, 28 Jun 2022 01:00:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37448) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62jy-00025E-R3 for qemu-devel@nongnu.org; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.22.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:22:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=s1QgksttsueY6FvMnd78DU1ItWwupOc7VixnN8qFMG0=; b=HDES5eo+iAEwEYGGr7iBNN/vUCq17yvYhIWS/gWUmwoDu5rKDrOOJOBtepvbpaDvnf fvWNY5xoOqZvpjeMMtnfNfuiUGLAOSxO2lkvrsD11ggaHQ1s7aCzlCXbsJvqxFu4GNuF Q1EAE4TmvWu8YN+EyVqiCXgm81f6Q/8Mr1XQET0CT8mLiGYVvDtmcA5ErLhDzHy4l8G5 +sqLblZlAGWdyt1igmS/b8+z4y3RaKgwmj4F4+LBqjODLtx0SLFRkMxrmoPTQh4ytcql 3Vi+fEgX46jtQ9U+drnJmIBlK1zkTtX1AWJb9F5SajZOjebBNnOTE1o/+IjQN3oXD6xI b2Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=s1QgksttsueY6FvMnd78DU1ItWwupOc7VixnN8qFMG0=; b=pqq+R2+kKcz5ihqnIcDzDozH/3zJmQ9MbnuR9sXhSfYTlF8/V69ahF5GjztoVgJ/rU FqFkBrZB4W3PShF+Ask8MTaEe5WA3p6MhWYWS5921CuQp4dAHg+lBmo3G6TRI8WfEwsJ XnwWd5K1CbyYsy1UOpT6JCAS8LI4Rc04i3WpRUPqx95HjEA9ZsjXe/tCJx6JWNKvnKEI fB3M6Uug2PYLWvTqoKGa8Hc5hTQUzz3jAS0cVSy4HNRcRqG8Zicn+wofTxRMYMA2kUZ1 Ygo+OZpwRddadxIJA5I6IbPrRkOdJdOQdQ0XcfynBDD9fW0uzcSHOAy0Ow1KzFbpVkR2 TQTA== X-Gm-Message-State: AJIora+K6k10IxJQglNgEdhmw4bBbkZSjwoB0RE63jxyIIn31ABvxy2/ g+dj4xXtbSTgCp008VrsCj/IV1K8i7cvbw== X-Google-Smtp-Source: AGRyM1sUuexrpEXuV8ibR9ZJd52WsC5IgYQ4F2YYlakopDrTmn5ZBwu4q60z1rRARf4KOJ+br95YzQ== X-Received: by 2002:a63:af1c:0:b0:40c:f9d6:9f07 with SMTP id w28-20020a63af1c000000b0040cf9d69f07mr15435055pge.384.1656390132352; Mon, 27 Jun 2022 21:22:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v4 21/45] target/arm: Export unpredicated ld/st from translate-sve.c Date: Tue, 28 Jun 2022 09:50:53 +0530 Message-Id: <20220628042117.368549-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656392436615100001 Content-Type: text/plain; charset="utf-8" Add a TCGv_ptr base argument, which will be cpu_env for SVE. We will reuse this for SME save and restore array insns. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 3 +++ target/arm/translate-sve.c | 48 ++++++++++++++++++++++++++++---------- 2 files changed, 39 insertions(+), 12 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 2a7fe6e9e7..ad3762d1ac 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -195,4 +195,7 @@ void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint3= 2_t rn_ofs, uint32_t rm_ofs, int64_t shift, uint32_t opr_sz, uint32_t max_sz); =20 +void gen_sve_ldr(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int= imm); +void gen_sve_str(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int= imm); + #endif /* TARGET_ARM_TRANSLATE_A64_H */ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 9e304f78bc..374a0a87f2 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4306,7 +4306,8 @@ TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz, * The load should begin at the address Rn + IMM. */ =20 -static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int im= m) +void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs, + int len, int rn, int imm) { int len_align =3D QEMU_ALIGN_DOWN(len, 8); int len_remain =3D len % 8; @@ -4332,7 +4333,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, in= t len, int rn, int imm) t0 =3D tcg_temp_new_i64(); for (i =3D 0; i < len_align; i +=3D 8) { tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ); - tcg_gen_st_i64(t0, cpu_env, vofs + i); + tcg_gen_st_i64(t0, base, vofs + i); tcg_gen_addi_i64(clean_addr, clean_addr, 8); } tcg_temp_free_i64(t0); @@ -4345,6 +4346,12 @@ static void do_ldr(DisasContext *s, uint32_t vofs, i= nt len, int rn, int imm) clean_addr =3D new_tmp_a64_local(s); tcg_gen_mov_i64(clean_addr, t0); =20 + if (base !=3D cpu_env) { + TCGv_ptr b =3D tcg_temp_local_new_ptr(); + tcg_gen_mov_ptr(b, base); + base =3D b; + } + gen_set_label(loop); =20 t0 =3D tcg_temp_new_i64(); @@ -4352,7 +4359,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, in= t len, int rn, int imm) tcg_gen_addi_i64(clean_addr, clean_addr, 8); =20 tp =3D tcg_temp_new_ptr(); - tcg_gen_add_ptr(tp, cpu_env, i); + tcg_gen_add_ptr(tp, base, i); tcg_gen_addi_ptr(i, i, 8); tcg_gen_st_i64(t0, tp, vofs); tcg_temp_free_ptr(tp); @@ -4360,6 +4367,11 @@ static void do_ldr(DisasContext *s, uint32_t vofs, i= nt len, int rn, int imm) =20 tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); tcg_temp_free_ptr(i); + + if (base !=3D cpu_env) { + tcg_temp_free_ptr(base); + assert(len_remain =3D=3D 0); + } } =20 /* @@ -4388,13 +4400,14 @@ static void do_ldr(DisasContext *s, uint32_t vofs, = int len, int rn, int imm) default: g_assert_not_reached(); } - tcg_gen_st_i64(t0, cpu_env, vofs + len_align); + tcg_gen_st_i64(t0, base, vofs + len_align); tcg_temp_free_i64(t0); } } =20 /* Similarly for stores. */ -static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int im= m) +void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs, + int len, int rn, int imm) { int len_align =3D QEMU_ALIGN_DOWN(len, 8); int len_remain =3D len % 8; @@ -4420,7 +4433,7 @@ static void do_str(DisasContext *s, uint32_t vofs, in= t len, int rn, int imm) =20 t0 =3D tcg_temp_new_i64(); for (i =3D 0; i < len_align; i +=3D 8) { - tcg_gen_ld_i64(t0, cpu_env, vofs + i); + tcg_gen_ld_i64(t0, base, vofs + i); tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); tcg_gen_addi_i64(clean_addr, clean_addr, 8); } @@ -4434,11 +4447,17 @@ static void do_str(DisasContext *s, uint32_t vofs, = int len, int rn, int imm) clean_addr =3D new_tmp_a64_local(s); tcg_gen_mov_i64(clean_addr, t0); =20 + if (base !=3D cpu_env) { + TCGv_ptr b =3D tcg_temp_local_new_ptr(); + tcg_gen_mov_ptr(b, base); + base =3D b; + } + gen_set_label(loop); =20 t0 =3D tcg_temp_new_i64(); tp =3D tcg_temp_new_ptr(); - tcg_gen_add_ptr(tp, cpu_env, i); + tcg_gen_add_ptr(tp, base, i); tcg_gen_ld_i64(t0, tp, vofs); tcg_gen_addi_ptr(i, i, 8); tcg_temp_free_ptr(tp); @@ -4449,12 +4468,17 @@ static void do_str(DisasContext *s, uint32_t vofs, = int len, int rn, int imm) =20 tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); tcg_temp_free_ptr(i); + + if (base !=3D cpu_env) { + tcg_temp_free_ptr(base); + assert(len_remain =3D=3D 0); + } } =20 /* Predicate register stores can be any multiple of 2. */ if (len_remain) { t0 =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(t0, cpu_env, vofs + len_align); + tcg_gen_ld_i64(t0, base, vofs + len_align); =20 switch (len_remain) { case 2: @@ -4486,7 +4510,7 @@ static bool trans_LDR_zri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D vec_full_reg_size(s); int off =3D vec_full_reg_offset(s, a->rd); - do_ldr(s, off, size, a->rn, a->imm * size); + gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } @@ -4499,7 +4523,7 @@ static bool trans_LDR_pri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D pred_full_reg_size(s); int off =3D pred_full_reg_offset(s, a->rd); - do_ldr(s, off, size, a->rn, a->imm * size); + gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } @@ -4512,7 +4536,7 @@ static bool trans_STR_zri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D vec_full_reg_size(s); int off =3D vec_full_reg_offset(s, a->rd); - do_str(s, off, size, a->rn, a->imm * size); + gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } @@ -4525,7 +4549,7 @@ static bool trans_STR_pri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D pred_full_reg_size(s); int off =3D pred_full_reg_offset(s, a->rd); - do_str(s, off, size, a->rn, a->imm * size); + gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656391719870814.4567683595764; Mon, 27 Jun 2022 21:48:39 -0700 (PDT) Received: from localhost ([::1]:46732 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o639S-0006Pd-Kq for importer@patchew.org; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.22.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:22:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=etMuVHeaAxa7UcmLEv5W86A71baIUw+lp8OsVjYF6WM=; b=puj1I9y/VtHkwVJGHxevoTOBp1e2q2AntNADVlFiTKf2CkV7X5+wD8Kf7Aq+Hji1HS JXWepixmwfbIJsYQUyN/6+2VttmQ2dJtwy9F8Kj4l1h8k0/WrlsGxt0s/8nAvXwXaatJ o3Tu8LOaTqAjCpl3iWFAuKPrCMNK9Lvh4M6cXi8lz/ynUs/25mXJcTITWzEuSaMlHc6p YKP8BYJS3kSW0k1yQ0OGWjF/wmmwTfJRBbCom7SWs4oenBcGm553MVkynQJpaaqJajaL UoEaM4vpgo0jCZSZ4NjH1GfNUZOoxBvYIHlDX2wMZSI0yZVvoLdys6N/aEOY+X/cjhpY +Kdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=etMuVHeaAxa7UcmLEv5W86A71baIUw+lp8OsVjYF6WM=; b=1oWyhaxI0TK/JAAjPdg995BKpm/eZqJoZUSxNc/3j9iHfNSoITlbyhAfgzKwrFeGXy xfzfJHjdSsiOIrGXrSgxABW/HiEun8DdGxUZpjb9XKUKgOJTfiufggDRo55qsBTBRpkX OKSKXRIHBZ6uShvul9VQd8W5Pj0kr/18YrVSDeQqSuDIsMd57NMe713LYmscrCbn2Een 7bazeavb/fqCBTUZ/BkrLQWoTTq8ZYK67b+aSSD7ss3zRmYT2LlTGM/m25cveT5lqtAm j3WnmHPA+n+0znTEDAc0wE0nDHk1pERaO0TVCdwCkeJiKrGocAQbEThm9sKPIfZfd2j2 1sEw== X-Gm-Message-State: AJIora/slua1/J3EoBhGjcXqkJmMVUxKuBB4O2JxJOOJ8utjzyj60wmw W0U4Mwx4GzTsUCG/KHPMBoDozL8ynLKBzQ== X-Google-Smtp-Source: AGRyM1tMSlXDEJmaofYfXW3uQOFhMZM6li87nFj6lR9u9M+/pqkGfsAubx+4T0isNERjAtM7fKW2eg== X-Received: by 2002:a63:3e47:0:b0:40c:fa04:dd6e with SMTP id l68-20020a633e47000000b0040cfa04dd6emr15900035pga.224.1656390134643; Mon, 27 Jun 2022 21:22:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v4 22/45] target/arm: Implement SME LDR, STR Date: Tue, 28 Jun 2022 09:50:54 +0530 Message-Id: <20220628042117.368549-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656391721420100001 Content-Type: text/plain; charset="utf-8" We can reuse the SVE functions for LDR and STR, passing in the base of the ZA vector and a zero offset. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sme.decode | 7 +++++++ target/arm/translate-sme.c | 24 ++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 900e3f2a07..f1ebd857a5 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -46,3 +46,10 @@ LDST1 1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn= :5 0 za_imm:4 \ &ldst rs=3D%mova_rs LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ &ldst esz=3D4 rs=3D%mova_rs + +&ldstr rv rn imm +@ldstr ....... ... . ...... .. ... rn:5 . imm:4 \ + &ldstr rv=3D%mova_rs + +LDR 1110000 100 0 000000 .. 000 ..... 0 .... @ldstr +STR 1110000 100 1 000000 .. 000 ..... 0 .... @ldstr diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index f9846f137f..87bbf9ab7f 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -246,3 +246,27 @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) tcg_temp_free_i64(addr); return true; } + +typedef void GenLdStR(DisasContext *, TCGv_ptr, int, int, int, int); + +static bool do_ldst_r(DisasContext *s, arg_ldstr *a, GenLdStR *fn) +{ + int svl =3D streaming_vec_reg_size(s); + int imm =3D a->imm; + TCGv_ptr base; + + if (!sme_za_enabled_check(s)) { + return true; + } + + /* ZA[n] equates to ZA0H.B[n]. */ + base =3D get_tile_rowcol(s, MO_8, a->rv, imm, false); + + fn(s, base, 0, svl, a->rn, imm * svl); + + tcg_temp_free_ptr(base); + return true; +} + +TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr) +TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str) --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656391378339983.5127378718539; Mon, 27 Jun 2022 21:42:58 -0700 (PDT) Received: from localhost ([::1]:35504 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o633x-0006rc-1I for importer@patchew.org; Tue, 28 Jun 2022 00:42:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37522) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62k2-00028r-SG for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:23 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:35594) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62jy-0003lP-Ms for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:21 -0400 Received: by mail-pj1-x1032.google.com with SMTP id x1-20020a17090abc8100b001ec7f8a51f5so14626314pjr.0 for ; Mon, 27 Jun 2022 21:22:17 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.22.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:22:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TAvqWTorLRtZ2RYJUMwjEw2a2lKrYwmfuEb0hOk02IA=; b=fVjlFnBtoLlZyD4xH2beo4sb1IxWHE0Cjhcne3VLZymh5WhnAQsQ91GYZDOwAt8izf XN3Bhm7hCrrsGCFNf61ZpE6+RsYzOJq72+RQjZ/QgiS3KLGLV6gqfmrPfgz3N3/g9+YR ZtBYJCy/utEhjhRd7GUpRfH+ZXquHM3N+2oUF3OsIp0ey9XlsXaT7YZblsYTCFR6Aq7f /R64UENh+K8MjxTHm4V1bXxk7BlmufdtPP4mXNun8ZeYILtZSwiz5NJ1l/NpzP5r9fBD Q+Wq+2LHUSHsM6XSHh1g2s5MeBTZL6EAKvq+z9giJGpJbN1uEy6+lcrTXfrKrn9SIY4H Vmxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TAvqWTorLRtZ2RYJUMwjEw2a2lKrYwmfuEb0hOk02IA=; b=FXB0f2hprRC7EQw9pw6mkcLEkYiuhSnMS8ILkWcG6FX5x4Dg2hUtNntkPMHfV3KdMg ajdaZsJiP9syCn1Dme1UI9L6riPTYpNjBeTpQizAKy2IbWN0qjCO1CIyvW+Qy0Rt6aNc g8fXGG3OC5AEiUKSoKd9g6/zNTTf4GSVxIB+agmU2sZUZRqebMOO940Z0oWbn/yHTARp JuevcuYfAYCTq1ABfh7zy1NUkKH0V2vulfIc+qtL50QUtdvwngj5twO4Qv+uYuE24fPF yv1rVX5k8qGKW4vt+X7NClTY7c1Z5/sx+FHfINtbK6jdZYjPK6za4gvkN2pZCMYAscE4 mxbw== X-Gm-Message-State: AJIora9SPw4ae+qgRypNNVp/vn+BbEFsDkoEjyjjLFuOBij6RqZGMU+O yMI/VIfI0XmW8lBibIMnihZvzfaEwx+FkA== X-Google-Smtp-Source: AGRyM1udSqsWZBP4hybcHHgL42/n/5spvXmr2aupJrb4b1MjzeRep2WiGWLdJsZ7Q0fW7m7kWq7JfQ== X-Received: by 2002:a17:902:d504:b0:16a:4846:3f46 with SMTP id b4-20020a170902d50400b0016a48463f46mr1619343plg.159.1656390136925; Mon, 27 Jun 2022 21:22:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 23/45] target/arm: Implement SME ADDHA, ADDVA Date: Tue, 28 Jun 2022 09:50:55 +0530 Message-Id: <20220628042117.368549-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656391379837100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- v4: Drop restrict. --- target/arm/helper-sme.h | 5 +++ target/arm/sme.decode | 11 +++++ target/arm/sme_helper.c | 90 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 31 +++++++++++++ 4 files changed, 137 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 95f6e88bdd..753e9e624c 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -115,3 +115,8 @@ DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, v= oid, env, ptr, ptr, tl, i DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) +DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) +DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) +DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index f1ebd857a5..8cb6c4053c 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -53,3 +53,14 @@ LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn= :5 0 za_imm:4 \ =20 LDR 1110000 100 0 000000 .. 000 ..... 0 .... @ldstr STR 1110000 100 1 000000 .. 000 ..... 0 .... @ldstr + +### SME Add Vector to Array + +&adda zad zn pm pn +@adda_32 ........ .. ..... . pm:3 pn:3 zn:5 ... zad:2 &adda +@adda_64 ........ .. ..... . pm:3 pn:3 zn:5 .. zad:3 &adda + +ADDHA_s 11000000 10 01000 0 ... ... ..... 000 .. @adda_32 +ADDVA_s 11000000 10 01000 1 ... ... ..... 000 .. @adda_32 +ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64 +ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 4ff4e22c2c..61fe9e9dc8 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -808,3 +808,93 @@ DO_ST(q, _be, MO_128) DO_ST(q, _le, MO_128) =20 #undef DO_ST + +void HELPER(sme_addha_s)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 4; + uint64_t *pn =3D vpn, *pm =3D vpm; + uint32_t *zda =3D vzda, *zn =3D vzn; + + for (row =3D 0; row < oprsz; ) { + uint64_t pa =3D pn[row >> 4]; + do { + if (pa & 1) { + for (col =3D 0; col < oprsz; ) { + uint64_t pb =3D pm[col >> 4]; + do { + if (pb & 1) { + zda[row * sizeof(ARMVectorReg) + col] +=3D zn[= col]; + } + pb >>=3D 4; + } while (++col & 15); + } + } + pa >>=3D 4; + } while (++row & 15); + } +} + +void HELPER(sme_addha_d)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8; + uint8_t *pn =3D vpn, *pm =3D vpm; + uint64_t *zda =3D vzda, *zn =3D vzn; + + for (row =3D 0; row < oprsz; ++row) { + if (pn[H1(row)] & 1) { + for (col =3D 0; col < oprsz; ++col) { + if (pm[H1(col)] & 1) { + zda[row * sizeof(ARMVectorReg) + col] +=3D zn[col]; + } + } + } + } +} + +void HELPER(sme_addva_s)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 4; + uint64_t *pn =3D vpn, *pm =3D vpm; + uint32_t *zda =3D vzda, *zn =3D vzn; + + for (row =3D 0; row < oprsz; ) { + uint64_t pa =3D pn[row >> 4]; + do { + if (pa & 1) { + uint32_t zn_row =3D zn[row]; + for (col =3D 0; col < oprsz; ) { + uint64_t pb =3D pm[col >> 4]; + do { + if (pb & 1) { + zda[row * sizeof(ARMVectorReg) + col] +=3D zn_= row; + } + pb >>=3D 4; + } while (++col & 15); + } + } + pa >>=3D 4; + } while (++row & 15); + } +} + +void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8; + uint8_t *pn =3D vpn, *pm =3D vpm; + uint64_t *zda =3D vzda, *zn =3D vzn; + + for (row =3D 0; row < oprsz; ++row) { + if (pn[H1(row)] & 1) { + uint64_t zn_row =3D zn[row]; + for (col =3D 0; col < oprsz; ++col) { + if (pm[H1(col)] & 1) { + zda[row * sizeof(ARMVectorReg) + col] +=3D zn_row; + } + } + } + } +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 87bbf9ab7f..12995d6a46 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -270,3 +270,34 @@ static bool do_ldst_r(DisasContext *s, arg_ldstr *a, G= enLdStR *fn) =20 TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr) TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str) + +static bool do_adda(DisasContext *s, arg_adda *a, MemOp esz, + gen_helper_gvec_4 *fn) +{ + int svl =3D streaming_vec_reg_size(s); + uint32_t desc =3D simd_desc(svl, svl, 0); + TCGv_ptr za, zn, pn, pm; + + if (!sme_smza_enabled_check(s)) { + return true; + } + + /* Sum XZR+zad to find ZAd. */ + za =3D get_tile_rowcol(s, esz, 31, a->zad, false); + zn =3D vec_full_reg_ptr(s, a->zn); + pn =3D pred_full_reg_ptr(s, a->pn); + pm =3D pred_full_reg_ptr(s, a->pm); + + fn(za, zn, pn, pm, tcg_constant_i32(desc)); + + tcg_temp_free_ptr(za); + tcg_temp_free_ptr(zn); + tcg_temp_free_ptr(pn); + tcg_temp_free_ptr(pm); + return true; +} + +TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addha_s) +TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s) +TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= ha_d) +TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= va_d) --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656391667082100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 5 +++ target/arm/sme.decode | 9 ++++++ target/arm/sme_helper.c | 63 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 32 +++++++++++++++++++ 4 files changed, 109 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 753e9e624c..f50d0fe1d6 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -120,3 +120,8 @@ DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) + +DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 8cb6c4053c..ba4774d174 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -64,3 +64,12 @@ ADDHA_s 11000000 10 01000 0 ... ... ..... 000 ..= @adda_32 ADDVA_s 11000000 10 01000 1 ... ... ..... 000 .. @adda_32 ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64 ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64 + +### SME Outer Product + +&op zad zn zm pm pn sub:bool +@op_32 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 .. zad:2 &op +@op_64 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 . zad:3 &op + +FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32 +FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 61fe9e9dc8..31c53ad896 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -25,6 +25,7 @@ #include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "qemu/int128.h" +#include "fpu/softfloat.h" #include "vec_internal.h" #include "sve_ldst_internal.h" =20 @@ -898,3 +899,65 @@ void HELPER(sme_addva_d)(void *vzda, void *vzn, void *= vpn, } } } + +void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, void *vst, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_maxsz(desc); + uint32_t neg =3D simd_data(desc) << 31; + uint16_t *pn =3D vpn, *pm =3D vpm; + float_status fpst =3D *(float_status *)vst; + + set_default_nan_mode(true, &fpst); + + for (row =3D 0; row < oprsz; ) { + uint16_t pa =3D pn[H2(row >> 4)]; + do { + if (pa & 1) { + void *vza_row =3D vza + row * sizeof(ARMVectorReg); + uint32_t n =3D *(uint32_t *)(vzn + row) ^ neg; + + for (col =3D 0; col < oprsz; ) { + uint16_t pb =3D pm[H2(col >> 4)]; + do { + if (pb & 1) { + uint32_t *a =3D vza_row + col; + uint32_t *m =3D vzm + col; + *a =3D float32_muladd(n, *m, *a, 0, vst); + } + col +=3D 4; + pb >>=3D 4; + } while (col & 15); + } + } + row +=3D 4; + pa >>=3D 4; + } while (row & 15); + } +} + +void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, void *vst, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8; + uint64_t neg =3D (uint64_t)simd_data(desc) << 63; + uint64_t *za =3D vza, *zn =3D vzn, *zm =3D vzm; + uint8_t *pn =3D vpn, *pm =3D vpm; + float_status fpst =3D *(float_status *)vst; + + set_default_nan_mode(true, &fpst); + + for (row =3D 0; row < oprsz; ++row) { + if (pn[H1(row)] & 1) { + uint64_t *za_row =3D &za[row * sizeof(ARMVectorReg)]; + uint64_t n =3D zn[row] ^ neg; + + for (col =3D 0; col < oprsz; ++col) { + if (pm[H1(col)] & 1) { + uint64_t *a =3D &za_row[col]; + *a =3D float64_muladd(n, zm[col], *a, 0, &fpst); + } + } + } + } +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 12995d6a46..1117a61f62 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -301,3 +301,35 @@ TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_h= elper_sme_addha_s) TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s) TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= ha_d) TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= va_d) + +static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, + gen_helper_gvec_5_ptr *fn) +{ + int svl =3D streaming_vec_reg_size(s); + uint32_t desc =3D simd_desc(svl, svl, a->sub); + TCGv_ptr za, zn, zm, pn, pm, fpst; + + if (!sme_smza_enabled_check(s)) { + return true; + } + + /* Sum XZR+zad to find ZAd. */ + za =3D get_tile_rowcol(s, esz, 31, a->zad, false); + zn =3D vec_full_reg_ptr(s, a->zn); + zm =3D vec_full_reg_ptr(s, a->zm); + pn =3D pred_full_reg_ptr(s, a->pn); + pm =3D pred_full_reg_ptr(s, a->pm); + fpst =3D fpstatus_ptr(FPST_FPCR); + + fn(za, zn, zm, pn, pm, fpst, tcg_constant_i32(desc)); + + tcg_temp_free_ptr(za); + tcg_temp_free_ptr(zn); + tcg_temp_free_ptr(pn); + tcg_temp_free_ptr(pm); + tcg_temp_free_ptr(fpst); + return true; +} + +TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fm= opa_s) +TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper= _sme_fmopa_d) --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656391968279100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 2 ++ target/arm/sme.decode | 2 ++ target/arm/sme_helper.c | 52 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 30 ++++++++++++++++++++++ 4 files changed, 86 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index f50d0fe1d6..1d68fb8c74 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -125,3 +125,5 @@ DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index ba4774d174..afd9c0dffd 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -73,3 +73,5 @@ ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... = @adda_64 =20 FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32 FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 + +BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 31c53ad896..d2e1057124 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -961,3 +961,55 @@ void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *v= zm, void *vpn, } } } + +/* + * Alter PAIR as needed for controlling predicates being false, + * and for NEG on an enabled row element. + */ +static inline uint32_t f16mop_adj_pair(uint32_t pair, uint32_t pg, uint32_= t neg) +{ + pair ^=3D neg; + if (!(pg & 1)) { + pair &=3D 0xffff0000u; + } + if (!(pg & 4)) { + pair &=3D 0x0000ffffu; + } + return pair; +} + +void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_maxsz(desc); + uint32_t neg =3D simd_data(desc) << 15; + uint16_t *pn =3D vpn, *pm =3D vpm; + + for (row =3D 0; row < oprsz; ) { + uint16_t pa =3D pn[H2(row >> 4)]; + do { + void *vza_row =3D vza + row * sizeof(ARMVectorReg); + uint32_t n =3D *(uint32_t *)(vzn + row); + + n =3D f16mop_adj_pair(n, pa, neg); + + for (col =3D 0; col < oprsz; ) { + uint16_t pb =3D pm[H2(col >> 4)]; + do { + if ((pa & 0b0101) =3D=3D 0b0101 || (pb & 0b0101) =3D= =3D 0b0101) { + uint32_t *a =3D vza_row + col; + uint32_t m =3D *(uint32_t *)(vzm + col); + + m =3D f16mop_adj_pair(m, pb, neg); + *a =3D bfdotadd(*a, n, m); + + col +=3D 4; + pb >>=3D 4; + } + } while (col & 15); + } + row +=3D 4; + pa >>=3D 4; + } while (row & 15); + } +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 1117a61f62..e537a14b6d 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -302,6 +302,33 @@ TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_h= elper_sme_addva_s) TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= ha_d) TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= va_d) =20 +static bool do_outprod(DisasContext *s, arg_op *a, MemOp esz, + gen_helper_gvec_5 *fn) +{ + int svl =3D streaming_vec_reg_size(s); + uint32_t desc =3D simd_desc(svl, svl, a->sub); + TCGv_ptr za, zn, zm, pn, pm; + + if (!sme_smza_enabled_check(s)) { + return true; + } + + /* Sum XZR+zad to find ZAd. */ + za =3D get_tile_rowcol(s, esz, 31, a->zad, false); + zn =3D vec_full_reg_ptr(s, a->zn); + zm =3D vec_full_reg_ptr(s, a->zm); + pn =3D pred_full_reg_ptr(s, a->pn); + pm =3D pred_full_reg_ptr(s, a->pm); + + fn(za, zn, zm, pn, pm, tcg_constant_i32(desc)); + + tcg_temp_free_ptr(za); + tcg_temp_free_ptr(zn); + tcg_temp_free_ptr(pn); + tcg_temp_free_ptr(pm); + return true; +} + static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, gen_helper_gvec_5_ptr *fn) { @@ -333,3 +360,6 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a,= MemOp esz, =20 TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fm= opa_s) TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper= _sme_fmopa_d) + +/* TODO: FEAT_EBF16 */ +TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa) --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.22.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:22:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jaoQinxUaximkiCoQcc+UCRePY0G4BJDjQPWJn5V2Us=; b=zw55OJt2BihFiphDe/Z2gaV4hB6htx3vFjuaas04x2wh969T7ss4f8WBe4L+BlIMcb MqCzJDXESjd+BHZoCzjlz7ZTRPHopCv/LR2FokgewLycw+7AoN2yVZPjIW6phaxbWzRV xPKXU+ppWJjUkqCE5G0o1J/cft9HjISVF8++lmT2hZ7l+Iwj/ufg0F+3jsJRan0+PxIF RqT3UQKtj6LJcJ8phcyiiHqmkxQc4hq+j8AvxDMvIAODydcwLcY7Z189AfYZEcx97CuJ A3uBju3tVKA1+YfYeAAzdXlPZj6J7gjpI4dA0MDkk/Rqb3hD0UDnvGwBZrY/fQ7WPnm8 glQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656393212619100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 2 ++ target/arm/sme.decode | 1 + target/arm/sme_helper.c | 68 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 1 + 4 files changed, 72 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 1d68fb8c74..4d5d05db3a 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -121,6 +121,8 @@ DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) =20 +DEF_HELPER_FLAGS_7(sme_fmopa_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, diff --git a/target/arm/sme.decode b/target/arm/sme.decode index afd9c0dffd..e8d27fd8a0 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -75,3 +75,4 @@ FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. = @op_32 FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 =20 BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 +FMOPA_h 10000001 101 ..... ... ... ..... . 00 .. @op_32 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index d2e1057124..39d630a91c 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -978,6 +978,74 @@ static inline uint32_t f16mop_adj_pair(uint32_t pair, = uint32_t pg, uint32_t neg) return pair; } =20 +static float32 f16_dotadd(float32 sum, uint32_t e1, uint32_t e2, + float_status *s_std, float_status *s_odd) +{ + float64 e1r =3D float16_to_float64(e1 & 0xffff, true, s_std); + float64 e1c =3D float16_to_float64(e1 >> 16, true, s_std); + float64 e2r =3D float16_to_float64(e2 & 0xffff, true, s_std); + float64 e2c =3D float16_to_float64(e2 >> 16, true, s_std); + float64 t64; + float32 t32; + + /* + * The ARM pseudocode function FPDot performs both multiplies + * and the add with a single rounding operation. Emulate this + * by performing the first multiply in round-to-odd, then doing + * the second multiply as fused multiply-add, and rounding to + * float32 all in one step. + */ + t64 =3D float64_mul(e1r, e2r, s_odd); + t64 =3D float64r32_muladd(e1c, e2c, t64, 0, s_std); + + /* This conversion is exact, because we've already rounded. */ + t32 =3D float64_to_float32(t64, s_std); + + /* The final accumulation step is not fused. */ + return float32_add(sum, t32, s_std); +} + +void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, void *vst, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_maxsz(desc); + uint32_t neg =3D simd_data(desc) << 15; + uint16_t *pn =3D vpn, *pm =3D vpm; + float_status fpst_odd, fpst_std =3D *(float_status *)vst; + + set_default_nan_mode(true, &fpst_std); + fpst_odd =3D fpst_std; + set_float_rounding_mode(float_round_to_odd, &fpst_odd); + + for (row =3D 0; row < oprsz; ) { + uint16_t pa =3D pn[H2(row >> 4)]; + do { + void *vza_row =3D vza + row * sizeof(ARMVectorReg); + uint32_t n =3D *(uint32_t *)(vzn + row); + + n =3D f16mop_adj_pair(n, pa, neg); + + for (col =3D 0; col < oprsz; ) { + uint16_t pb =3D pm[H2(col >> 4)]; + do { + if ((pa & 0b0101) =3D=3D 0b0101 || (pb & 0b0101) =3D= =3D 0b0101) { + uint32_t *a =3D vza_row + col; + uint32_t m =3D *(uint32_t *)(vzm + col); + + m =3D f16mop_adj_pair(m, pb, neg); + *a =3D f16_dotadd(*a, n, m, &fpst_std, &fpst_odd); + + col +=3D 4; + pb >>=3D 4; + } + } while (col & 15); + } + row +=3D 4; + pa >>=3D 4; + } while (row & 15); + } +} + void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, void *vpm, uint32_t desc) { diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index e537a14b6d..0fcb33cb3f 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -358,6 +358,7 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a,= MemOp esz, return true; } =20 +TRANS_FEAT(FMOPA_h, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fm= opa_h) TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fm= opa_s) TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper= _sme_fmopa_d) =20 --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656391215962965.3910874005878; Mon, 27 Jun 2022 21:40:15 -0700 (PDT) Received: from localhost ([::1]:59450 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o631K-0003i7-To for importer@patchew.org; Tue, 28 Jun 2022 00:40:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37640) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62k9-0002O4-Q2 for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:30 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:43816) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62k7-0003og-G6 for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:29 -0400 Received: by mail-pj1-x1035.google.com with SMTP id dw10-20020a17090b094a00b001ed00a16eb4so11433741pjb.2 for ; Mon, 27 Jun 2022 21:22:27 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.22.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:22:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G5IR0e01IiLHM/qqXKrRTHY9/xhdp14OJQCAtI9uZ5k=; b=mCngACNDiUQ8ssyPQ+/NKGRQKh7OYHJQB25cRLPVIfRjgAptisUA6AD7afqsubUWHV ykOiQG8pWXmP56GqXFMdf0vQO8f36/1tpCOCYgJuEb+bMc0SOjEQn2Lj6VSrpnoerD2Y VFIYOkLSJdWTfsqZvwe3jc1KUDMz0l34Ob8pTQegz5E6WACfwsweU0gWlEaAEOCQLPHC 3gdTQdEWaNBni4cDfgaQOwlEtinOy6JuORlcqbJlkMx8Lep8shTcui4kAeQFm4MzXaZI /R9Hb0JsuPYNQNDT/tVZnzf1u19gYSiMTX+eGrcCh1HVpcG1b1cY05xs2Q9ZwZT+WRWC Pmrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G5IR0e01IiLHM/qqXKrRTHY9/xhdp14OJQCAtI9uZ5k=; b=6dfdRb/4BxxRvQGEbRXBmVKsmUwKbKNecraGGLJ8BjKHsuyj45S8yQxrdRFzYK6hRk vTihCiE3JPCQtKZMiDmKc6CCSlTe/rBH8usm7R7Ix/6VQ3L1rKZv4plhxePYCQD5ytIq SJ0qXy2HopLpkUpCQsegr31MT9yjB5q9dK3Uu2DzyMUam8LORdpTJWsY7DPPzDKP3D+R kYUbPwt7zUWFgg/7W1Ojsbi0Y2EZ5Sqng9XTG8w1nWW3tpOqdt6zRbZFEuNcYZi85JFP QGsQiQfn/6wumhuD3lK/+Oz1caTQXZVrFt9Um1pgJfV32mVX5tED5RMXzez9L2T0WSKE qmEA== X-Gm-Message-State: AJIora/odIlUqlxVs+STm2PwZYZn4vgLIBtepSIGJ9FAB+Rho4evF1FW Ig0k0KnMcvfnsBwlHt8Guv060Kb+7Rz09Q== X-Google-Smtp-Source: AGRyM1vNRVKGt2Sug3zA54tjOKzpoASxZpc/mIh1umHA9IS4s+HK9QUcb+qHxu3wBv5vx1iHaevi2A== X-Received: by 2002:a17:90b:3148:b0:1ed:75:47b with SMTP id ip8-20020a17090b314800b001ed0075047bmr19973660pjb.9.1656390146262; Mon, 27 Jun 2022 21:22:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v4 27/45] target/arm: Implement SME integer outer product Date: Tue, 28 Jun 2022 09:50:59 +0530 Message-Id: <20220628042117.368549-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656391216825100001 Content-Type: text/plain; charset="utf-8" This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 16 ++++++++ target/arm/sme.decode | 10 +++++ target/arm/sme_helper.c | 82 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 10 +++++ 4 files changed, 118 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 4d5d05db3a..d2d544a696 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -129,3 +129,19 @@ DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_smopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_umopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_sumopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_usmopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_smopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_umopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_sumopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_usmopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index e8d27fd8a0..628804e37a 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -76,3 +76,13 @@ FMOPA_d 10000000 110 ..... ... ... ..... . 0 ...= @op_64 =20 BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 FMOPA_h 10000001 101 ..... ... ... ..... . 00 .. @op_32 + +SMOPA_s 1010000 0 10 0 ..... ... ... ..... . 00 .. @op_32 +SUMOPA_s 1010000 0 10 1 ..... ... ... ..... . 00 .. @op_32 +USMOPA_s 1010000 1 10 0 ..... ... ... ..... . 00 .. @op_32 +UMOPA_s 1010000 1 10 1 ..... ... ... ..... . 00 .. @op_32 + +SMOPA_d 1010000 0 11 0 ..... ... ... ..... . 0 ... @op_64 +SUMOPA_d 1010000 0 11 1 ..... ... ... ..... . 0 ... @op_64 +USMOPA_d 1010000 1 11 0 ..... ... ... ..... . 0 ... @op_64 +UMOPA_d 1010000 1 11 1 ..... ... ... ..... . 0 ... @op_64 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 39d630a91c..e6204ab236 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -1081,3 +1081,85 @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *= vzm, void *vpn, } while (row & 15); } } + +typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool); + +static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm, + uint8_t *pn, uint8_t *pm, + uint32_t desc, IMOPFn *fn) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8; + bool neg =3D simd_data(desc); + + for (row =3D 0; row < oprsz; ++row) { + uint8_t pa =3D pn[H1(row)]; + uint64_t *za_row =3D &za[row * sizeof(ARMVectorReg)]; + uint64_t n =3D zn[row]; + + for (col =3D 0; col < oprsz; ++col) { + uint8_t pb =3D pm[H1(col)]; + uint64_t *a =3D &za_row[col]; + + *a =3D fn(n, zm[col], *a, pa & pb, neg); + } + } +} + +#define DEF_IMOP_32(NAME, NTYPE, MTYPE) \ +static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool n= eg) \ +{ = \ + uint32_t sum0 =3D 0, sum1 =3D 0; = \ + /* Apply P to N as a mask, making the inactive elements 0. */ = \ + n &=3D expand_pred_b(p); = \ + sum0 +=3D (NTYPE)(n >> 0) * (MTYPE)(m >> 0); = \ + sum0 +=3D (NTYPE)(n >> 8) * (MTYPE)(m >> 8); = \ + sum0 +=3D (NTYPE)(n >> 16) * (MTYPE)(m >> 16); = \ + sum0 +=3D (NTYPE)(n >> 24) * (MTYPE)(m >> 24); = \ + sum1 +=3D (NTYPE)(n >> 32) * (MTYPE)(m >> 32); = \ + sum1 +=3D (NTYPE)(n >> 40) * (MTYPE)(m >> 40); = \ + sum1 +=3D (NTYPE)(n >> 48) * (MTYPE)(m >> 48); = \ + sum1 +=3D (NTYPE)(n >> 56) * (MTYPE)(m >> 56); = \ + if (neg) { = \ + sum0 =3D (uint32_t)a - sum0, sum1 =3D (uint32_t)(a >> 32) - sum1; = \ + } else { = \ + sum0 =3D (uint32_t)a + sum0, sum1 =3D (uint32_t)(a >> 32) + sum1; = \ + } = \ + return ((uint64_t)sum1 << 32) | sum0; = \ +} + +#define DEF_IMOP_64(NAME, NTYPE, MTYPE) \ +static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool n= eg) \ +{ = \ + uint64_t sum =3D 0; = \ + /* Apply P to N as a mask, making the inactive elements 0. */ = \ + n &=3D expand_pred_h(p); = \ + sum +=3D (NTYPE)(n >> 0) * (MTYPE)(m >> 0); = \ + sum +=3D (NTYPE)(n >> 16) * (MTYPE)(m >> 16); = \ + sum +=3D (NTYPE)(n >> 32) * (MTYPE)(m >> 32); = \ + sum +=3D (NTYPE)(n >> 48) * (MTYPE)(m >> 48); = \ + return neg ? a - sum : a + sum; = \ +} + +DEF_IMOP_32(smopa_s, int8_t, int8_t) +DEF_IMOP_32(umopa_s, uint8_t, uint8_t) +DEF_IMOP_32(sumopa_s, int8_t, uint8_t) +DEF_IMOP_32(usmopa_s, uint8_t, int8_t) + +DEF_IMOP_64(smopa_d, int16_t, int16_t) +DEF_IMOP_64(umopa_d, uint16_t, uint16_t) +DEF_IMOP_64(sumopa_d, int16_t, uint16_t) +DEF_IMOP_64(usmopa_d, uint16_t, int16_t) + +#define DEF_IMOPH(NAME) \ + void HELPER(sme_##NAME)(void *vza, void *vzn, void *vzm, void *vpn, = \ + void *vpm, uint32_t desc) = \ + { do_imopa(vza, vzn, vzm, vpn, vpm, desc, NAME); } + +DEF_IMOPH(smopa_s) +DEF_IMOPH(umopa_s) +DEF_IMOPH(sumopa_s) +DEF_IMOPH(usmopa_s) +DEF_IMOPH(smopa_d) +DEF_IMOPH(umopa_d) +DEF_IMOPH(sumopa_d) +DEF_IMOPH(usmopa_d) diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 0fcb33cb3f..876184e8bd 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -364,3 +364,13 @@ TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, = a, MO_64, gen_helper_sme_f =20 /* TODO: FEAT_EBF16 */ TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa) + +TRANS_FEAT(SMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_smopa_s) +TRANS_FEAT(UMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_umopa_s) +TRANS_FEAT(SUMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_sumopa= _s) +TRANS_FEAT(USMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_usmopa= _s) + +TRANS_FEAT(SMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_= smopa_d) +TRANS_FEAT(UMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_= umopa_d) +TRANS_FEAT(SUMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme= _sumopa_d) +TRANS_FEAT(USMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme= _usmopa_d) --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656392192662802.336694846596; Mon, 27 Jun 2022 21:56:32 -0700 (PDT) Received: from localhost ([::1]:40054 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o63H5-0004PE-A1 for importer@patchew.org; Tue, 28 Jun 2022 00:56:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37674) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62kC-0002Ue-BT for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:32 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:33484) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62kA-0003qi-IV for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:32 -0400 Received: by mail-pj1-x102c.google.com with SMTP id i8-20020a17090aee8800b001ecc929d14dso11525957pjz.0 for ; Mon, 27 Jun 2022 21:22:30 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.22.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:22:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ez0Fk7Hr9AjzIaIFm6v2h/vIMvDr735Y3UJNyri/gRQ=; b=RJ709bJIs5pr81ybVBoxZT/foZ+BocgHKt9H8pmIc+jZutM+g8rmaGuH+gbbGchlPY JM5K+kN2owAwNIJ4AnTf1goJzLJCG5Qwe/KrtRcKxGsdRHWVdse6cHby9LPmAQIHe/0J H3T2r8WnRZyIiRu59pGC0JXd4lBMwhRXTKS3VerGflxK0ovALOfiKGvVAaqHjnvNwaSt D5jenUA7Bx+XbnmAbVFCrmqyijj+QEibOrgn5trwBJriAKi8y3Ky6X5cMb9mBfGN4Ctk uRaFbj+DfCt3R/IYtYZoQRktzHAUKXHshzDoDdkeD5E1F+/MrNemr03Do0KBnCO4t2KY fhZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ez0Fk7Hr9AjzIaIFm6v2h/vIMvDr735Y3UJNyri/gRQ=; b=io+RTZppaF1gaIlv3U4FAgJahMCYKbiJ7Yk43c6ZT9aENQkt13CUo4/W/YZyYuWiBc hwUEYysz8mLRl8rzu/pAGn9PaZzEYVH7mj3692aAtUd88wphDJvj38HcGYqWka3l0+oN BBq1xcIJTMKqY9UMVXvmnva2qPodCaEqk/Pa3PY5Wo5mrGevoNSedPysxY1T1xAJlKNw rXMJvbZlGKa4VsBq47q1r2N5EZ5ivLwlXrCxnjL7nyV7uW/iggfeM+J/twgXbh4gI5qz 3vof6wU5jk/ilEOw2e31Ssq53GSdRxHAFGB/1VOsLrbr3AKkuR9pVe3w5yvOND25MJtk V03w== X-Gm-Message-State: AJIora+0pMImvNBiIPeMZYtZVlseD27Mnlb4XxJBY2zJYj1hJO5HLevQ EqH004E4fnIkgleJ4S/w2wf74ED55poYEQ== X-Google-Smtp-Source: AGRyM1svZdWY2pcB2JATwd90svpmwtm+rhAVkzo+/7Pm5AiGUYwIYVLy0w1YgAPTZLVcAkzpJckN8w== X-Received: by 2002:a17:90b:35c7:b0:1ee:f8a7:2b03 with SMTP id nb7-20020a17090b35c700b001eef8a72b03mr3530096pjb.50.1656390149020; Mon, 27 Jun 2022 21:22:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v4 28/45] target/arm: Implement PSEL Date: Tue, 28 Jun 2022 09:51:00 +0530 Message-Id: <20220628042117.368549-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656392193379100001 Content-Type: text/plain; charset="utf-8" This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve.decode | 20 +++++++++++++ target/arm/translate-sve.c | 57 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 95af08c139..966803cbb7 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1674,3 +1674,23 @@ BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ...= .. @rrxr_3a esz=3D2 =20 ### SVE2 floating-point bfloat16 dot-product (indexed) BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=3D2 + +### SVE broadcast predicate element + +&psel esz pd pn pm rv imm +%psel_rv 16:2 !function=3Dplus_12 +%psel_imm_b 22:2 19:2 +%psel_imm_h 22:2 20:1 +%psel_imm_s 22:2 +%psel_imm_d 23:1 +@psel ........ .. . ... .. .. pn:4 . pm:4 . pd:4 \ + &psel rv=3D%psel_rv + +PSEL 00100101 .. 1 ..1 .. 01 .... 0 .... 0 .... \ + @psel esz=3D0 imm=3D%psel_imm_b +PSEL 00100101 .. 1 .10 .. 01 .... 0 .... 0 .... \ + @psel esz=3D1 imm=3D%psel_imm_h +PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \ + @psel esz=3D2 imm=3D%psel_imm_s +PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ + @psel esz=3D3 imm=3D%psel_imm_d diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 374a0a87f2..23b051746c 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7415,3 +7415,60 @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr= _esz *a, bool sel) =20 TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false) TRANS_FEAT(BFMLALT_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, true) + +static bool trans_PSEL(DisasContext *s, arg_psel *a) +{ + int vl =3D vec_full_reg_size(s); + int pl =3D pred_gvec_reg_size(s); + int elements =3D vl >> a->esz; + TCGv_i64 tmp, didx, dbit; + TCGv_ptr ptr; + + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (!sve_access_check(s)) { + return true; + } + + tmp =3D tcg_temp_new_i64(); + dbit =3D tcg_temp_new_i64(); + didx =3D tcg_temp_new_i64(); + ptr =3D tcg_temp_new_ptr(); + + /* Compute the predicate element. */ + tcg_gen_addi_i64(tmp, cpu_reg(s, a->rv), a->imm); + if (is_power_of_2(elements)) { + tcg_gen_andi_i64(tmp, tmp, elements - 1); + } else { + tcg_gen_remu_i64(tmp, tmp, tcg_constant_i64(elements)); + } + + /* Extract the predicate byte and bit indices. */ + tcg_gen_shli_i64(tmp, tmp, a->esz); + tcg_gen_andi_i64(dbit, tmp, 7); + tcg_gen_shri_i64(didx, tmp, 3); + if (HOST_BIG_ENDIAN) { + tcg_gen_xori_i64(didx, didx, 7); + } + + /* Load the predicate word. */ + tcg_gen_trunc_i64_ptr(ptr, didx); + tcg_gen_add_ptr(ptr, ptr, cpu_env); + tcg_gen_ld8u_i64(tmp, ptr, pred_full_reg_offset(s, a->pm)); + + /* Extract the predicate bit and replicate to MO_64. */ + tcg_gen_shr_i64(tmp, tmp, dbit); + tcg_gen_andi_i64(tmp, tmp, 1); + tcg_gen_neg_i64(tmp, tmp); + + /* Apply to either copy the source, or write zeros. */ + tcg_gen_gvec_ands(MO_64, pred_full_reg_offset(s, a->pd), + pred_full_reg_offset(s, a->pn), tmp, pl, pl); + + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(dbit); + tcg_temp_free_i64(didx); + tcg_temp_free_ptr(ptr); + return true; +} --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656391818084119.84626006015208; Mon, 27 Jun 2022 21:50:18 -0700 (PDT) Received: from localhost ([::1]:52060 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o63B1-0001d8-8F for importer@patchew.org; Tue, 28 Jun 2022 00:50:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37720) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62kG-0002dH-56 for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:36 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:34579) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62kD-0003sK-0X for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:35 -0400 Received: by mail-pf1-x42d.google.com with SMTP id t21so10912724pfq.1 for ; Mon, 27 Jun 2022 21:22:32 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.22.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:22:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=28vgYGphhmuIGOQ3NR6EcTiIP3DBoLZHG9GLZrK4ZGk=; b=VnZAVHZ0nNzEow/Pq92Ft6c66/PHkHX6Yr59H/uaKZMxAYfn/xmCjPvq9MnLA48IK/ 2WTppk4Yet52+E3BI71b+aNSyPvSUC05yO8feWzvbX8MMPYIU/lwf/58X3Yn60fQfiyZ VsZEbp4iBjbm82oPf7mYplCaDZnh52iOgUTX9aetUlWiv3LaK05dz2KQMr3HFFz2Kzch sPA76ycy56+lB0ZL3nTBi7E/0w346FRm4yIAdFQ1ufDJjh6NxefDkzfny48brxtcgrgQ v0e5pynldBIlIVtRyCscEU+tqwoK5+WSvcuxzxwFj3JPSz1bDiTEAG6gtlmqp18o/676 p7Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=28vgYGphhmuIGOQ3NR6EcTiIP3DBoLZHG9GLZrK4ZGk=; b=Yszu2j7+IT1VDO/yHe7CVpvEtPHoVOAESau642NZnX7BFq0QqKkMSTtwNp2xYk/IHg sGR6uckyXd6RGT9oqDPSO9Xg5qohCau9+oGRxfqcV01FxPqznz16NNjMq/hh/jWw4hnn fS/peeYO6oV6aOWnefsMkx8n8dN4tvgSRYQfOrG3/jltxBdtf3T9bRHR/ARuxGHhBEz2 D1MNzU7Njk+PTZc+WtxOrXdOWD6gCIC2ARYfEQfRbcCcmCo4FC+dH8Qmv4CVff3q4pZX UEqzaaRxDErzLUyIBZVsYfCJLDKhrUs82+TSgTUrEHgnXLr73jeKAHtVXZqdn12OsbRJ ufxg== X-Gm-Message-State: AJIora9ZzdW7lGI2Guy073Kr0T2RIo/Ww+2K9rBV1oD5FtVfqbBIo5/2 X2jprt77xbVKaQ4WTu86wf4zc7NYs+462w== X-Google-Smtp-Source: AGRyM1sOq7FaI7Sl1bRB8eFErreB/EL5XyiF0QyCdR3+zrqD5pmyyMhmV1TOmymz2Bj0HGV4iTw7yg== X-Received: by 2002:a05:6a00:8c5:b0:510:6eae:6fa1 with SMTP id s5-20020a056a0008c500b005106eae6fa1mr1639483pfu.12.1656390151606; Mon, 27 Jun 2022 21:22:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v4 29/45] target/arm: Implement REVD Date: Tue, 28 Jun 2022 09:51:01 +0530 Message-Id: <20220628042117.368549-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656391820107100001 Content-Type: text/plain; charset="utf-8" This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 2 ++ target/arm/sve.decode | 1 + target/arm/sve_helper.c | 16 ++++++++++++++++ target/arm/translate-sve.c | 2 ++ 4 files changed, 21 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index ab0333400f..cc4e1d8948 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -719,6 +719,8 @@ DEF_HELPER_FLAGS_4(sve_revh_d, TCG_CALL_NO_RWG, void, p= tr, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_4(sve_revw_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(sme_revd_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(sve_rbit_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_rbit_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_rbit_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 966803cbb7..a9e48f07b4 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -652,6 +652,7 @@ REVB 00000101 .. 1001 00 100 ... ..... .....= @rd_pg_rn REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn +REVD 00000101 00 1011 10 100 ... ..... ..... @rd_pg_rn_= e0 =20 # SVE vector splice (predicated, destructive) SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 9a26f253e0..5de82696b5 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -931,6 +931,22 @@ DO_ZPZ_D(sve_revh_d, uint64_t, hswap64) =20 DO_ZPZ_D(sve_revw_d, uint64_t, wswap64) =20 +void HELPER(sme_revd_q)(void *vd, void *vn, void *vg, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd, *n =3D vn; + uint8_t *pg =3D vg; + + for (i =3D 0; i < opr_sz; i +=3D 2) { + if (pg[H1(i)] & 1) { + uint64_t n0 =3D n[i + 0]; + uint64_t n1 =3D n[i + 1]; + d[i + 0] =3D n1; + d[i + 1] =3D n0; + } + } +} + DO_ZPZ(sve_rbit_b, uint8_t, H1, revbit8) DO_ZPZ(sve_rbit_h, uint16_t, H1_2, revbit16) DO_ZPZ(sve_rbit_s, uint32_t, H1_4, revbit32) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 23b051746c..6019dfb53c 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -2901,6 +2901,8 @@ TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh= _fns[a->esz], a, 0) TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz, a->esz =3D=3D 3 ? gen_helper_sve_revw_d : NULL, a, 0) =20 +TRANS_FEAT(REVD, aa64_sme, gen_gvec_ool_arg_zpz, gen_helper_sme_revd_q, a,= 0) + TRANS_FEAT(SPLICE, aa64_sve, gen_gvec_ool_arg_zpzz, gen_helper_sve_splice, a, a->esz) =20 --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656391994172602.5574054980191; Mon, 27 Jun 2022 21:53:14 -0700 (PDT) Received: from localhost ([::1]:60414 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o63Dt-0007RQ-4I for importer@patchew.org; Tue, 28 Jun 2022 00:53:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37750) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62kH-0002f7-TQ for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:37 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:40811) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62kF-0003u4-EY for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:37 -0400 Received: by mail-pg1-x533.google.com with SMTP id 9so11011231pgd.7 for ; Mon, 27 Jun 2022 21:22:34 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.22.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:22:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NUdz7FhxT+a1aI5GTd9ofqruaMOFmsTTrFvfE9J6oVU=; b=Sd/GnZ93K/HtstLOp/KZkTczc4+cprBHmD64TQmME/WDo09wRMjVBPyH/O7U9S7QF+ PjhvJXJ1cbFSC02ozzp0bYj9Ph6Mb7ZYkETSEah6uNdE+KABN2lWtniYoJlcXvDJ/TBP Hb5fzin3jJpTnkAM3MP9jwAJsELUaPXUsKnJ+rxPRUjLUBqQD7cYEHRjph/9o12rWH6a bUUk2cQpdzgEU7L+TGkB7T2aJM8r03fPjX3Bw1P0aHAFEfFpgbn5CLNUdpeOVk5QoU0X gUNyMtjAUXPywC9FVcYqdGbF5EMZ4Wes4tYZFuPL9xh8ORpNPAeTthWVtWfcS0aqDa80 73dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NUdz7FhxT+a1aI5GTd9ofqruaMOFmsTTrFvfE9J6oVU=; b=neW+gSzbhzAHfe5sFqa1dWfDJYgM1/YLoHOTdQAol72yy8AHoiZqkTV8L3IFZY2RfL ssikVU8/JjNI/jxObuDCh70sOfZzTiX39Srz8uddaztVBf2nfCI6ZUa6/dUz79o5gCjZ cg6eLnFPvnARVdBidTL2Sx7dIliLqE+K0wwuSfTCzHhAfWtrgpzuUVu3S+juGDGPggHs Z0QX2zNsSJ0mrI3Q87r+XGispo61bMcA7DNg7pUrPyVy2SRkWSErTxcHdNvHgkP+eunU RyfVcxwZiu6dfLGwT+2fHlYB2I4ct2u2WRPxQKm2+0/rum0nQdixgmWj4eKjS7cE+Y3o bn6g== X-Gm-Message-State: AJIora89rSDrAwzyREz4DKTPOoJY+sNILCSE2If9Ut8GskVwNCakHy/F qhNISIzTVRQMM4kWX6nQ9juf5/cTTcoUfA== X-Google-Smtp-Source: AGRyM1tKf/IiwmVoQ2sW0CKVg4/53o/5e5i7tOptB7hu6vsOYtSMSAXDtclGvcCLJx5iovEqxrOrUA== X-Received: by 2002:a63:d949:0:b0:408:870f:70d1 with SMTP id e9-20020a63d949000000b00408870f70d1mr15741304pgj.620.1656390154060; Mon, 27 Jun 2022 21:22:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v4 30/45] target/arm: Implement SCLAMP, UCLAMP Date: Tue, 28 Jun 2022 09:51:02 +0530 Message-Id: <20220628042117.368549-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656391994484100001 Content-Type: text/plain; charset="utf-8" This is an SVE instruction that operates using the SVE vector length but that it is present only if SME is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.h | 18 +++++++ target/arm/sve.decode | 5 ++ target/arm/translate-sve.c | 102 +++++++++++++++++++++++++++++++++++++ target/arm/vec_helper.c | 24 +++++++++ 4 files changed, 149 insertions(+) diff --git a/target/arm/helper.h b/target/arm/helper.h index 3a8ce42ab0..92f36d9dbb 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1019,6 +1019,24 @@ DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_uclamp_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a9e48f07b4..14b3a69c36 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1695,3 +1695,8 @@ PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0= .... \ @psel esz=3D2 imm=3D%psel_imm_s PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ @psel esz=3D3 imm=3D%psel_imm_d + +### SVE clamp + +SCLAMP 01000100 .. 0 ..... 110000 ..... ..... @rda_rn_rm +UCLAMP 01000100 .. 0 ..... 110001 ..... ..... @rda_rn_rm diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 6019dfb53c..2eb9844cda 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7474,3 +7474,105 @@ static bool trans_PSEL(DisasContext *s, arg_psel *a) tcg_temp_free_ptr(ptr); return true; } + +static void gen_sclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a) +{ + tcg_gen_smax_i32(d, a, n); + tcg_gen_smin_i32(d, d, m); +} + +static void gen_sclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a) +{ + tcg_gen_smax_i64(d, a, n); + tcg_gen_smin_i64(d, d, m); +} + +static void gen_sclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n, + TCGv_vec m, TCGv_vec a) +{ + tcg_gen_smax_vec(vece, d, a, n); + tcg_gen_smin_vec(vece, d, d, m); +} + +static void gen_sclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m, + uint32_t a, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop[] =3D { + INDEX_op_smin_vec, INDEX_op_smax_vec, 0 + }; + static const GVecGen4 ops[4] =3D { + { .fniv =3D gen_sclamp_vec, + .fno =3D gen_helper_gvec_sclamp_b, + .opt_opc =3D vecop, + .vece =3D MO_8 }, + { .fniv =3D gen_sclamp_vec, + .fno =3D gen_helper_gvec_sclamp_h, + .opt_opc =3D vecop, + .vece =3D MO_16 }, + { .fni4 =3D gen_sclamp_i32, + .fniv =3D gen_sclamp_vec, + .fno =3D gen_helper_gvec_sclamp_s, + .opt_opc =3D vecop, + .vece =3D MO_32 }, + { .fni8 =3D gen_sclamp_i64, + .fniv =3D gen_sclamp_vec, + .fno =3D gen_helper_gvec_sclamp_d, + .opt_opc =3D vecop, + .vece =3D MO_64, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64 } + }; + tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]); +} + +TRANS_FEAT(SCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_sclamp, a) + +static void gen_uclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a) +{ + tcg_gen_umax_i32(d, a, n); + tcg_gen_umin_i32(d, d, m); +} + +static void gen_uclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a) +{ + tcg_gen_umax_i64(d, a, n); + tcg_gen_umin_i64(d, d, m); +} + +static void gen_uclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n, + TCGv_vec m, TCGv_vec a) +{ + tcg_gen_umax_vec(vece, d, a, n); + tcg_gen_umin_vec(vece, d, d, m); +} + +static void gen_uclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m, + uint32_t a, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop[] =3D { + INDEX_op_umin_vec, INDEX_op_umax_vec, 0 + }; + static const GVecGen4 ops[4] =3D { + { .fniv =3D gen_uclamp_vec, + .fno =3D gen_helper_gvec_uclamp_b, + .opt_opc =3D vecop, + .vece =3D MO_8 }, + { .fniv =3D gen_uclamp_vec, + .fno =3D gen_helper_gvec_uclamp_h, + .opt_opc =3D vecop, + .vece =3D MO_16 }, + { .fni4 =3D gen_uclamp_i32, + .fniv =3D gen_uclamp_vec, + .fno =3D gen_helper_gvec_uclamp_s, + .opt_opc =3D vecop, + .vece =3D MO_32 }, + { .fni8 =3D gen_uclamp_i64, + .fniv =3D gen_uclamp_vec, + .fno =3D gen_helper_gvec_uclamp_d, + .opt_opc =3D vecop, + .vece =3D MO_64, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64 } + }; + tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]); +} + +TRANS_FEAT(UCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_uclamp, a) diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 9a9c034e36..f59d3b26ea 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -2690,3 +2690,27 @@ void HELPER(gvec_bfmlal_idx)(void *vd, void *vn, voi= d *vm, } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +#define DO_CLAMP(NAME, TYPE) \ +void HELPER(NAME)(void *d, void *n, void *m, void *a, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc); \ + for (i =3D 0; i < opr_sz; i +=3D sizeof(TYPE)) { = \ + TYPE aa =3D *(TYPE *)(a + i); \ + TYPE nn =3D *(TYPE *)(n + i); \ + TYPE mm =3D *(TYPE *)(m + i); \ + TYPE dd =3D MIN(MAX(aa, nn), mm); \ + *(TYPE *)(d + i) =3D dd; \ + } \ + clear_tail(d, opr_sz, simd_maxsz(desc)); \ +} + +DO_CLAMP(gvec_sclamp_b, int8_t) +DO_CLAMP(gvec_sclamp_h, int16_t) +DO_CLAMP(gvec_sclamp_s, int32_t) +DO_CLAMP(gvec_sclamp_d, int64_t) + +DO_CLAMP(gvec_uclamp_b, uint8_t) +DO_CLAMP(gvec_uclamp_h, uint16_t) +DO_CLAMP(gvec_uclamp_s, uint32_t) +DO_CLAMP(gvec_uclamp_d, uint64_t) --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.22.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:22:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QMHowAe2qqOcR59WIhFIt7ar7qrWdpcyRnVo7s79wDU=; b=M2VRsroE7qD9F2EoJaW/fOsPoy0uGgP2yzBaCecTaKYiZeb1uKLOyWq+O2N79SzT01 h8Y/lvnnHHKqayXwDmceSGXdMmILMvadNTRZYWZa00Bv/HhkMSunNidW0HHjXk7cyt2d JeolNr/+F9hndx5bMvMP8VcmDAPm6EJOkhpi0JOCz/iDQ3SjXsTdWThDJQX70ajT41CE b+lVy9BBkKv7FY4M6ykXMTOj7tziQbPnTdF/FUmi8j3+qXXD4iIN4sVOAtMOtb/ncDlU CkIgjMJ4TYyyka0eYyV5vGyRPgNDDp6Pni9zPOi3kLYCalDgdZ1XNwlrCoxRA4VmMUkw 4OVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QMHowAe2qqOcR59WIhFIt7ar7qrWdpcyRnVo7s79wDU=; b=opKi8w+bwQlJgJxyhRNR+3cOnavBAyIQdKTvgCgyBK7IePEDFV11AZ0ZZWBjXc8ChU apAhu58fQdgz2rQYchUR/NXERoFZuVQ9TV6xc/PurP+vL58y49j3+z6wLFmvAasFAO7Y 7OfbdvgC3dPm49RXz1Jvz2w0MWbipeIiEAd7dmKygMtjE1tED6Wcj6NE1CVJWG8RbewP 8nRoC67vXja6Gs5EqUqIv0OQXFvKoE7gCZoU543GwMbth1RfGq3RxVYX1o8fd0Mlrmna NgOh/5jYVWVK+v1nPlUzc03bUvd+yA00AgDxGedNE5zvVjBgkvZGPm9rmcZNfASwvMOq 8fxA== X-Gm-Message-State: AJIora+nFDjGwrTdJsz4cZctJcWBwyfQVoWGcQ7zTQ4tA/nvYzBCzgDl KlYrL3z2MTXK5mFj+g6B/5SSOSLhIbm1LQ== X-Google-Smtp-Source: AGRyM1uvCtRhgncLYqYeVyt2/WxXR+3MjEV6++hnIq23Q4SbKY3dsKy27y/ipQ6T8Qt0ckq5DGDzaA== X-Received: by 2002:a63:7a49:0:b0:40c:ca38:aed7 with SMTP id j9-20020a637a49000000b0040cca38aed7mr15981612pgn.11.1656390156422; Mon, 27 Jun 2022 21:22:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v4 31/45] target/arm: Reset streaming sve state on exception boundaries Date: Tue, 28 Jun 2022 09:51:03 +0530 Message-Id: <20220628042117.368549-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656392466716100001 Content-Type: text/plain; charset="utf-8" We can handle both exception entry and exception return by hooking into aarch64_sve_change_el. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 976e414eda..2dc1f95c6d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11754,6 +11754,19 @@ void aarch64_sve_change_el(CPUARMState *env, int o= ld_el, return; } =20 + old_a64 =3D old_el ? arm_el_is_aa64(env, old_el) : el0_a64; + new_a64 =3D new_el ? arm_el_is_aa64(env, new_el) : el0_a64; + + /* + * Both AArch64.TakeException and AArch64.ExceptionReturn + * invoke ResetSVEState when taking an exception from, or + * returning to, AArch32 state when PSTATE.SM is enabled. + */ + if (old_a64 !=3D new_a64 && FIELD_EX64(env->svcr, SVCR, SM)) { + arm_reset_sve_state(env); + return; + } + /* * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped * at ELx, or not available because the EL is in AArch32 state, then @@ -11766,10 +11779,8 @@ void aarch64_sve_change_el(CPUARMState *env, int o= ld_el, * we already have the correct register contents when encountering the * vq0->vq0 transition between EL0->EL1. */ - old_a64 =3D old_el ? arm_el_is_aa64(env, old_el) : el0_a64; old_len =3D (old_a64 && !sve_exception_el(env, old_el) ? sve_vqm1_for_el(env, old_el) : 0); - new_a64 =3D new_el ? arm_el_is_aa64(env, new_el) : el0_a64; new_len =3D (new_a64 && !sve_exception_el(env, new_el) ? sve_vqm1_for_el(env, new_el) : 0); =20 --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656393517223470.28359313871954; Mon, 27 Jun 2022 22:18:37 -0700 (PDT) Received: from localhost ([::1]:47630 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o63cR-0004ii-1W for importer@patchew.org; Tue, 28 Jun 2022 01:18:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37830) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62kO-0002nJ-Hz for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:45 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:35426) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62kK-0003vZ-Th for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:42 -0400 Received: by mail-pf1-x433.google.com with SMTP id x4so10915804pfq.2 for ; Mon, 27 Jun 2022 21:22:40 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.22.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:22:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=asVIVIoowKUhkyzxDq1stWKniA6O4cXXCtHWZbtFt2Q=; b=Ao/eB+e5FFFqh27hPkQrx/LIlq2Ca6tVIwX7ae33mY84ib+/BsB1Xqe4wcLVr6DjE2 fSJwZBkjhjr29nzvBbhGKerDEOkRX8QO3QEOviE+kIsLn2X3pORH6L2COpe9PRn60KNf Ivqc1ZTSj9pGnpNNiqOHWckSddaKyvAVSI4lGxlRpY2Arg/I/AkEtOYFlYLWB7NxmUHZ frucMkKKqpHodFrQ9ePW57H3x8wGEOr8EGpbF7NSkNbvUtFLXL+JDBis4Zl3d5Mjgh0o puyeOFOTvqY7iq+5iMKe3PHMLXY6GxFPGtTNpP6ne1+U3eCzThTxvI1OaztodgumU0vM M9/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=asVIVIoowKUhkyzxDq1stWKniA6O4cXXCtHWZbtFt2Q=; b=NvWBdaUh3I0Lk2KIfbrsnVWspOtb6fMO6n6j9jrWo311Sa58Umiy099X+ulWu/6Nxl 8cLzaG61//g49VJx6oIC2cEFXasOowXwoe9O07RPeWmoFWgRKW23yBvi6A4iC1X4ZtbQ npJ4btcn47pNyds4KQx3ZRjIAcS20u3zXR+W8n6k2nxu1akpRql25dXpxgJdp5trhBS0 cdwBKXnB2XT6oWHK0UKltqAF7u/zRJjlGMLnKcsL4vl3hRVDnqCJh2/uEiXsyD70jH1e 4iFBb2q0IwggwiRU2MoeLOJVC3Ww04IPwWgM1hHoFGE5rK1FZpOA0HN6JRyGC0vAwRl8 Qlbw== X-Gm-Message-State: AJIora+YkJPWJTCzGhfrLDwctYhBpGY0Bf/HIqAM7u41KGB3u2VtSxpc vTI8iM1NnS2+YNxUavUPDytuLvJZFHpgEQ== X-Google-Smtp-Source: AGRyM1tafMU8PaLVUf8kM2QudlO1Y6YK9Ti+lQtut2tr9Khc2d1XFnKexofIvPp14bBMpHoR2f9Wlg== X-Received: by 2002:aa7:90c4:0:b0:521:2cd6:bd3e with SMTP id k4-20020aa790c4000000b005212cd6bd3emr2659317pfk.19.1656390159201; Mon, 27 Jun 2022 21:22:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v4 32/45] target/arm: Enable SME for -cpu max Date: Tue, 28 Jun 2022 09:51:04 +0530 Message-Id: <20220628042117.368549-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656393518762100001 Content-Type: text/plain; charset="utf-8" Note that SME remains effectively disabled for user-only, because we do not yet set CPACR_EL1.SMEN. This needs to wait until the kernel ABI is implemented. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 4 ++++ target/arm/cpu64.c | 11 +++++++++++ 2 files changed, 15 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 83b4410065..8e494c8bea 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -65,6 +65,10 @@ the following architecture extensions: - FEAT_SHA512 (Advanced SIMD SHA512 instructions) - FEAT_SM3 (Advanced SIMD SM3 instructions) - FEAT_SM4 (Advanced SIMD SM4 instructions) +- FEAT_SME (Scalable Matrix Extension) +- FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode) +- FEAT_SME_F64F64 (Double-precision floating-point outer product instructi= ons) +- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instruc= tions) - FEAT_SPECRES (Speculation restriction instructions) - FEAT_SSBS (Speculative Store Bypass Safe) - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 19188d6cc2..40a0f043d0 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1018,6 +1018,7 @@ static void aarch64_max_initfn(Object *obj) */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ t =3D FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT= _DoubleFault */ + t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr1 =3D t; =20 @@ -1068,6 +1069,16 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 + t =3D cpu->isar.id_aa64smfr0; + t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ + cpu->isar.id_aa64smfr0 =3D t; + /* Replicate the same data to the 32-bit id registers. */ aa32_max_features(cpu); =20 --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656392207566448.4849146278631; Mon, 27 Jun 2022 21:56:47 -0700 (PDT) Received: from localhost ([::1]:40906 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o63HJ-0004y4-HQ for importer@patchew.org; Tue, 28 Jun 2022 00:56:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37882) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62kR-0002om-C2 for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:47 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:46612) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62kO-0003vl-Fs for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:46 -0400 Received: by mail-pl1-x62c.google.com with SMTP id q18so9948866pld.13 for ; Mon, 27 Jun 2022 21:22:42 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656392209412100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/aarch64/target_cpu.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cp= u.h index 97a477bd3e..f90359faf2 100644 --- a/linux-user/aarch64/target_cpu.h +++ b/linux-user/aarch64/target_cpu.h @@ -34,10 +34,13 @@ static inline void cpu_clone_regs_parent(CPUARMState *e= nv, unsigned flags) =20 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) { - /* Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is + /* + * Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is * different from AArch32 Linux, which uses TPIDRRO. */ env->cp15.tpidr_el[0] =3D newtls; + /* TPIDR2_EL0 is cleared with CLONE_SETTLS. */ + env->cp15.tpidr2_el0 =3D 0; } =20 static inline abi_ulong get_sp_from_cpustate(CPUARMState *state) --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656393870692131.5325649373034; Mon, 27 Jun 2022 22:24:30 -0700 (PDT) Received: from localhost ([::1]:57230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o63i9-0003CL-Ej for importer@patchew.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656393871695100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/aarch64/cpu_loop.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 3b273f6299..4af6996d57 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -89,6 +89,15 @@ void cpu_loop(CPUARMState *env) =20 switch (trapnr) { case EXCP_SWI: + /* + * On syscall, PSTATE.ZA is preserved, along with the ZA matri= x. + * PSTATE.SM is cleared, per SMSTOP, which does ResetSVEState. + */ + if (FIELD_EX64(env->svcr, SVCR, SM)) { + env->svcr =3D FIELD_DP64(env->svcr, SVCR, SM, 0); + arm_rebuild_hflags(env); + arm_reset_sve_state(env); + } ret =3D do_syscall(env, env->xregs[8], env->xregs[0], --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656394297433327.61936070938805; Mon, 27 Jun 2022 22:31:37 -0700 (PDT) Received: from localhost ([::1]:39982 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o63p2-0002Xm-8G for importer@patchew.org; Tue, 28 Jun 2022 01:31:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37924) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62kV-0002pz-GH for qemu-devel@nongnu.org; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.22.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:22:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FjmC/46ARakxFpcFGMLJHjfrHdRZ+a4Hi4clf4uxgwU=; b=hBs/391mBUNXZXJVaDcIN3yFJeRFk6nzxqb9FprRy/Bg1FKtqoP++ezU6gfp8I934n SHEwCnKqHjJzt3KNjcqUMnwDU9I2quv2mlRoBHAbRwmMctvAuJhJFqKB5NJeCUQYFo40 jj4zio/zX1UKxXgN3UAVC+PV4zzmXC9xT3AtojprgyHuf0yxkBmNCv57S/rpGxyFo4bd MwR/QssPvrTvpb9LoGeGGKzlXllYtcKeDKCj6PTPpBB0T34jLP4LKQOT7ogOp70hSxJP YA/moE9Ocei8SHogqZiJCPeSY+vGl7t8gI+EukE5ApWHUUAL0s955kxdQe5624S6rp3L Shdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FjmC/46ARakxFpcFGMLJHjfrHdRZ+a4Hi4clf4uxgwU=; b=DttaTJYvuk8TlFUjmTAPoYaaQ1Sl8vZzZ1TBBbJTro2CsXyfpGW6VRLxT8g9xL/XQX eiLUmPZ7U8+WSSgG0YLwIthisHETH7A/ARAdsTpxAJmUPoFE/nVwJcaYtvWXpEYeykp1 wjlHOdMBG6Y+/zyGUrO4XrZVxcDyVv28H6SkdlJxvOxno3xHuJ7vwRiN3AhOKSGb4NkZ cP+8MxjyNx3OfDiM87yHyk2fSDSsqsEdlnZSFdi7hqq9Xw/zOhJ79jJnWBoEnWCH4G5l o+QGKUKt4Gw3LVjC9vzA/ZXu/PUepbl7aoSAJUzH9gChv71ol2eSkDyLv4GMIxsXejEB EYxw== X-Gm-Message-State: AJIora87aV+lRKkrryRs9Z/nn7hXy8CPFA22pNPv6bZtKYYAl3JE0O4S s78/8ViXYcmph2KRLNkuYfbyidPx4z341A== X-Google-Smtp-Source: AGRyM1uSYxKTIYeI/f8BOm3mFqZWGpRy67nHzTyvJk938JoVkCE5ilZRPkfjytrR7LeH191WE0DKag== X-Received: by 2002:a17:902:6b05:b0:168:ee36:1928 with SMTP id o5-20020a1709026b0500b00168ee361928mr1764667plk.114.1656390166075; Mon, 27 Jun 2022 21:22:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 35/45] linux-user/aarch64: Add SM bit to SVE signal context Date: Tue, 28 Jun 2022 09:51:07 +0530 Message-Id: <20220628042117.368549-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656394298535100003 Content-Type: text/plain; charset="utf-8" Make sure to zero the currently reserved fields. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 7da0e36c6d..3cef2f44cf 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -78,7 +78,8 @@ struct target_extra_context { struct target_sve_context { struct target_aarch64_ctx head; uint16_t vl; - uint16_t reserved[3]; + uint16_t flags; + uint16_t reserved[2]; /* The actual SVE data immediately follows. It is laid out * according to TARGET_SVE_SIG_{Z,P}REG_OFFSET, based off of * the original struct pointer. @@ -101,6 +102,8 @@ struct target_sve_context { #define TARGET_SVE_SIG_CONTEXT_SIZE(VQ) \ (TARGET_SVE_SIG_PREG_OFFSET(VQ, 17)) =20 +#define TARGET_SVE_SIG_FLAG_SM 1 + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -177,9 +180,13 @@ static void target_setup_sve_record(struct target_sve_= context *sve, { int i, j; =20 + memset(sve, 0, sizeof(*sve)); __put_user(TARGET_SVE_MAGIC, &sve->head.magic); __put_user(size, &sve->head.size); __put_user(vq * TARGET_SVE_VQ_BYTES, &sve->vl); + if (FIELD_EX64(env->svcr, SVCR, SM)) { + __put_user(TARGET_SVE_SIG_FLAG_SM, &sve->flags); + } =20 /* Note that SVE regs are stored as a byte stream, with each byte elem= ent * at a subsequent address. This corresponds to a little-endian store --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656391619151640.4827298405353; Mon, 27 Jun 2022 21:46:59 -0700 (PDT) Received: from localhost ([::1]:42372 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o637o-0003IQ-6l for importer@patchew.org; Tue, 28 Jun 2022 00:46:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37986) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62kX-0002sA-Rx for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:56 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:38427) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62kW-0003mt-5h for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:53 -0400 Received: by mail-pl1-x634.google.com with SMTP id m14so9985013plg.5 for ; Mon, 27 Jun 2022 21:22:48 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.22.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:22:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VPMml4Tfq67+y3oqJMSmdBs/iUTANF8r3DziFKMfYRY=; b=qNMv5KJ4/nrWDTYoTfCVBMX18+24NTGEJBQX0ZTv0L+ahPfTg5P6WxN8SLRKd7VnQ1 gGHWIaNAZFu+3X+qTv9QqTIRRq9Swtlh+BlIfurGpJmUS0uFm2s9/o3Y1lRAxTtl4gZi xwphL7fgW42NeUufUras1zZDD/MpKBobJBOXzVQ91B/TuRH5uleufFlb4FqaYGFoSZvS x0uYL6S180ghHP0Zsy8JwUVj33M7R2bLoVlACt2dmS0G2EfYgquclUPb7iP1k8Jc410m yJ0Zd1vR1gTUVm8iLEMbGBgrlDYNuAeUjNC/ZSA5nqWBRmFabEEw9DrDCrhKdKqD64sZ vD7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VPMml4Tfq67+y3oqJMSmdBs/iUTANF8r3DziFKMfYRY=; b=2JvaHgil/VMlYYyNbFdEO11z/mcp37Mxr6Kv0sZNYjKAWtc7V7r8fvPWL6EY6BtehY I0uTjJv5LVX/JPPoJ76Skhu1U632WQSPdD8Jkrw0ABnpaM3m6egAu3o0X7iOCVwF3f5H lXwtmemPDJEoIXQKlFesjIZEp597HNuWB2OUCtOK9XlotaUKtMCx/1GsAGyxNLIgS+BU lptvhycjNjn6GjlovLeDk7jskCATPxtMQ66MvgYScvlOspuNlZKdOANvc64eNa9yzHDP 6eExP2PLhttz9N6aH/dGGGqdkzEMCIMRThHnznaiUCgJ7Bqddwci/D1lrOh+zxl2gw90 9EQA== X-Gm-Message-State: AJIora8LcTlSuRknNuxpR4Pw5VAd6DGFvRtEWE4Z1CyQzBCfw1Z20jEk ZHfBEb4MmvsT3zeEMgqPeV3+jEDKPqulfw== X-Google-Smtp-Source: AGRyM1v3k2yELXuMoWhj8XgQEwZk3ZB7SJzVSV6cpBxob4GR8fNY342E1Ad9OJnRbMvSlSjubGQUiw== X-Received: by 2002:a17:90b:1b4d:b0:1ec:c42a:7eb5 with SMTP id nv13-20020a17090b1b4d00b001ecc42a7eb5mr19503118pjb.122.1656390168179; Mon, 27 Jun 2022 21:22:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 36/45] linux-user/aarch64: Tidy target_restore_sigframe error return Date: Tue, 28 Jun 2022 09:51:08 +0530 Message-Id: <20220628042117.368549-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656391620954100001 Content-Type: text/plain; charset="utf-8" Fold the return value setting into the goto, so each point of failure need not do both. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/aarch64/signal.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 3cef2f44cf..8b352abb97 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -287,7 +287,6 @@ static int target_restore_sigframe(CPUARMState *env, struct target_sve_context *sve =3D NULL; uint64_t extra_datap =3D 0; bool used_extra =3D false; - bool err =3D false; int vq =3D 0, sve_size =3D 0; =20 target_restore_general_frame(env, sf); @@ -301,8 +300,7 @@ static int target_restore_sigframe(CPUARMState *env, switch (magic) { case 0: if (size !=3D 0) { - err =3D true; - goto exit; + goto err; } if (used_extra) { ctx =3D NULL; @@ -314,8 +312,7 @@ static int target_restore_sigframe(CPUARMState *env, =20 case TARGET_FPSIMD_MAGIC: if (fpsimd || size !=3D sizeof(struct target_fpsimd_context)) { - err =3D true; - goto exit; + goto err; } fpsimd =3D (struct target_fpsimd_context *)ctx; break; @@ -329,13 +326,11 @@ static int target_restore_sigframe(CPUARMState *env, break; } } - err =3D true; - goto exit; + goto err; =20 case TARGET_EXTRA_MAGIC: if (extra || size !=3D sizeof(struct target_extra_context)) { - err =3D true; - goto exit; + goto err; } __get_user(extra_datap, &((struct target_extra_context *)ctx)->datap); @@ -348,8 +343,7 @@ static int target_restore_sigframe(CPUARMState *env, /* Unknown record -- we certainly didn't generate it. * Did we in fact get out of sync? */ - err =3D true; - goto exit; + goto err; } ctx =3D (void *)ctx + size; } @@ -358,17 +352,19 @@ static int target_restore_sigframe(CPUARMState *env, if (fpsimd) { target_restore_fpsimd_record(env, fpsimd); } else { - err =3D true; + goto err; } =20 /* SVE data, if present, overwrites FPSIMD data. */ if (sve) { target_restore_sve_record(env, sve, vq); } - - exit: unlock_user(extra, extra_datap, 0); - return err; + return 0; + + err: + unlock_user(extra, extra_datap, 0); + return 1; } =20 static abi_ulong get_sigframe(struct target_sigaction *ka, --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656391767013729.725606177981; Mon, 27 Jun 2022 21:49:27 -0700 (PDT) Received: from localhost ([::1]:50656 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o63AD-0000gE-As for importer@patchew.org; Tue, 28 Jun 2022 00:49:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38020) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62kZ-0002sN-DT for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:56 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:51722) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62kX-0003xB-4r for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:54 -0400 Received: by mail-pj1-x1029.google.com with SMTP id l2so10194605pjf.1 for ; Mon, 27 Jun 2022 21:22:52 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.22.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:22:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Khgw4zesO+K18d95Nf0OQk5x631DSo+q5LDKVsiqTz0=; b=rDzqmofjl4o98bp+xn1VuN1Q8v0nCh/xUhzrCMEqK/teEdEpqEyuNefE09ALI9d0sx 8wI+TdkeqFEUvweY+mNlnD0EeyEtKC8a+GS0vParPXMv/rjacvpAW/30xRYYy23ebKYw LunZOOpFdhvT3DehNPa6kAFYv36JaSJhLe3pdZMGy/wiB9s8U0byXLwAVF5rAuYIMSlI 7I0iLlxzIlncM/441iqepljy8hI3P9VPJxSmmK84OpbLdBONduKSejvDEliCSIoBFj4q 91sF9VN3pobXF/EIrWtrUioxz50nVRiupACfX7B3BFktYfzH0mmv69ctnbOq1B2cClG9 bf7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Khgw4zesO+K18d95Nf0OQk5x631DSo+q5LDKVsiqTz0=; b=MjLRawW2a9jCCZlDpS8YNvu/lTniRSW0au/YALcAf+Ej8jzgQ3q5veHyTuhTDMa3nR E31PPCfFRWID7BIHIBqX0114LLO+cD0rNQ7Rkvv4z/YNIspKCX62e4UwDuxC/X3QqaaT frZXoLVAA9GbN4D5UxQjB46iMJt0ukVa8r1XvZMB8Mvo6s+DWj+KeXG4mWlMaNUZpfZ4 brMetrJOxLc/FmIc2B8m4KYDN8eGJISYkFH1BHUKam09n9AT3KtYZBXVn4XLqERoDhXV P7V5gDflPlLWDhSU6XdXOA/R1vb3xjXyEeF4/lSDd0OvDwsvwiBDTcuu3tKMV0Y7HFGQ 4fGw== X-Gm-Message-State: AJIora+GY366TgLrW66q0SxZ/aGTpyoCLxJ4VmKo10BQYmDbd9y8gjV6 +oBbELuDyI8BrWzXGuqS5woIeEh/Y6tW/g== X-Google-Smtp-Source: AGRyM1smO3xpfqKjxN3DXHrSd9IPWaTcre+PBw9skAy/51+IaY17K5Tl4deAsWe62DLmWnh5gfGz+Q== X-Received: by 2002:a17:902:e382:b0:16a:23a0:9530 with SMTP id g2-20020a170902e38200b0016a23a09530mr3000637ple.128.1656390170373; Mon, 27 Jun 2022 21:22:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 37/45] linux-user/aarch64: Do not allow duplicate or short sve records Date: Tue, 28 Jun 2022 09:51:09 +0530 Message-Id: <20220628042117.368549-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656391767524100001 Content-Type: text/plain; charset="utf-8" In parse_user_sigframe, the kernel rejects duplicate sve records, or records that are smaller than the header. We were silently allowing these cases to pass, dropping the record. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 8b352abb97..8fbe98d72f 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -318,10 +318,13 @@ static int target_restore_sigframe(CPUARMState *env, break; =20 case TARGET_SVE_MAGIC: + if (sve || size < sizeof(struct target_sve_context)) { + goto err; + } if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { vq =3D sve_vq(env); sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq)= , 16); - if (!sve && size =3D=3D sve_size) { + if (size =3D=3D sve_size) { sve =3D (struct target_sve_context *)ctx; break; } --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656394732881492.0772652946297; Mon, 27 Jun 2022 22:38:52 -0700 (PDT) Received: from localhost ([::1]:48594 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o63w3-0000A8-Du for importer@patchew.org; Tue, 28 Jun 2022 01:38:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38014) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62kZ-0002sL-DL for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:56 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:41679) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62kX-0003nj-Jh for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:22:54 -0400 Received: by mail-pf1-x42f.google.com with SMTP id i64so10876758pfc.8 for ; Mon, 27 Jun 2022 21:22:53 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656394734453100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/aarch64/signal.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 8fbe98d72f..9ff79da4be 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -340,6 +340,9 @@ static int target_restore_sigframe(CPUARMState *env, __get_user(extra_size, &((struct target_extra_context *)ctx)->size); extra =3D lock_user(VERIFY_READ, extra_datap, extra_size, 0); + if (!extra) { + return 1; + } break; =20 default: --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656395412151233.92563843878054; Mon, 27 Jun 2022 22:50:12 -0700 (PDT) Received: from localhost ([::1]:60102 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o646z-0000qg-Fx for importer@patchew.org; Tue, 28 Jun 2022 01:50:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38082) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62kq-0002wY-OY for qemu-devel@nongnu.org; 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([122.255.60.245]) by smtp.gmail.com with ESMTPSA id jg6-20020a17090326c600b0016a087cfad8sm7994929plb.264.2022.06.27.21.22.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:22:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pyZCOGTvs2PmDR4WHKguGZ+NHJT+1M/Dn/XfXNcerpI=; b=vCmVON94gl4G2Y+bZqxMm2Q6igB/O8sZ2JUs3RBmf801kLb5ANfdrNhXCBXTbrE6rW FWusndL4okxMTEPF4rG/gqF98GgFESQyNff6kLeV+YUKxUG0JQ3jB44UsmusDAIBDcri GyU5QzfdziOzDODjTHuV2TPgZ1fyaC3BsR+aF2KJISanHuZFu+qVYcC0a4VHyiKArgNz Yp2PcOtQwCMbv0w3bhXSXIGG1M2XfhfFFwooQn0jfaWrTn6YABzYS3KrWLcO66lKHnAE TA0l4mP5w8x1mEQrcNESjCGGIWstPNYEOQ8Ci5Ok/i1kPjvTzb9cQJXOE2S8irQZcWot 6XHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pyZCOGTvs2PmDR4WHKguGZ+NHJT+1M/Dn/XfXNcerpI=; b=1k0N6LaWqj0u0ThkIpAHAxpDLDBgdLlnaRkqc4G765IrbVCXoNppnvTEhZZBfPDjpe dvEUKC7GnK60Q0/r+Sxjlm6prWsIYJ34bOOWGYRx+D8BGG/0aDYOsQq/rFwVJcNJ7L+h /YyoK8x3F2WrZaJO1xxzVNM0nkaGoDCWdXF696Sc6RNl4VmxKZ/13y1J8eBcxU4jt9zb P2XPw5jUXL2UZaiDAI3BWPZ6nBYFZzyUl1O6JKVlIAq0hZwbVN++4wX79I1fhjk1MJlV FeIOVuvFcPVecZSU3pINDzv9B9J4ivo4sW8CL8PGh7if9nxUv7qUX3RMfH//vkqdXORn VKgw== X-Gm-Message-State: AJIora9vdGNTZmZ6n6sKcxLxcgc3NYF9JSSxePKAe/k8Zs5NF4Bk60QH QXcg5ao1IkqrZKVYF8wYvlC4xiWgbzZMlQ== X-Google-Smtp-Source: AGRyM1vD4Kr4MyesWIWXYFCX96gR/7VAL40Vhfp1QgF9NAI/pCZT8CnXyaHDOS0XIG1miIpPnPPbwA== X-Received: by 2002:a63:1759:0:b0:40d:5aba:4bb0 with SMTP id 25-20020a631759000000b0040d5aba4bb0mr16085440pgx.496.1656390175165; Mon, 27 Jun 2022 21:22:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 39/45] linux-user/aarch64: Move sve record checks into restore Date: Tue, 28 Jun 2022 09:51:11 +0530 Message-Id: <20220628042117.368549-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656395413973100001 Content-Type: text/plain; charset="utf-8" Move the checks out of the parsing loop and into the restore function. This more closely mirrors the code structure in the kernel, and is slightly clearer. Reject rather than silently skip incorrect VL and SVE record sizes. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/aarch64/signal.c | 51 +++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 16 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 9ff79da4be..22d0b8b4ec 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -250,12 +250,36 @@ static void target_restore_fpsimd_record(CPUARMState = *env, } } =20 -static void target_restore_sve_record(CPUARMState *env, - struct target_sve_context *sve, int = vq) +static bool target_restore_sve_record(CPUARMState *env, + struct target_sve_context *sve, + int size) { - int i, j; + int i, j, vl, vq; =20 - /* Note that SVE regs are stored as a byte stream, with each byte elem= ent + if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) { + return false; + } + + __get_user(vl, &sve->vl); + vq =3D sve_vq(env); + + /* Reject mismatched VL. */ + if (vl !=3D vq * TARGET_SVE_VQ_BYTES) { + return false; + } + + /* Accept empty record -- used to clear PSTATE.SM. */ + if (size <=3D sizeof(*sve)) { + return true; + } + + /* Reject non-empty but incomplete record. */ + if (size < TARGET_SVE_SIG_CONTEXT_SIZE(vq)) { + return false; + } + + /* + * Note that SVE regs are stored as a byte stream, with each byte elem= ent * at a subsequent address. This corresponds to a little-endian load * of our 64-bit hunks. */ @@ -277,6 +301,7 @@ static void target_restore_sve_record(CPUARMState *env, } } } + return true; } =20 static int target_restore_sigframe(CPUARMState *env, @@ -287,7 +312,7 @@ static int target_restore_sigframe(CPUARMState *env, struct target_sve_context *sve =3D NULL; uint64_t extra_datap =3D 0; bool used_extra =3D false; - int vq =3D 0, sve_size =3D 0; + int sve_size =3D 0; =20 target_restore_general_frame(env, sf); =20 @@ -321,15 +346,9 @@ static int target_restore_sigframe(CPUARMState *env, if (sve || size < sizeof(struct target_sve_context)) { goto err; } - if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { - vq =3D sve_vq(env); - sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq)= , 16); - if (size =3D=3D sve_size) { - sve =3D (struct target_sve_context *)ctx; - break; - } - } - goto err; + sve =3D (struct target_sve_context *)ctx; + sve_size =3D size; + break; =20 case TARGET_EXTRA_MAGIC: if (extra || size !=3D sizeof(struct target_extra_context)) { @@ -362,8 +381,8 @@ static int target_restore_sigframe(CPUARMState *env, } =20 /* SVE data, if present, overwrites FPSIMD data. */ - if (sve) { - target_restore_sve_record(env, sve, vq); + if (sve && !target_restore_sve_record(env, sve, sve_size)) { + goto err; } unlock_user(extra, extra_datap, 0); return 0; --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656391975444317.05591276877806; Mon, 27 Jun 2022 21:52:55 -0700 (PDT) Received: from localhost ([::1]:58982 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o63Da-0006VJ-9G for importer@patchew.org; Tue, 28 Jun 2022 00:52:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38678) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62nd-0008Q9-DN for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:26:05 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:39689) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62nb-0004N7-5R for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:26:04 -0400 Received: by mail-pg1-x529.google.com with SMTP id q140so11021066pgq.6 for ; Mon, 27 Jun 2022 21:26:02 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id k26-20020aa7821a000000b0052517150777sm8160565pfi.41.2022.06.27.21.25.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:26:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pHB4ROsLewdQ7HrrSMrZ3uGIT5+drN7tItK3h279f+o=; b=QUqugosrd9RGlDrUFLIEKrx3iQFjgMEKXr1W87CRq/wniF1UkOadR0KbgNfdQzKZWt 0mpc/ZBfj0Ruo2bH72nKnnAnNnJkNyG/KAhCWxMNrCHxBaYtgK1AdhOKGHIhqSw5dwqz jnfEjJDKAnNVoKIIA+D0s/BGMbZ3GDR8ZRSkuVuVUzL7mYfrbGk1exCYLlfC8pWKRFKH oGmHzOaGIHpKxAQMES3TkrGLMRPI7Rjbg1UjO7iVnMJ5J4PJl+ONvfQYKZ0EDngbXAx1 f8rmMH7GBliQYzwT32W2ML989gNDRkC96fh2MPQv84fZ6RaraeP0PCBAd3PyVv6F6t6K V4Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pHB4ROsLewdQ7HrrSMrZ3uGIT5+drN7tItK3h279f+o=; b=CY4MMJWN3SjWeYQSM0xnTd21oVOYHpyQfV88Uy0Vtvd+zGNvcMX3y3ovviSgT+QHDj Z0uLei+Y7b8zG1hqHQ3v9dADZ+5X7WbwIidV7k8LdsD/XbBHqi7yRcXqRhjf5ESMr9GN wZL5PywoedWKVqgujoIm2sHNXPnrrYrpHQwDGqrXUjajl5ZQfXpBWsfxYxNshRC72z9m nbraoCM4hfWq9l85lZDCdW2gqlFTWw6QkXoqf3YcphffHhF2xOyUAVVCeIHJjTcOeeKI Xw+cso3X9ILiIaZnY/G0589pRPH0cdgvprXH1Zfg8jr2fJrOvD1WUOYA64mU+7Blao6K KCEg== X-Gm-Message-State: AJIora8/s5rEyQ3t+t/FvMlobzKA2En869Q+dCXoa5T/SxIi4OnVk77J ung1YqqSR+oSv5zdRi6vHnDzAiDVjLcCRw== X-Google-Smtp-Source: AGRyM1tXfUGZKpzMhhFU7DzbB+e006Qhrdh3b8RIDjPVvDgqZGe2PntDNLLUqV7O3Hws9rscG95UGg== X-Received: by 2002:a63:9044:0:b0:40c:9a2e:5b88 with SMTP id a65-20020a639044000000b0040c9a2e5b88mr15918544pge.214.1656390361383; Mon, 27 Jun 2022 21:26:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 40/45] linux-user/aarch64: Implement SME signal handling Date: Tue, 28 Jun 2022 09:51:12 +0530 Message-Id: <20220628042117.368549-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656391976467100001 Content-Type: text/plain; charset="utf-8" Set the SM bit in the SVE record on signal delivery, create the ZA record. Restore SM and ZA state according to the records present on return. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/aarch64/signal.c | 162 +++++++++++++++++++++++++++++++++--- 1 file changed, 151 insertions(+), 11 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 22d0b8b4ec..1ad125d3d9 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -104,6 +104,22 @@ struct target_sve_context { =20 #define TARGET_SVE_SIG_FLAG_SM 1 =20 +#define TARGET_ZA_MAGIC 0x54366345 + +struct target_za_context { + struct target_aarch64_ctx head; + uint16_t vl; + uint16_t reserved[3]; + /* The actual ZA data immediately follows. */ +}; + +#define TARGET_ZA_SIG_REGS_OFFSET \ + QEMU_ALIGN_UP(sizeof(struct target_za_context), TARGET_SVE_VQ_BYTES) +#define TARGET_ZA_SIG_ZAV_OFFSET(VQ, N) \ + (TARGET_ZA_SIG_REGS_OFFSET + (VQ) * TARGET_SVE_VQ_BYTES * (N)) +#define TARGET_ZA_SIG_CONTEXT_SIZE(VQ) \ + TARGET_ZA_SIG_ZAV_OFFSET(VQ, VQ * TARGET_SVE_VQ_BYTES) + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -176,9 +192,9 @@ static void target_setup_end_record(struct target_aarch= 64_ctx *end) } =20 static void target_setup_sve_record(struct target_sve_context *sve, - CPUARMState *env, int vq, int size) + CPUARMState *env, int size) { - int i, j; + int i, j, vq =3D sme_vq(env); =20 memset(sve, 0, sizeof(*sve)); __put_user(TARGET_SVE_MAGIC, &sve->head.magic); @@ -207,6 +223,34 @@ static void target_setup_sve_record(struct target_sve_= context *sve, } } =20 +static void target_setup_za_record(struct target_za_context *za, + CPUARMState *env, int size) +{ + int vq =3D sme_vq(env); + int vl =3D vq * TARGET_SVE_VQ_BYTES; + int i, j; + + memset(za, 0, sizeof(*za)); + __put_user(TARGET_ZA_MAGIC, &za->head.magic); + __put_user(size, &za->head.size); + __put_user(vl, &za->vl); + + if (size =3D=3D TARGET_ZA_SIG_CONTEXT_SIZE(0)) { + return; + } + + /* + * Note that ZA vectors are stored as a byte stream, + * with each byte element at a subsequent address. + */ + for (i =3D 0; i < vl; ++i) { + uint64_t *z =3D (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i); + for (j =3D 0; j < vq * 2; ++j) { + __put_user_e(env->zarray[i].d[j], z + j, le); + } + } +} + static void target_restore_general_frame(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -252,16 +296,28 @@ static void target_restore_fpsimd_record(CPUARMState = *env, =20 static bool target_restore_sve_record(CPUARMState *env, struct target_sve_context *sve, - int size) + int size, int *svcr) { - int i, j, vl, vq; + int i, j, vl, vq, flags; + bool sm; =20 + /* ??? Kernel tests SVE && (!sm || SME); suggest (sm ? SME : SVE). */ if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) { return false; } =20 __get_user(vl, &sve->vl); - vq =3D sve_vq(env); + __get_user(flags, &sve->flags); + + sm =3D flags & TARGET_SVE_SIG_FLAG_SM; + if (sm) { + if (!cpu_isar_feature(aa64_sme, env_archcpu(env))) { + return false; + } + vq =3D sme_vq(env); + } else { + vq =3D sve_vq(env); + } =20 /* Reject mismatched VL. */ if (vl !=3D vq * TARGET_SVE_VQ_BYTES) { @@ -278,6 +334,8 @@ static bool target_restore_sve_record(CPUARMState *env, return false; } =20 + *svcr =3D FIELD_DP64(*svcr, SVCR, SM, sm); + /* * Note that SVE regs are stored as a byte stream, with each byte elem= ent * at a subsequent address. This corresponds to a little-endian load @@ -304,15 +362,57 @@ static bool target_restore_sve_record(CPUARMState *en= v, return true; } =20 +static bool target_restore_za_record(CPUARMState *env, + struct target_za_context *za, + int size, int *svcr) +{ + int i, j, vl, vq; + + if (!cpu_isar_feature(aa64_sme, env_archcpu(env))) { + return false; + } + + __get_user(vl, &za->vl); + vq =3D sme_vq(env); + + /* Reject mismatched VL. */ + if (vl !=3D vq * TARGET_SVE_VQ_BYTES) { + return false; + } + + /* Accept empty record -- used to clear PSTATE.ZA. */ + if (size <=3D TARGET_ZA_SIG_CONTEXT_SIZE(0)) { + return true; + } + + /* Reject non-empty but incomplete record. */ + if (size < TARGET_ZA_SIG_CONTEXT_SIZE(vq)) { + return false; + } + + *svcr =3D FIELD_DP64(*svcr, SVCR, ZA, 1); + + for (i =3D 0; i < vl; ++i) { + uint64_t *z =3D (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i); + for (j =3D 0; j < vq * 2; ++j) { + __get_user_e(env->zarray[i].d[j], z + j, le); + } + } + return true; +} + static int target_restore_sigframe(CPUARMState *env, struct target_rt_sigframe *sf) { struct target_aarch64_ctx *ctx, *extra =3D NULL; struct target_fpsimd_context *fpsimd =3D NULL; struct target_sve_context *sve =3D NULL; + struct target_za_context *za =3D NULL; uint64_t extra_datap =3D 0; bool used_extra =3D false; int sve_size =3D 0; + int za_size =3D 0; + int svcr =3D 0; =20 target_restore_general_frame(env, sf); =20 @@ -350,6 +450,14 @@ static int target_restore_sigframe(CPUARMState *env, sve_size =3D size; break; =20 + case TARGET_ZA_MAGIC: + if (za || size < sizeof(struct target_za_context)) { + goto err; + } + za =3D (struct target_za_context *)ctx; + za_size =3D size; + break; + case TARGET_EXTRA_MAGIC: if (extra || size !=3D sizeof(struct target_extra_context)) { goto err; @@ -381,9 +489,16 @@ static int target_restore_sigframe(CPUARMState *env, } =20 /* SVE data, if present, overwrites FPSIMD data. */ - if (sve && !target_restore_sve_record(env, sve, sve_size)) { + if (sve && !target_restore_sve_record(env, sve, sve_size, &svcr)) { goto err; } + if (za && !target_restore_za_record(env, za, za_size, &svcr)) { + goto err; + } + if (env->svcr !=3D svcr) { + env->svcr =3D svcr; + arm_rebuild_hflags(env); + } unlock_user(extra, extra_datap, 0); return 0; =20 @@ -451,7 +566,8 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, .total_size =3D offsetof(struct target_rt_sigframe, uc.tuc_mcontext.__reserved), }; - int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, vq =3D 0, sve_size =3D 0; + int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, za_ofs =3D 0; + int sve_size =3D 0, za_size =3D 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; abi_ulong frame_addr, return_addr; @@ -461,11 +577,20 @@ static void target_setup_frame(int usig, struct targe= t_sigaction *ka, &layout); =20 /* SVE state needs saving only if it exists. */ - if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { - vq =3D sve_vq(env); - sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); + if (cpu_isar_feature(aa64_sve, env_archcpu(env)) || + cpu_isar_feature(aa64_sme, env_archcpu(env))) { + sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(sve_vq(env)= ), 16); sve_ofs =3D alloc_sigframe_space(sve_size, &layout); } + if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { + /* ZA state needs saving only if it is enabled. */ + if (FIELD_EX64(env->svcr, SVCR, ZA)) { + za_size =3D TARGET_ZA_SIG_CONTEXT_SIZE(sme_vq(0)); + } else { + za_size =3D TARGET_ZA_SIG_CONTEXT_SIZE(0); + } + za_ofs =3D alloc_sigframe_space(za_size, &layout); + } =20 if (layout.extra_ofs) { /* Reserve space for the extra end marker. The standard end marker @@ -512,7 +637,10 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, target_setup_end_record((void *)frame + layout.extra_end_ofs); } if (sve_ofs) { - target_setup_sve_record((void *)frame + sve_ofs, env, vq, sve_size= ); + target_setup_sve_record((void *)frame + sve_ofs, env, sve_size); + } + if (za_ofs) { + target_setup_za_record((void *)frame + za_ofs, env, za_size); } =20 /* Set up the stack frame for unwinding. */ @@ -536,6 +664,18 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, env->btype =3D 2; } =20 + /* + * Invoke the signal handler with both SM and ZA disabled. + * When clearing SM, ResetSVEState, per SMSTOP. + */ + if (FIELD_EX64(env->svcr, SVCR, SM)) { + arm_reset_sve_state(env); + } + if (env->svcr) { + env->svcr =3D 0; + arm_rebuild_hflags(env); + } + if (info) { tswap_siginfo(&frame->info, info); env->xregs[1] =3D frame_addr + offsetof(struct target_rt_sigframe,= info); --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656395845779752.0106889796882; Mon, 27 Jun 2022 22:57:25 -0700 (PDT) Received: from localhost ([::1]:42798 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o64E0-0008Th-0P for importer@patchew.org; Tue, 28 Jun 2022 01:57:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38710) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62nf-0008WO-53 for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:26:07 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:51073) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62nd-0004NN-Gy for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:26:06 -0400 Received: by mail-pj1-x1036.google.com with SMTP id go6so11436963pjb.0 for ; Mon, 27 Jun 2022 21:26:04 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id k26-20020aa7821a000000b0052517150777sm8160565pfi.41.2022.06.27.21.26.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:26:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fbE60MKW9MqcBNahx+13s58wIA5fTI9eDU3V2q8ulQ0=; b=Hyi9eOgtLrj8x5NdCzoi7vDogIWt2Djdhcz8wNfkMidl9lM0VZ/TWBNG2ByuQiAN3h BQ22zDkqjvCW4xL6Czb02IKxTCsnF/qyItnqTmCC/fHbO9Y8ttDVOBMFvqks9M5iuZlb oMtIfK5IDuUhww90GFQTHhnoZyERrF7W3fAb27SyXKWjfcLRwxGrbn3iHPbDeaiAw+hV Af+OVTEptelCC5fi6htocU1adyY1N7uYzUVNNqcnA2Q9TEMxvJRdcNlEtenXoNJST/ML aJAZI19jmvbKPoYc36+ezwrLZaEMCWTIRtTYF02XdUYQq3m3+0wXVaeV0/pfwbvQuUDy mZmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fbE60MKW9MqcBNahx+13s58wIA5fTI9eDU3V2q8ulQ0=; b=ZpM36ieQ9lP5DXdO8CvY1YRdUBrRYcEj9bTQPxeamWiVkIpZUgW6dGDMKcb6Tqe4vK yVIWb5J5pvXD3uvKQKPoD3iIxHhiOUFVo56hhoi6MbfGbjxscW12bTGCRWV7hP1uJOLN TnOwsuoBQm99DpMZqu9JziR4EHNFhfuLWgiBVuN1oOB42ZW/kl0W5gCZ5rUmi1NiJjos s9ELj7ojkf0kFyts4iKvNs25otJTPA/7HYrAi9fUrtB1qWlnmWDEeWLx3lsgNTv+NWLD hlTeu4wsMUDRwHQxvfp+Y6p5S3jdre3Gn0F9T6B+J1y7gvMAY8yOct3JndhAoP0fHRJ6 I7hw== X-Gm-Message-State: AJIora80/ydRJmBTVMeobIVxp6ffyUUtCIdPhXKr7MadyKGEYGVU/Mcq rxh5dNu93bl2CxlLrzzdpIbzJ1n6nqhPOA== X-Google-Smtp-Source: AGRyM1v1+C5e0dGtI4kYqJb5gdXVDG4OUO8vh6SCAB/Aci8B6FsPkEHf7GNHfIkxfAs/Si4OAhy/rg== X-Received: by 2002:a17:902:bb8d:b0:168:e48d:86bc with SMTP id m13-20020a170902bb8d00b00168e48d86bcmr2961811pls.93.1656390364023; Mon, 27 Jun 2022 21:26:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 41/45] linux-user: Rename sve prctls Date: Tue, 28 Jun 2022 09:51:13 +0530 Message-Id: <20220628042117.368549-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656395847570100001 Content-Type: text/plain; charset="utf-8" Add "sve" to the sve prctl functions, to distinguish them from the coming "sme" prctls with similar names. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/aarch64/target_prctl.h | 8 ++++---- linux-user/syscall.c | 12 ++++++------ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_= prctl.h index 1d440ffbea..40481e6663 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -6,7 +6,7 @@ #ifndef AARCH64_TARGET_PRCTL_H #define AARCH64_TARGET_PRCTL_H =20 -static abi_long do_prctl_get_vl(CPUArchState *env) +static abi_long do_prctl_sve_get_vl(CPUArchState *env) { ARMCPU *cpu =3D env_archcpu(env); if (cpu_isar_feature(aa64_sve, cpu)) { @@ -14,9 +14,9 @@ static abi_long do_prctl_get_vl(CPUArchState *env) } return -TARGET_EINVAL; } -#define do_prctl_get_vl do_prctl_get_vl +#define do_prctl_sve_get_vl do_prctl_sve_get_vl =20 -static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2) +static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2) { /* * We cannot support either PR_SVE_SET_VL_ONEXEC or PR_SVE_VL_INHERIT. @@ -47,7 +47,7 @@ static abi_long do_prctl_set_vl(CPUArchState *env, abi_lo= ng arg2) } return -TARGET_EINVAL; } -#define do_prctl_set_vl do_prctl_set_vl +#define do_prctl_sve_set_vl do_prctl_sve_set_vl =20 static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) { diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 669add74c1..cbde82c907 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6362,11 +6362,11 @@ static abi_long do_prctl_inval1(CPUArchState *env, = abi_long arg2) #ifndef do_prctl_set_fp_mode #define do_prctl_set_fp_mode do_prctl_inval1 #endif -#ifndef do_prctl_get_vl -#define do_prctl_get_vl do_prctl_inval0 +#ifndef do_prctl_sve_get_vl +#define do_prctl_sve_get_vl do_prctl_inval0 #endif -#ifndef do_prctl_set_vl -#define do_prctl_set_vl do_prctl_inval1 +#ifndef do_prctl_sve_set_vl +#define do_prctl_sve_set_vl do_prctl_inval1 #endif #ifndef do_prctl_reset_keys #define do_prctl_reset_keys do_prctl_inval1 @@ -6431,9 +6431,9 @@ static abi_long do_prctl(CPUArchState *env, abi_long = option, abi_long arg2, case PR_SET_FP_MODE: return do_prctl_set_fp_mode(env, arg2); case PR_SVE_GET_VL: - return do_prctl_get_vl(env); + return do_prctl_sve_get_vl(env); case PR_SVE_SET_VL: - return do_prctl_set_vl(env, arg2); + return do_prctl_sve_set_vl(env, arg2); case PR_PAC_RESET_KEYS: if (arg3 || arg4 || arg5) { return -TARGET_EINVAL; --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656392239532698.1289325737498; Mon, 27 Jun 2022 21:57:19 -0700 (PDT) Received: from localhost ([::1]:42088 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o63Hp-0005lf-T1 for importer@patchew.org; Tue, 28 Jun 2022 00:57:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38746) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62ni-0000F4-Jk for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:26:10 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:36598) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62ng-0004Nt-9S for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:26:09 -0400 Received: by mail-pj1-x102f.google.com with SMTP id c6-20020a17090abf0600b001eee794a478so3913707pjs.1 for ; Mon, 27 Jun 2022 21:26:07 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id k26-20020aa7821a000000b0052517150777sm8160565pfi.41.2022.06.27.21.26.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:26:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XzmAsw+HehUgAR34ijj4idKuyBEWb7euFeYY0G4Evdg=; b=gUGPKIvi4ZWycsTjoR8nwk2UV/r9O8uhCXbDBVxirKqVAPBwE34Pxsvn7s4TZvvUJU 7wsgMD2ZATeXWLH+l+5GNQHbmuQjt/mRz+ilPXVVgHZ9Mu5vNhfVi+MZaNcBowXwmgDD MdhO5VFBLK6A7slOhDRMExECC/9Dp1EauxpwhsYy6K2p7SAcZiPtpoqkNC1PcswtpFV8 LC59T550tYuqQcSuFs32Q0GqP7hz+VccV+sajI4hTROAdf2FFzfhJiOTC0F9jU1EJ8gI F/uJ4VzhwXgCXrgLT2JR/nvpFFfd8LWFOeSJV14wXpFdaLTjPV1JaKaMdIWK1SPEaFvI fPTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XzmAsw+HehUgAR34ijj4idKuyBEWb7euFeYY0G4Evdg=; b=NYci7h+GcvVF4SLBC/idwbyk1qkOB2nuI7/filLhkGr5qvpuqo4uI1wsOEWgCZXZ78 Hgfi3lPLCjeq0TpoQHT0deY9/+wME0cmDAhQ1etClS5DdxUIqhl02EDASJgJfL0ZMZDL kcOQPxedDBNFHAcROEoMjSuQZqGM7LzVnlRD76Y6vcJsxWXTJBNLKzQh4v184VXrjV8B bHeWlpFe+F5FcHD0BGcBND2aQATjtcPHOihhVukKTTNECpvo5I4iaqw5yMAQzCUU35i4 qLYJ3HteWtgT/fpz21SfXmLogYOeqTnnKR4Rlz1Ri0WwO5Q6CYh/3O2Dgzx5aME7Syfc CGMA== X-Gm-Message-State: AJIora+YZg2+9xhquLsm6tfvDJNBjGj3UtRuekveo7VA0K5usreJnh1G 1I711riQUHtLXPcq0XAzPTyLMP/GtW7Ltg== X-Google-Smtp-Source: AGRyM1v0O4ISpFA0dUu244rYwNA4qquLhGpHqyfW0fnQ6T5gpvXqayX9cRRxM136JqtBHrjEdEvnEQ== X-Received: by 2002:a17:90b:4c92:b0:1ec:ea7c:89af with SMTP id my18-20020a17090b4c9200b001ecea7c89afmr25144105pjb.195.1656390366971; Mon, 27 Jun 2022 21:26:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 42/45] linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL Date: Tue, 28 Jun 2022 09:51:14 +0530 Message-Id: <20220628042117.368549-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656392241546100001 Content-Type: text/plain; charset="utf-8" These prctl set the Streaming SVE vector length, which may be completely different from the Normal SVE vector length. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/aarch64/target_prctl.h | 48 +++++++++++++++++++++++++++++++ linux-user/syscall.c | 16 +++++++++++ 2 files changed, 64 insertions(+) diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_= prctl.h index 40481e6663..f8f8f88992 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -10,6 +10,7 @@ static abi_long do_prctl_sve_get_vl(CPUArchState *env) { ARMCPU *cpu =3D env_archcpu(env); if (cpu_isar_feature(aa64_sve, cpu)) { + /* PSTATE.SM is always unset on syscall entry. */ return sve_vq(env) * 16; } return -TARGET_EINVAL; @@ -27,6 +28,7 @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, ab= i_long arg2) && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { uint32_t vq, old_vq; =20 + /* PSTATE.SM is always unset on syscall entry. */ old_vq =3D sve_vq(env); =20 /* @@ -49,6 +51,52 @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, a= bi_long arg2) } #define do_prctl_sve_set_vl do_prctl_sve_set_vl =20 +static abi_long do_prctl_sme_get_vl(CPUArchState *env) +{ + ARMCPU *cpu =3D env_archcpu(env); + if (cpu_isar_feature(aa64_sme, cpu)) { + return sme_vq(env) * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_sme_get_vl do_prctl_sme_get_vl + +static abi_long do_prctl_sme_set_vl(CPUArchState *env, abi_long arg2) +{ + /* + * We cannot support either PR_SME_SET_VL_ONEXEC or PR_SME_VL_INHERIT. + * Note the kernel definition of sve_vl_valid allows for VQ=3D512, + * i.e. VL=3D8192, even though the architectural maximum is VQ=3D16. + */ + if (cpu_isar_feature(aa64_sme, env_archcpu(env)) + && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { + int vq, old_vq; + + old_vq =3D sme_vq(env); + + /* + * Bound the value of vq, so that we know that it fits into + * the 4-bit field in SMCR_EL1. Because PSTATE.SM is cleared + * on syscall entry, we are not modifying the current SVE + * vector length. + */ + vq =3D MAX(arg2 / 16, 1); + vq =3D MIN(vq, 16); + env->vfp.smcr_el[1] =3D + FIELD_DP64(env->vfp.smcr_el[1], SMCR, LEN, vq - 1); + vq =3D sme_vq(env); + + if (old_vq !=3D vq) { + /* PSTATE.ZA state is cleared on any change to VQ. */ + env->svcr =3D FIELD_DP64(env->svcr, SVCR, ZA, 0); + arm_rebuild_hflags(env); + } + return vq * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_sme_set_vl do_prctl_sme_set_vl + static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) { ARMCPU *cpu =3D env_archcpu(env); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index cbde82c907..991b85e6b4 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6343,6 +6343,12 @@ abi_long do_arch_prctl(CPUX86State *env, int code, a= bi_ulong addr) #ifndef PR_SET_SYSCALL_USER_DISPATCH # define PR_SET_SYSCALL_USER_DISPATCH 59 #endif +#ifndef PR_SME_SET_VL +# define PR_SME_SET_VL 63 +# define PR_SME_GET_VL 64 +# define PR_SME_VL_LEN_MASK 0xffff +# define PR_SME_VL_INHERIT (1 << 17) +#endif =20 #include "target_prctl.h" =20 @@ -6383,6 +6389,12 @@ static abi_long do_prctl_inval1(CPUArchState *env, a= bi_long arg2) #ifndef do_prctl_set_unalign #define do_prctl_set_unalign do_prctl_inval1 #endif +#ifndef do_prctl_sme_get_vl +#define do_prctl_sme_get_vl do_prctl_inval0 +#endif +#ifndef do_prctl_sme_set_vl +#define do_prctl_sme_set_vl do_prctl_inval1 +#endif =20 static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5) @@ -6434,6 +6446,10 @@ static abi_long do_prctl(CPUArchState *env, abi_long= option, abi_long arg2, return do_prctl_sve_get_vl(env); case PR_SVE_SET_VL: return do_prctl_sve_set_vl(env, arg2); + case PR_SME_GET_VL: + return do_prctl_sme_get_vl(env); + case PR_SME_SET_VL: + return do_prctl_sme_set_vl(env, arg2); case PR_PAC_RESET_KEYS: if (arg3 || arg4 || arg5) { return -TARGET_EINVAL; --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656393402153681.6635980556193; Mon, 27 Jun 2022 22:16:42 -0700 (PDT) Received: from localhost ([::1]:43744 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o63aa-0001pk-RJ for importer@patchew.org; Tue, 28 Jun 2022 01:16:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38784) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62nk-0000Lg-Dg for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:26:12 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:40932) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62ni-0004O3-Is for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:26:11 -0400 Received: by mail-pj1-x1029.google.com with SMTP id g16-20020a17090a7d1000b001ea9f820449so14578196pjl.5 for ; Mon, 27 Jun 2022 21:26:10 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id k26-20020aa7821a000000b0052517150777sm8160565pfi.41.2022.06.27.21.26.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:26:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0UlDy0s46WXVhDokiQ6HI/w5EEoWJmV5q8PtzjD7erw=; b=DyzmU2Y6oSr+sKvo7u70OQ9WghlNaAGbXQG7unBCBgkO+K5z+sNqXWSHoUM6ST/Vez dTFq8/JFQJpQZvsZXsl5MSYwH5uBTEUiKRnV/pxT8VTzvjIxwimita7rkeYre2zP0NKq nbjrY205dYmOM68tzO1EV/CEdShtesAk7EbSNyzI5cwni8uAMS5+aFR0+P+ULPBjlpqZ WnbF5jQGdvBsbgWTyA/AduPCYG4t3p8LszOWxK1Qf3UEhMigzaN0ka4UIJqmkSaMNI6C d4VBCc/zpUSzx4TP24R6TgHibe9MvJWumHlCmOv2qFAGBzQkEYct7darvjoTmmh/1o74 pXDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0UlDy0s46WXVhDokiQ6HI/w5EEoWJmV5q8PtzjD7erw=; b=gLDAJQ3ivYvMJlheoAr81GjPNj6Y5uKLLWYanOyikZphAyzjr26Co3JV4hIR4vjqCA b87UUab1BlL+eZkr12Lq9P8WvoySW1ZZG0dq2gF3IZJ2LxzMOyE6MP7s3EqHtjv40H5l /jINkB2Uv9Rzsdm7kTMdCz+o8jDFJ3UJBnUUeKCe6XAXhGiKOSoJ7CtKdIIFxabdNVey YwND5CzBbbzYNzQQ7M3H3VhD3sG3hxn1G5Zp41kQTYz6KtWdj3nODwQcBjXQl1m7ngFg EJwWxg2K6dtRhLRG9llcWHJ6F1BTGiB9ILf9oSsYg9mGSuZuw8nu+Rn0ilohaipdWY2D CLXQ== X-Gm-Message-State: AJIora9Z1DpuGiRqjrL8TOzN3GNq7BMuYwi7expNr1M1+E+vLz3V2QjE A0Pllsk8oOLkzbgZCsbTc5pQjKBa2fEZoA== X-Google-Smtp-Source: AGRyM1sZyhm9pRLn+InnhH2Kifgj6CE8MiBxKhBD9JEtBEkk4BokFj3/WnHoOX/H2DXlWIIMuI9hhw== X-Received: by 2002:a17:902:e84b:b0:16a:4e50:d4be with SMTP id t11-20020a170902e84b00b0016a4e50d4bemr3105738plg.84.1656390369241; Mon, 27 Jun 2022 21:26:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 43/45] target/arm: Only set ZEN in reset if SVE present Date: Tue, 28 Jun 2022 09:51:15 +0530 Message-Id: <20220628042117.368549-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656393403917100001 Content-Type: text/plain; charset="utf-8" There's no reason to set CPACR_EL1.ZEN if SVE disabled. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4a35890853..20cb622083 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -204,11 +204,10 @@ static void arm_cpu_reset(DeviceState *dev) /* and to the FP/Neon instructions */ env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, CPACR_EL1, FPEN, 3); - /* and to the SVE instructions */ - env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, - CPACR_EL1, ZEN, 3); - /* with reasonable vector length */ + /* and to the SVE instructions, with default vector length */ if (cpu_isar_feature(aa64_sve, cpu)) { + env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, + CPACR_EL1, ZEN, 3); env->vfp.zcr_el[1] =3D cpu->sve_default_vq - 1; } /* --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656392458063973.4649407480699; Mon, 27 Jun 2022 22:00:58 -0700 (PDT) Received: from localhost ([::1]:50714 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o63LM-0003M5-Rl for importer@patchew.org; Tue, 28 Jun 2022 01:00:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62nl-0000R7-Sh for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:26:14 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:34500) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62nk-0004Nu-CV for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:26:13 -0400 Received: by mail-pl1-x62f.google.com with SMTP id jh14so9999970plb.1 for ; Mon, 27 Jun 2022 21:26:11 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id k26-20020aa7821a000000b0052517150777sm8160565pfi.41.2022.06.27.21.26.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:26:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SXozRQJRDsddSiDU4WvdirQqE4A6/ObOnm30QCWvExc=; b=lw3ZBC5IAkdqx1p1s2KVFqXCc6vW6k1VFV64JFiVW4zFkG5KdVnVQK1JGC8aSYfHXx 3woHK+egJwJ2qOXjvFDPXy3InKWNCqPiMA1v3P1YjJucKsBEgFwOaaaiVhREgD+jZh+P OKlzLPpHI2sCukSVETWVXw3ATh0uKiOgYEHCZ4UEqwqGm5sJbGW275g0ZHs83SWTRT8H /XrkD5ghWLO6LK+9HYhR/lQF8x+2T2H6R8ufQNMS3E/o75Rd/tEf4MUiDneQzJ1kxJ9D 3EINihabLq0WW4sesm1jjhANIOJaeoAaOKTl/KuM8B7NbSON+Rzn/QVya+bmGfd7Gdx8 mQCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SXozRQJRDsddSiDU4WvdirQqE4A6/ObOnm30QCWvExc=; b=JSy6/FfXZNDs9suRAqggqBfURyq6ngfRya1zJZcJXPoKtlLDH62a5bPLkNjYFFnFez vZlxUTYf7wbl9CGuY2/cBUBk6dg7JFpwcYA4l0+YWojwIe/0VefDKFun2veuUvpM09vN ZutJXi+YYJCcE0H1ulUMLAToUrEH2A20OG4/PHqcIq0At3rh7kdv3x3d/WbITStfI1Sm 4C1/W2si26uNYUjVS2GCz7t1XuLoAF1IULUiG0VoIAtEaWV1qLivRVigf2c6e+o+m17T NAuDSn6brRXGtvKR3uMb7Q5EfwEJHQcgFUzSaV+Kbatzq2Cs8z9kDnTU5gTSgA7c2pXw Gplg== X-Gm-Message-State: AJIora/8BSLX41tH9TI3jVj/+IEMpXluN1LCjjf7+MGjSi5iWefFMd3H h/eX+nrP29NiocNZr+PcJPS5TJpz66kSDA== X-Google-Smtp-Source: AGRyM1sA/qHuZH5zlcCEgU5FfSAdrBl0BxVmnqbHpWvvgDFxmpLG08uSk3DXwV31VxLpiRwN/As20Q== X-Received: by 2002:a17:90a:a40b:b0:1ec:a22d:5c3 with SMTP id y11-20020a17090aa40b00b001eca22d05c3mr25318448pjp.118.1656390371598; Mon, 27 Jun 2022 21:26:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 44/45] target/arm: Enable SME for user-only Date: Tue, 28 Jun 2022 09:51:16 +0530 Message-Id: <20220628042117.368549-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656392458569100001 Content-Type: text/plain; charset="utf-8" Enable SME, TPIDR2_EL0, and FA64 if supported by the cpu. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 20cb622083..87d836fb2f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -210,6 +210,17 @@ static void arm_cpu_reset(DeviceState *dev) CPACR_EL1, ZEN, 3); env->vfp.zcr_el[1] =3D cpu->sve_default_vq - 1; } + /* and for SME instructions, with default vector length, and TPIDR= 2 */ + if (cpu_isar_feature(aa64_sme, cpu)) { + env->cp15.sctlr_el[1] |=3D SCTLR_EnTP2; + env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, + CPACR_EL1, SMEN, 3); + env->vfp.smcr_el[1] =3D cpu->sme_default_vq - 1; + if (cpu_isar_feature(aa64_sme_fa64, cpu)) { + env->vfp.smcr_el[1] =3D FIELD_DP64(env->vfp.smcr_el[1], + SMCR, FA64, 1); + } + } /* * Enable 48-bit address space (TODO: take reserved_va into accoun= t). * Enable TBI0 but not TBI1. --=20 2.34.1 From nobody Mon Feb 9 17:27:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165639636030273.77266042474548; Mon, 27 Jun 2022 23:06:00 -0700 (PDT) Received: from localhost ([::1]:54824 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o64MJ-00007n-3b for importer@patchew.org; Tue, 28 Jun 2022 02:05:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38850) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o62no-0000YS-Lq for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:26:16 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:37815) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o62nm-0004N8-Pg for qemu-devel@nongnu.org; Tue, 28 Jun 2022 00:26:16 -0400 Received: by mail-pf1-x435.google.com with SMTP id bo5so10908529pfb.4 for ; Mon, 27 Jun 2022 21:26:14 -0700 (PDT) Received: from stoup.. ([122.255.60.245]) by smtp.gmail.com with ESMTPSA id k26-20020aa7821a000000b0052517150777sm8160565pfi.41.2022.06.27.21.26.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:26:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VC8ZWzxnyu6yTnDCbARNM0LQoo/mTr0TQhi66jhQlAA=; b=EnF7Soo7x/yp9bK5HX2/N5c8/ae7rAWSAvvf48wBuBAa16sm4m/zZIBCa08cnwnLrM viJqn7+Lwggj2ntuIQ+WUfeFVGtUBBHh86vRAUyYLVsnVJX8GMXzO2Y47QlO0JjuqHzY 0ne9PYmovpPihskoDNx/mHtRJJolNZ1TWrQeuct/Y90M77bDK0qzNsEA7HomKXzdCbUZ 7LAc9aapWyQyYOJQiVW0ZA6ZHL06yiByKAB8b2ds/Znb97h8ctid430Cxt54/BPqoRWO ulidfXaB6DJtZYayxq8l6X4JT+pCMdUfZ9MHuKZ80S/GJsOKNFzTTGiEKZrxtPH3k7/J bURA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VC8ZWzxnyu6yTnDCbARNM0LQoo/mTr0TQhi66jhQlAA=; b=mUPSChW3tpkqFh8RO5hfaY3ySXXYnc/KmdOS+OqXkCaUk3ds+6cSmcn7gzPokUUD7E sD84sQqc34DLsBaAfQOKLZKxI1PVvv26OM3rq9cLhR0HrrkU2oAxnhTvvHdyM/x/hqoQ GNPIKuM1tyB5U5Q5ze3tNa0S/9jnIZTHwi50kBKXj+25JOIwlz+xwUt9/4mzG71+r3kW hE1okxcyZFMPlRit8d3OzCmnc+G42xc6nSXP803ib/gniWWMr0OmouMFx7rYGQUkhOTu ptV1FMz3+/9U5eWWZV4uDIAuvCXtXq9v0SwNqXyVRao1y5C54JdJWsdPfySLC3bmR8BG lzUg== X-Gm-Message-State: AJIora8XxENkALBi4/QBPedbr0a7oVG0YR/ET4NlvW58SwS8VxhQWm1j 30HG91LjN9saabnNrO+KLe4yHALBxHCX8Q== X-Google-Smtp-Source: AGRyM1vmH6Znx0Axapkde/ElA2i64xiW3vWzaylGxSm786yIVE9sy/zUKniI6kdYQVKNDR53yrHirg== X-Received: by 2002:a05:6a00:278c:b0:525:65c0:6415 with SMTP id bd12-20020a056a00278c00b0052565c06415mr1455052pfb.33.1656390374005; Mon, 27 Jun 2022 21:26:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 45/45] linux-user/aarch64: Add SME related hwcap entries Date: Tue, 28 Jun 2022 09:51:17 +0530 Message-Id: <20220628042117.368549-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628042117.368549-1-richard.henderson@linaro.org> References: <20220628042117.368549-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1656396362633100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/elfload.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 163fc8a1ee..a496c37855 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -605,6 +605,18 @@ enum { ARM_HWCAP2_A64_RNG =3D 1 << 16, ARM_HWCAP2_A64_BTI =3D 1 << 17, ARM_HWCAP2_A64_MTE =3D 1 << 18, + ARM_HWCAP2_A64_ECV =3D 1 << 19, + ARM_HWCAP2_A64_AFP =3D 1 << 20, + ARM_HWCAP2_A64_RPRES =3D 1 << 21, + ARM_HWCAP2_A64_MTE3 =3D 1 << 22, + ARM_HWCAP2_A64_SME =3D 1 << 23, + ARM_HWCAP2_A64_SME_I16I64 =3D 1 << 24, + ARM_HWCAP2_A64_SME_F64F64 =3D 1 << 25, + ARM_HWCAP2_A64_SME_I8I32 =3D 1 << 26, + ARM_HWCAP2_A64_SME_F16F32 =3D 1 << 27, + ARM_HWCAP2_A64_SME_B16F32 =3D 1 << 28, + ARM_HWCAP2_A64_SME_F32F32 =3D 1 << 29, + ARM_HWCAP2_A64_SME_FA64 =3D 1 << 30, }; =20 #define ELF_HWCAP get_elf_hwcap() @@ -674,6 +686,14 @@ static uint32_t get_elf_hwcap2(void) GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG); GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI); GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE); + GET_FEATURE_ID(aa64_sme, (ARM_HWCAP2_A64_SME | + ARM_HWCAP2_A64_SME_F32F32 | + ARM_HWCAP2_A64_SME_B16F32 | + ARM_HWCAP2_A64_SME_F16F32 | + ARM_HWCAP2_A64_SME_I8I32)); + GET_FEATURE_ID(aa64_sme_f64f64, ARM_HWCAP2_A64_SME_F64F64); + GET_FEATURE_ID(aa64_sme_i16i64, ARM_HWCAP2_A64_SME_I16I64); + GET_FEATURE_ID(aa64_sme_fa64, ARM_HWCAP2_A64_SME_FA64); =20 return hwcaps; } --=20 2.34.1