From nobody Tue Feb 10 12:09:33 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656345234788565.7781496974196; Mon, 27 Jun 2022 08:53:54 -0700 (PDT) Received: from localhost ([::1]:40360 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o5r3h-0003Vt-Ps for importer@patchew.org; Mon, 27 Jun 2022 11:53:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43220) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o5qxn-0001RP-Jy; Mon, 27 Jun 2022 11:47:47 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:57702) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1o5qxl-0005et-8U; Mon, 27 Jun 2022 11:47:47 -0400 Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 27 Jun 2022 08:47:42 -0700 Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2022 08:47:42 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 27 Jun 2022 08:47:42 -0700 Received: from maru.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 27 Jun 2022 08:47:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1656344865; x=1687880865; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Y09mCb5si9Qj7bmCcbC9RswbhEYEXytjucZp5yK9lbo=; b=udbBe35HcpCcE4ehh76fFtqGyQdT5HqVjoy3mJ4uYqLj8av7SqTdY6eu QPHafM4UjJW6hzYHzf+6IixH50dNV6nOssuGYYyAzaPU1HSSdA5r+vuWV ed1+oNcmnBNZUD99oTYdqQluXNikLnL1v/G/HYioRMJT4+J5iuDkXy6wN c=; X-QCInternal: smtphost From: Jae Hyun Yoo To: Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Titus Rwantare , Andrew Jeffery , Joel Stanley , Patrick Venture , Hao Wu CC: Graeme Gregory , Maheswara Kurapati , Jae Hyun Yoo , , Subject: [PATCH v2 7/7] hw/arm/aspeed: firework: add I2C MUXes for VR channels Date: Mon, 27 Jun 2022 08:47:03 -0700 Message-ID: <20220627154703.148943-8-quic_jaehyoo@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627154703.148943-1-quic_jaehyoo@quicinc.com> References: <20220627154703.148943-1-quic_jaehyoo@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=quic_jaehyoo@quicinc.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1656345235284100001 Content-Type: text/plain; charset="utf-8" Add 2-level cascaded I2C MUXes for SOC VR channels into the Firework machine. Signed-off-by: Jae Hyun Yoo Reviewed-by: C=C3=A9dric Le Goater --- Changes in v2: * None hw/arm/aspeed.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index cfc322ee30e9..1708a8f3408d 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1002,13 +1002,21 @@ static void qcom_dc_scm_bmc_i2c_init(AspeedMachineS= tate *bmc) static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc =3D &bmc->soc; - I2CSlave *therm_mux; + I2CSlave *therm_mux, *cpuvr_mux; =20 /* Create the generic DC-SCM hardware */ qcom_dc_scm_bmc_i2c_init(bmc); =20 /* Now create the Firework specific hardware */ =20 + /* I2C7 CPUVR MUX */ + cpuvr_mux =3D i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), + "pca9546", 0x70); + i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", = 0x72); + i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", = 0x72); + i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", = 0x72); + i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", = 0x72); + /* I2C8 Thermal Diodes*/ therm_mux =3D i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9548", 0x70); --=20 2.25.1