From nobody Tue Feb 10 19:17:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656345224716326.57726009590885; Mon, 27 Jun 2022 08:53:44 -0700 (PDT) Received: from localhost ([::1]:39564 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o5r3W-0002yk-Qm for importer@patchew.org; Mon, 27 Jun 2022 11:53:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43230) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o5qxo-0001SW-7b; Mon, 27 Jun 2022 11:47:48 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:49002) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1o5qxl-0005eI-99; Mon, 27 Jun 2022 11:47:47 -0400 Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-01.qualcomm.com with ESMTP; 27 Jun 2022 08:47:37 -0700 Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2022 08:47:36 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 27 Jun 2022 08:47:36 -0700 Received: from maru.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 27 Jun 2022 08:47:34 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1656344865; x=1687880865; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wlE4/kRVP+JrOBEciIqPQfCAOuGeAuBM13j3gCsmiyw=; b=XPI01AHCHUzNCYyXldCXSh2yJ1IiLilqkQi5XCBpefpsr5OTquLFOBMx ck/aQ9256sEqLOtz5U9FHiY+BDYv2diPaOdQ6EdqXif8fIs6Saz0Cr7CR 8pt5mJKDwSGLdCk2IXTeekum5CinwgNz9caSLZM56DQusU9WnNfC9TB1J 0=; X-QCInternal: smtphost From: Jae Hyun Yoo To: Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Titus Rwantare , Andrew Jeffery , Joel Stanley , Patrick Venture , Hao Wu CC: Graeme Gregory , Maheswara Kurapati , Jae Hyun Yoo , , Subject: [PATCH v2 1/7] hw/arm/aspeed: add support for the Qualcomm DC-SCM v1 board Date: Mon, 27 Jun 2022 08:46:57 -0700 Message-ID: <20220627154703.148943-2-quic_jaehyoo@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627154703.148943-1-quic_jaehyoo@quicinc.com> References: <20220627154703.148943-1-quic_jaehyoo@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=quic_jaehyoo@quicinc.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1656345225412100001 Content-Type: text/plain; charset="utf-8" Add qcom-dc-scm-v1 board support. Signed-off-by: Jae Hyun Yoo Reviewed-by: C=C3=A9dric Le Goater --- Changes in v2: * Fixed a typo in HW strap value comment. (Rebecca) * Removed a useless change which is reverted by the next patch. (Joel) hw/arm/aspeed.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 98dc185acd9a..cb7d99513816 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -174,6 +174,10 @@ struct AspeedMachineState { #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 =20 +/* Qualcomm DC-SCM hardware value */ +#define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 +#define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 + /* * The max ram region is for firmwares that scan the address space * with load/store to guess how much RAM the SoC has. @@ -988,6 +992,13 @@ static void fby35_i2c_init(AspeedMachineState *bmc) */ } =20 +static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc =3D &bmc->soc; + + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0= x4d); +} + static bool aspeed_get_mmio_exec(Object *obj, Error **errp) { return ASPEED_MACHINE(obj)->mmio_exec; @@ -1420,6 +1431,26 @@ static void aspeed_minibmc_machine_ast1030_evb_class= _init(ObjectClass *oc, amc->macs_mask =3D 0; } =20 +static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, + void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "Qualcomm DC-SCM V1 BMC (Cortex A7)"; + amc->soc_name =3D "ast2600-a3"; + amc->hw_strap1 =3D QCOM_DC_SCM_V1_BMC_HW_STRAP1; + amc->hw_strap2 =3D QCOM_DC_SCM_V1_BMC_HW_STRAP2; + amc->fmc_model =3D "n25q512a"; + amc->spi_model =3D "n25q512a"; + amc->num_cs =3D 2; + amc->macs_mask =3D ASPEED_MAC2_ON | ASPEED_MAC3_ON; + amc->i2c_init =3D qcom_dc_scm_bmc_i2c_init; + mc->default_ram_size =3D 1 * GiB; + mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D + aspeed_soc_num_cpus(amc->soc_name); +}; + static const TypeInfo aspeed_machine_types[] =3D { { .name =3D MACHINE_TYPE_NAME("palmetto-bmc"), @@ -1457,6 +1488,10 @@ static const TypeInfo aspeed_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("g220a-bmc"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_g220a_class_init, + }, { + .name =3D MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_qcom_dc_scm_v1_class_init, }, { .name =3D MACHINE_TYPE_NAME("fp5280g2-bmc"), .parent =3D TYPE_ASPEED_MACHINE, --=20 2.25.1