From nobody Sat May 18 06:04:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656345224716326.57726009590885; Mon, 27 Jun 2022 08:53:44 -0700 (PDT) Received: from localhost ([::1]:39564 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o5r3W-0002yk-Qm for importer@patchew.org; Mon, 27 Jun 2022 11:53:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43230) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o5qxo-0001SW-7b; Mon, 27 Jun 2022 11:47:48 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:49002) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1o5qxl-0005eI-99; Mon, 27 Jun 2022 11:47:47 -0400 Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-01.qualcomm.com with ESMTP; 27 Jun 2022 08:47:37 -0700 Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2022 08:47:36 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 27 Jun 2022 08:47:36 -0700 Received: from maru.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 27 Jun 2022 08:47:34 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1656344865; x=1687880865; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wlE4/kRVP+JrOBEciIqPQfCAOuGeAuBM13j3gCsmiyw=; b=XPI01AHCHUzNCYyXldCXSh2yJ1IiLilqkQi5XCBpefpsr5OTquLFOBMx ck/aQ9256sEqLOtz5U9FHiY+BDYv2diPaOdQ6EdqXif8fIs6Saz0Cr7CR 8pt5mJKDwSGLdCk2IXTeekum5CinwgNz9caSLZM56DQusU9WnNfC9TB1J 0=; X-QCInternal: smtphost From: Jae Hyun Yoo To: Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Titus Rwantare , Andrew Jeffery , Joel Stanley , Patrick Venture , Hao Wu CC: Graeme Gregory , Maheswara Kurapati , Jae Hyun Yoo , , Subject: [PATCH v2 1/7] hw/arm/aspeed: add support for the Qualcomm DC-SCM v1 board Date: Mon, 27 Jun 2022 08:46:57 -0700 Message-ID: <20220627154703.148943-2-quic_jaehyoo@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627154703.148943-1-quic_jaehyoo@quicinc.com> References: <20220627154703.148943-1-quic_jaehyoo@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=quic_jaehyoo@quicinc.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1656345225412100001 Content-Type: text/plain; charset="utf-8" Add qcom-dc-scm-v1 board support. Signed-off-by: Jae Hyun Yoo Reviewed-by: C=C3=A9dric Le Goater --- Changes in v2: * Fixed a typo in HW strap value comment. (Rebecca) * Removed a useless change which is reverted by the next patch. (Joel) hw/arm/aspeed.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 98dc185acd9a..cb7d99513816 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -174,6 +174,10 @@ struct AspeedMachineState { #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 =20 +/* Qualcomm DC-SCM hardware value */ +#define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 +#define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 + /* * The max ram region is for firmwares that scan the address space * with load/store to guess how much RAM the SoC has. @@ -988,6 +992,13 @@ static void fby35_i2c_init(AspeedMachineState *bmc) */ } =20 +static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc =3D &bmc->soc; + + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0= x4d); +} + static bool aspeed_get_mmio_exec(Object *obj, Error **errp) { return ASPEED_MACHINE(obj)->mmio_exec; @@ -1420,6 +1431,26 @@ static void aspeed_minibmc_machine_ast1030_evb_class= _init(ObjectClass *oc, amc->macs_mask =3D 0; } =20 +static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, + void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "Qualcomm DC-SCM V1 BMC (Cortex A7)"; + amc->soc_name =3D "ast2600-a3"; + amc->hw_strap1 =3D QCOM_DC_SCM_V1_BMC_HW_STRAP1; + amc->hw_strap2 =3D QCOM_DC_SCM_V1_BMC_HW_STRAP2; + amc->fmc_model =3D "n25q512a"; + amc->spi_model =3D "n25q512a"; + amc->num_cs =3D 2; + amc->macs_mask =3D ASPEED_MAC2_ON | ASPEED_MAC3_ON; + amc->i2c_init =3D qcom_dc_scm_bmc_i2c_init; + mc->default_ram_size =3D 1 * GiB; + mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D + aspeed_soc_num_cpus(amc->soc_name); +}; + static const TypeInfo aspeed_machine_types[] =3D { { .name =3D MACHINE_TYPE_NAME("palmetto-bmc"), @@ -1457,6 +1488,10 @@ static const TypeInfo aspeed_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("g220a-bmc"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_g220a_class_init, + }, { + .name =3D MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_qcom_dc_scm_v1_class_init, }, { .name =3D MACHINE_TYPE_NAME("fp5280g2-bmc"), .parent =3D TYPE_ASPEED_MACHINE, --=20 2.25.1 From nobody Sat May 18 06:04:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16563453845041008.5195338434287; Mon, 27 Jun 2022 08:56:24 -0700 (PDT) Received: from localhost ([::1]:46510 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o5r67-0007fh-GR for importer@patchew.org; Mon, 27 Jun 2022 11:56:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43228) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o5qxn-0001RV-R5; Mon, 27 Jun 2022 11:47:47 -0400 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:30721) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1o5qxl-0005eM-5Q; Mon, 27 Jun 2022 11:47:47 -0400 Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 27 Jun 2022 08:47:37 -0700 Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2022 08:47:37 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 27 Jun 2022 08:47:37 -0700 Received: from maru.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 27 Jun 2022 08:47:35 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1656344865; x=1687880865; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bc1EQ1HHmWjIcNG6T1vJreDy+rpZiUs2yToN+Zr2a9w=; b=QTz1kf3IfhN+9EAN9C0RMIx4ULfXRUE96d4koKC1xHabWdZ5E1wxc/W3 shY7VzPjzKC251IhSus6Y3lWKzLc4uugRcVHiDWtXx+Oe5S/t/awP+BsS m7nFSVGJdjfpAABUPr7ZR+XNyg4w5djfkaVJW0Fv/jbSgTz4Alxp8Nt3e Y=; X-QCInternal: smtphost From: Jae Hyun Yoo To: Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Titus Rwantare , Andrew Jeffery , Joel Stanley , Patrick Venture , Hao Wu CC: Graeme Gregory , Maheswara Kurapati , Jae Hyun Yoo , , Subject: [PATCH v2 2/7] hw/arm/aspeed: add Qualcomm Firework BMC machine Date: Mon, 27 Jun 2022 08:46:58 -0700 Message-ID: <20220627154703.148943-3-quic_jaehyoo@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627154703.148943-1-quic_jaehyoo@quicinc.com> References: <20220627154703.148943-1-quic_jaehyoo@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=quic_jaehyoo@quicinc.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1656345385190100001 Content-Type: text/plain; charset="utf-8" From: Graeme Gregory Add base for Qualcomm Firework BMC machine. Signed-off-by: Graeme Gregory Signed-off-by: Jae Hyun Yoo Reviewed-by: C=C3=A9dric Le Goater --- Changes in v2: * Changed machine name to 'qcom-firework-bmc'. (Cedric) * Dropped FRU eeprom initialization part. (Patrick) hw/arm/aspeed.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index cb7d99513816..342cf39c9747 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -999,6 +999,16 @@ static void qcom_dc_scm_bmc_i2c_init(AspeedMachineStat= e *bmc) i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0= x4d); } =20 +static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc =3D &bmc->soc; + + /* Create the generic DC-SCM hardware */ + qcom_dc_scm_bmc_i2c_init(bmc); + + /* Now create the Firework specific hardware */ +} + static bool aspeed_get_mmio_exec(Object *obj, Error **errp) { return ASPEED_MACHINE(obj)->mmio_exec; @@ -1451,6 +1461,26 @@ static void aspeed_machine_qcom_dc_scm_v1_class_init= (ObjectClass *oc, aspeed_soc_num_cpus(amc->soc_name); }; =20 +static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, + void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; + amc->soc_name =3D "ast2600-a3"; + amc->hw_strap1 =3D QCOM_DC_SCM_V1_BMC_HW_STRAP1; + amc->hw_strap2 =3D QCOM_DC_SCM_V1_BMC_HW_STRAP2; + amc->fmc_model =3D "n25q512a"; + amc->spi_model =3D "n25q512a"; + amc->num_cs =3D 2; + amc->macs_mask =3D ASPEED_MAC2_ON | ASPEED_MAC3_ON; + amc->i2c_init =3D qcom_dc_scm_firework_i2c_init; + mc->default_ram_size =3D 1 * GiB; + mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D + aspeed_soc_num_cpus(amc->soc_name); +}; + static const TypeInfo aspeed_machine_types[] =3D { { .name =3D MACHINE_TYPE_NAME("palmetto-bmc"), @@ -1492,6 +1522,10 @@ static const TypeInfo aspeed_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_qcom_dc_scm_v1_class_init, + }, { + .name =3D MACHINE_TYPE_NAME("qcom-firework-bmc"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_qcom_firework_class_init, }, { .name =3D MACHINE_TYPE_NAME("fp5280g2-bmc"), .parent =3D TYPE_ASPEED_MACHINE, --=20 2.25.1 From nobody Sat May 18 06:04:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656345030524468.0993674233787; Mon, 27 Jun 2022 08:50:30 -0700 (PDT) Received: from localhost ([::1]:59380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o5r0P-0005in-3F for importer@patchew.org; Mon, 27 Jun 2022 11:50:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43224) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o5qxn-0001RQ-Mj; Mon, 27 Jun 2022 11:47:47 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:56387) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1o5qxk-0005eX-W8; Mon, 27 Jun 2022 11:47:47 -0400 Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 27 Jun 2022 08:47:38 -0700 Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2022 08:47:38 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 27 Jun 2022 08:47:38 -0700 Received: from maru.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 27 Jun 2022 08:47:36 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1656344865; x=1687880865; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZLvNBZesMKm1d1lMIiQZJv24d4CCjd7V6YQR7jsGm3o=; b=mXXJdWzWysKkQaMWPNtB3dJwWNl7dSEuqk4VPl623QBiLTkjGcGrg4dW OiZwRTUNHqybRkMlnpvNr2SrhpJYyL1m0XQjslRzbKkLIhHsP1LDijcd7 H/dOT9tKdkw/ccgTSsOe9zgf1IaW+0BgTQ57yzmdmvzA0I8TtcT6vMcL1 s=; X-QCInternal: smtphost From: Jae Hyun Yoo To: Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Titus Rwantare , Andrew Jeffery , Joel Stanley , Patrick Venture , Hao Wu CC: Graeme Gregory , Maheswara Kurapati , Jae Hyun Yoo , , Subject: [PATCH v2 3/7] hw/i2c: pmbus: Page #255 is valid page for read requests. Date: Mon, 27 Jun 2022 08:46:59 -0700 Message-ID: <20220627154703.148943-4-quic_jaehyoo@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627154703.148943-1-quic_jaehyoo@quicinc.com> References: <20220627154703.148943-1-quic_jaehyoo@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.46.98.28; envelope-from=quic_jaehyoo@quicinc.com; helo=alexa-out.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1656345030943100001 Content-Type: text/plain; charset="utf-8" From: Maheswara Kurapati Current implementation of the pmbus core driver treats the read request for page 255 as invalid request and sets the invalid command bit (bit 7) in the STATUS_CML register. As per the PMBus specification it is a valid request. Refer to the PMBus specification, revision 1.3.1, section 11.10 PAGE, on the page 58: "Setting the PAGE to FFh means that all subsequent comands are to be applied to all outputs. Some commands, such as READ_TEMPERATURE, may use a common sensor but be available on all pages of a device. Such implementations are the decision of each device manufacturer or are specified in a PMBus Application Profile. Consult the manufacturer's documents or the Application Profile Specification as needed." For e.g., The VOUT_MODE is a valid command for page 255 for maxim 31785 device. refer to Table 1. PMBus Command Codes on page 14 in the datasheet. https://datasheets.maximintegrated.com/en/ds/MAX31785.pdf Fixes: 38870253f1d1 ("hw/i2c: pmbus: fix error returns and guard against ou= t of range accesses") Signed-off-by: Maheswara Kurapati Signed-off-by: Jae Hyun Yoo Reviewed-by: Titus Rwantare Reviewed-by: C=C3=A9dric Le Goater --- Changes in v2: * Fixed comment for a case of PB_ALL_PAGES. (Titus) * Removed an error log printing when it handles PB_ALL_PAGES. (Jae) hw/i2c/pmbus_device.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c index 62885fa6a15e..749a33af827b 100644 --- a/hw/i2c/pmbus_device.c +++ b/hw/i2c/pmbus_device.c @@ -284,14 +284,10 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd) =20 /* * Reading from all pages will return the value from page 0, - * this is unspecified behaviour in general. + * means that all subsequent commands are to be applied to all output. */ if (pmdev->page =3D=3D PB_ALL_PAGES) { index =3D 0; - qemu_log_mask(LOG_GUEST_ERROR, - "%s: tried to read from all pages\n", - __func__); - pmbus_cml_error(pmdev); } else if (pmdev->page > pmdev->num_pages - 1) { qemu_log_mask(LOG_GUEST_ERROR, "%s: page %d is out of range\n", --=20 2.25.1 From nobody Sat May 18 06:04:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=quic_jaehyoo@quicinc.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1656345225520100003 Content-Type: text/plain; charset="utf-8" From: Maheswara Kurapati MAX31785 is a PMBus compliant 6-Channel fan controller. It supports 6 fan channels, 11 temperature sensors, and 6-Channel ADC to measure the remote voltages. Datasheet can be found here: https://datasheets.maximintegrated.com/en/ds/MAX31785.pdf This initial version of the driver has skeleton and support for the fan channels. Requests for temperature sensors, and ADC Channels the are serviced with the default values as per the datasheet. No additional instrumentation is done. NV Log feature is not supported. Signed-off-by: Maheswara Kurapati Signed-off-by: Jae Hyun Yoo Reviewed-by: Joel Stanley Reviewed-by: C=C3=A9dric Le Goater --- Changes in v2: * Fixed a typo in copyright. (Rebecca) * Fixed indentation issues. (Titus) * Fixed license identifier style and refined indentation of defines. (Jae) hw/sensor/Kconfig | 4 + hw/sensor/max31785.c | 573 ++++++++++++++++++++++++++++++++++++++++++ hw/sensor/meson.build | 1 + 3 files changed, 578 insertions(+) create mode 100644 hw/sensor/max31785.c diff --git a/hw/sensor/Kconfig b/hw/sensor/Kconfig index df392e786904..e03bd09b50e8 100644 --- a/hw/sensor/Kconfig +++ b/hw/sensor/Kconfig @@ -34,3 +34,7 @@ config LSM303DLHC_MAG config ISL_PMBUS_VR bool depends on PMBUS + +config MAX31785 + bool + depends on PMBUS diff --git a/hw/sensor/max31785.c b/hw/sensor/max31785.c new file mode 100644 index 000000000000..8b95e324814b --- /dev/null +++ b/hw/sensor/max31785.c @@ -0,0 +1,573 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Maxim MAX31785 PMBus 6-Channel Fan Controller + * + * Datasheet: + * https://datasheets.maximintegrated.com/en/ds/MAX31785.pdf + * + * Copyright(c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "qemu/osdep.h" +#include "hw/i2c/pmbus_device.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "qemu/log.h" +#include "qemu/module.h" + +#define TYPE_MAX31785 "max31785" +#define MAX31785(obj) OBJECT_CHECK(MAX31785State, (obj), TYPE_MAX31785) + +/* MAX31785 mfr specific PMBus commands */ +#define MAX31785_MFR_MODE 0xD1 +#define MAX31785_MFR_PSEN_CONFIG 0xD2 +#define MAX31785_MFR_VOUT_PEAK 0xD4 +#define MAX31785_MFR_TEMPERATURE_PEAK 0xD6 +#define MAX31785_MFR_VOUT_MIN 0xD7 +#define MAX31785_MFR_FAULT_RESPONSE 0xD9 +#define MAX31785_MFR_NV_FAULT_LOG 0xDC +#define MAX31785_MFR_TIME_COUNT 0xDD +#define MAX31785_MFR_TEMP_SENSOR_CONFIG 0xF0 +#define MAX31785_MFR_FAN_CONFIG 0xF1 +#define MAX31785_MFR_FAN_LUT 0xF2 +#define MAX31785_MFR_READ_FAN_PWM 0xF3 +#define MAX31785_MFR_FAN_FAULT_LIMIT 0xF5 +#define MAX31785_MFR_FAN_WARN_LIMIT 0xF6 +#define MAX31785_MFR_FAN_RUN_TIME 0xF7 +#define MAX31785_MFR_FAN_PWM_AVG 0xF8 +#define MAX31785_MFR_FAN_PWM2RPM 0xF9 + +/* defaults as per the data sheet */ +#define MAX31785_DEFAULT_CAPABILITY 0x10 +#define MAX31785_DEFAULT_VOUT_MODE 0x40 +#define MAX31785_DEFAULT_VOUT_SCALE_MONITOR 0x7FFF +#define MAX31785_DEFAULT_FAN_COMMAND_1 0x7FFF +#define MAX31785_DEFAULT_OV_FAULT_LIMIT 0x7FFF +#define MAX31785_DEFAULT_OV_WARN_LIMIT 0x7FFF +#define MAX31785_DEFAULT_OT_FAULT_LIMIT 0x7FFF +#define MAX31785_DEFAULT_OT_WARN_LIMIT 0x7FFF +#define MAX31785_DEFAULT_PMBUS_REVISION 0x11 +#define MAX31785_DEFAULT_MFR_ID 0x4D +#define MAX31785_DEFAULT_MFR_MODEL 0x53 +#define MAX31785_DEFAULT_MFR_REVISION 0x3030 +#define MAX31785A_DEFAULT_MFR_REVISION 0x3040 +#define MAX31785B_DEFAULT_MFR_REVISION 0x3061 +#define MAX31785B_DEFAULT_MFR_TEMPERATURE_PEAK 0x8000 +#define MAX31785B_DEFAULT_MFR_VOUT_MIN 0x7FFF +#define MAX31785_DEFAULT_TEXT 0x3130313031303130 + +/* MAX31785 pages */ +#define MAX31785_TOTAL_NUM_PAGES 23 +#define MAX31785_FAN_PAGES 6 +#define MAX31785_MIN_FAN_PAGE 0 +#define MAX31785_MAX_FAN_PAGE 5 +#define MAX31785_MIN_TEMP_PAGE 6 +#define MAX31785_MAX_TEMP_PAGE 16 +#define MAX31785_MIN_ADC_VOLTAGE_PAGE 17 +#define MAX31785_MAX_ADC_VOLTAGE_PAGE 22 + +/* FAN_CONFIG_1_2 */ +#define MAX31785_MFR_FAN_CONFIG 0xF1 +#define MAX31785_FAN_CONFIG_ENABLE BIT(7) +#define MAX31785_FAN_CONFIG_RPM_PWM BIT(6) +#define MAX31785_FAN_CONFIG_PULSE(pulse) (pulse << 4) +#define MAX31785_DEFAULT_FAN_CONFIG_1_2(pulse) = \ + (MAX31785_FAN_CONFIG_ENABLE | MAX31785_FAN_CONFIG_PULSE(pulse)) +#define MAX31785_DEFAULT_MFR_FAN_CONFIG 0x0000 + +/* fan speed in RPM */ +#define MAX31785_DEFAULT_FAN_SPEED 0x7fff +#define MAX31785_DEFAULT_FAN_STATUS 0x00 + +#define MAX31785_DEFAULT_FAN_MAX_PWM 0x2710 + +/* + * MAX31785State: + * @code: The command code received + * @page: Each page corresponds to a device monitored by the Max 31785 + * The page register determines the available commands depending on device + * _______________________________________________________________________= ______ + * | 0 | Fan Connected to PWM0 = | + * |_______|______________________________________________________________= _____| + * | 1 | Fan Connected to PWM1 = | + * |_______|______________________________________________________________= _____| + * | 2 | Fan Connected to PWM2 = | + * |_______|______________________________________________________________= _____| + * | 3 | Fan Connected to PWM3 = | + * |_______|______________________________________________________________= _____| + * | 4 | Fan Connected to PWM4 = | + * |_______|______________________________________________________________= _____| + * | 5 | Fan Connected to PWM5 = | + * |_______|______________________________________________________________= _____| + * | 6 | Remote Thermal Diode Connected to ADC 0 = | + * |_______|______________________________________________________________= _____| + * | 7 | Remote Thermal Diode Connected to ADC 1 = | + * |_______|______________________________________________________________= _____| + * | 8 | Remote Thermal Diode Connected to ADC 2 = | + * |_______|______________________________________________________________= _____| + * | 9 | Remote Thermal Diode Connected to ADC 3 = | + * |_______|______________________________________________________________= _____| + * | 10 | Remote Thermal Diode Connected to ADC 4 = | + * |_______|______________________________________________________________= _____| + * | 11 | Remote Thermal Diode Connected to ADC 5 = | + * |_______|______________________________________________________________= _____| + * | 12 | Internal Temperature Sensor = | + * |_______|______________________________________________________________= _____| + * | 13 | Remote I2C Temperature Sensor with Address 0 = | + * |_______|______________________________________________________________= _____| + * | 14 | Remote I2C Temperature Sensor with Address 1 = | + * |_______|______________________________________________________________= _____| + * | 15 | Remote I2C Temperature Sensor with Address 2 = | + * |_______|______________________________________________________________= _____| + * | 16 | Remote I2C Temperature Sensor with Address 3 = | + * |_______|______________________________________________________________= _____| + * | 17 | Remote I2C Temperature Sensor with Address 4 = | + * |_______|______________________________________________________________= _____| + * | 17 | Remote Voltage Connected to ADC0 = | + * |_______|______________________________________________________________= _____| + * | 18 | Remote Voltage Connected to ADC1 = | + * |_______|______________________________________________________________= _____| + * | 19 | Remote Voltage Connected to ADC2 = | + * |_______|______________________________________________________________= _____| + * | 20 | Remote Voltage Connected to ADC3 = | + * |_______|______________________________________________________________= _____| + * | 21 | Remote Voltage Connected to ADC4 = | + * |_______|______________________________________________________________= _____| + * | 22 | Remote Voltage Connected to ADC5 = | + * |_______|______________________________________________________________= _____| + * |23-254 | Reserved = | + * |_______|______________________________________________________________= _____| + * | 255 | Applies to all pages = | + * |_______|______________________________________________________________= _____| + */ + +/* Place holder to save the max31785 mfr specific registers */ +typedef struct MAX31785State { + PMBusDevice parent; + uint16_t mfr_mode[MAX31785_TOTAL_NUM_PAGES]; + uint16_t vout_peak[MAX31785_TOTAL_NUM_PAGES]; + uint16_t temperature_peak[MAX31785_TOTAL_NUM_PAGES]; + uint16_t vout_min[MAX31785_TOTAL_NUM_PAGES]; + uint8_t fault_response[MAX31785_TOTAL_NUM_PAGES]; + uint32_t time_count[MAX31785_TOTAL_NUM_PAGES]; + uint16_t temp_sensor_config[MAX31785_TOTAL_NUM_PAGES]; + uint16_t fan_config[MAX31785_TOTAL_NUM_PAGES]; + uint16_t read_fan_pwm[MAX31785_TOTAL_NUM_PAGES]; + uint16_t fan_fault_limit[MAX31785_TOTAL_NUM_PAGES]; + uint16_t fan_warn_limit[MAX31785_TOTAL_NUM_PAGES]; + uint16_t fan_run_time[MAX31785_TOTAL_NUM_PAGES]; + uint16_t fan_pwm_avg[MAX31785_TOTAL_NUM_PAGES]; + uint64_t fan_pwm2rpm[MAX31785_TOTAL_NUM_PAGES]; + uint64_t mfr_location; + uint64_t mfr_date; + uint64_t mfr_serial; + uint16_t mfr_revision; +} MAX31785State; + +static uint8_t max31785_read_byte(PMBusDevice *pmdev) +{ + MAX31785State *s =3D MAX31785(pmdev); + switch (pmdev->code) { + + case PMBUS_FAN_CONFIG_1_2: + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + pmbus_send8(pmdev, pmdev->pages[pmdev->page].fan_config_1_2); + } + break; + + case PMBUS_FAN_COMMAND_1: + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + pmbus_send16(pmdev, pmdev->pages[pmdev->page].fan_command_1); + } + break; + + case PMBUS_READ_FAN_SPEED_1: + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + pmbus_send16(pmdev, pmdev->pages[pmdev->page].read_fan_speed_1= ); + } + break; + + case PMBUS_STATUS_FANS_1_2: + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + pmbus_send16(pmdev, pmdev->pages[pmdev->page].status_fans_1_2); + } + break; + + case PMBUS_MFR_REVISION: + pmbus_send16(pmdev, MAX31785_DEFAULT_MFR_REVISION); + break; + + case PMBUS_MFR_ID: + pmbus_send8(pmdev, 0x4d); /* Maxim */ + break; + + case PMBUS_MFR_MODEL: + pmbus_send8(pmdev, 0x53); + break; + + case PMBUS_MFR_LOCATION: + pmbus_send64(pmdev, s->mfr_location); + break; + + case PMBUS_MFR_DATE: + pmbus_send64(pmdev, s->mfr_date); + break; + + case PMBUS_MFR_SERIAL: + pmbus_send64(pmdev, s->mfr_serial); + break; + + case MAX31785_MFR_MODE: + pmbus_send16(pmdev, s->mfr_mode[pmdev->page]); + break; + + case MAX31785_MFR_VOUT_PEAK: + if ((pmdev->page >=3D MAX31785_MIN_ADC_VOLTAGE_PAGE) && + (pmdev->page <=3D MAX31785_MAX_ADC_VOLTAGE_PAGE)) { + pmbus_send16(pmdev, s->vout_peak[pmdev->page]); + } + break; + + case MAX31785_MFR_TEMPERATURE_PEAK: + if ((pmdev->page >=3D MAX31785_MIN_TEMP_PAGE) && + (pmdev->page <=3D MAX31785_MAX_TEMP_PAGE)) { + pmbus_send16(pmdev, s->temperature_peak[pmdev->page]); + } + break; + + case MAX31785_MFR_VOUT_MIN: + if ((pmdev->page >=3D MAX31785_MIN_ADC_VOLTAGE_PAGE) && + (pmdev->page <=3D MAX31785_MAX_ADC_VOLTAGE_PAGE)) { + pmbus_send16(pmdev, s->vout_min[pmdev->page]); + } + break; + + case MAX31785_MFR_FAULT_RESPONSE: + pmbus_send8(pmdev, s->fault_response[pmdev->page]); + break; + + case MAX31785_MFR_TIME_COUNT: /* R/W 32 */ + pmbus_send32(pmdev, s->time_count[pmdev->page]); + break; + + case MAX31785_MFR_TEMP_SENSOR_CONFIG: /* R/W 16 */ + if ((pmdev->page >=3D MAX31785_MIN_TEMP_PAGE) && + (pmdev->page <=3D MAX31785_MAX_TEMP_PAGE)) { + pmbus_send16(pmdev, s->temp_sensor_config[pmdev->page]); + } + break; + + case MAX31785_MFR_FAN_CONFIG: /* R/W 16 */ + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + pmbus_send16(pmdev, s->fan_config[pmdev->page]); + } + break; + + case MAX31785_MFR_READ_FAN_PWM: /* R/W 16 */ + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + pmbus_send16(pmdev, s->read_fan_pwm[pmdev->page]); + } + break; + + case MAX31785_MFR_FAN_FAULT_LIMIT: /* R/W 16 */ + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + pmbus_send16(pmdev, s->fan_fault_limit[pmdev->page]); + } + break; + + case MAX31785_MFR_FAN_WARN_LIMIT: /* R/W 16 */ + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + pmbus_send16(pmdev, s->fan_warn_limit[pmdev->page]); + } + break; + + case MAX31785_MFR_FAN_RUN_TIME: /* R/W 16 */ + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + pmbus_send16(pmdev, s->fan_run_time[pmdev->page]); + } + break; + + case MAX31785_MFR_FAN_PWM_AVG: /* R/W 16 */ + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + pmbus_send16(pmdev, s->fan_pwm_avg[pmdev->page]); + } + break; + + case MAX31785_MFR_FAN_PWM2RPM: /* R/W 64 */ + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + pmbus_send64(pmdev, s->fan_pwm2rpm[pmdev->page]); + } + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: reading from unsupported register: 0x%02x\n", + __func__, pmdev->code); + break; + } + + return 0xFF; +} + +static int max31785_write_data(PMBusDevice *pmdev, const uint8_t *buf, + uint8_t len) +{ + MAX31785State *s =3D MAX31785(pmdev); + if (len =3D=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: writing empty data\n", __func_= _); + return -1; + } + + pmdev->code =3D buf[0]; /* PMBus command code */ + + if (len =3D=3D 1) { + return 0; + } + + /* Exclude command code from buffer */ + buf++; + len--; + + switch (pmdev->code) { + + case PMBUS_FAN_CONFIG_1_2: + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + pmdev->pages[pmdev->page].fan_config_1_2 =3D pmbus_receive8(pm= dev); + } + break; + + case PMBUS_FAN_COMMAND_1: + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + pmdev->pages[pmdev->page].fan_command_1 =3D pmbus_receive16(pm= dev); + pmdev->pages[pmdev->page].read_fan_speed_1 =3D + ((MAX31785_DEFAULT_FAN_SPEED / MAX31785_DEFAULT_FAN_MAX_PW= M) * + pmdev->pages[pmdev->page].fan_command_1); + } + break; + + case PMBUS_MFR_LOCATION: /* R/W 64 */ + s->mfr_location =3D pmbus_receive64(pmdev); + break; + + case PMBUS_MFR_DATE: /* R/W 64 */ + s->mfr_date =3D pmbus_receive64(pmdev); + break; + + case PMBUS_MFR_SERIAL: /* R/W 64 */ + s->mfr_serial =3D pmbus_receive64(pmdev); + break; + + case MAX31785_MFR_MODE: /* R/W word */ + s->mfr_mode[pmdev->page] =3D pmbus_receive16(pmdev); + break; + + case MAX31785_MFR_VOUT_PEAK: /* R/W word */ + if ((pmdev->page >=3D MAX31785_MIN_ADC_VOLTAGE_PAGE) && + (pmdev->page <=3D MAX31785_MAX_ADC_VOLTAGE_PAGE)) { + s->vout_peak[pmdev->page] =3D pmbus_receive16(pmdev); + } + break; + + case MAX31785_MFR_TEMPERATURE_PEAK: /* R/W word */ + if ((pmdev->page >=3D 6) && (pmdev->page <=3D 16)) { + s->temperature_peak[pmdev->page] =3D pmbus_receive16(pmdev); + } + break; + + case MAX31785_MFR_VOUT_MIN: /* R/W word */ + if ((pmdev->page >=3D MAX31785_MIN_ADC_VOLTAGE_PAGE) && + (pmdev->page <=3D MAX31785_MAX_ADC_VOLTAGE_PAGE)) { + s->vout_min[pmdev->page] =3D pmbus_receive16(pmdev); + } + break; + + case MAX31785_MFR_FAULT_RESPONSE: /* R/W 8 */ + s->fault_response[pmdev->page] =3D pmbus_receive8(pmdev); + break; + + case MAX31785_MFR_TIME_COUNT: /* R/W 32 */ + s->time_count[pmdev->page] =3D pmbus_receive32(pmdev); + break; + + case MAX31785_MFR_TEMP_SENSOR_CONFIG: /* R/W 16 */ + if ((pmdev->page >=3D MAX31785_MIN_TEMP_PAGE) && + (pmdev->page <=3D MAX31785_MAX_TEMP_PAGE)) { + s->temp_sensor_config[pmdev->page] =3D pmbus_receive16(pmdev); + } + break; + + case MAX31785_MFR_FAN_CONFIG: /* R/W 16 */ + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + s->fan_config[pmdev->page] =3D pmbus_receive16(pmdev); + } + break; + + case MAX31785_MFR_FAN_FAULT_LIMIT: /* R/W 16 */ + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + s->fan_fault_limit[pmdev->page] =3D pmbus_receive16(pmdev); + } + break; + + case MAX31785_MFR_FAN_WARN_LIMIT: /* R/W 16 */ + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + s->fan_warn_limit[pmdev->page] =3D pmbus_receive16(pmdev); + } + break; + + case MAX31785_MFR_FAN_RUN_TIME: /* R/W 16 */ + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + s->fan_run_time[pmdev->page] =3D pmbus_receive16(pmdev); + } + break; + + case MAX31785_MFR_FAN_PWM_AVG: /* R/W 16 */ + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + s->fan_pwm_avg[pmdev->page] =3D pmbus_receive16(pmdev); + } + break; + + case MAX31785_MFR_FAN_PWM2RPM: /* R/W 64 */ + if (pmdev->page <=3D MAX31785_MAX_FAN_PAGE) { + s->fan_pwm2rpm[pmdev->page] =3D pmbus_receive64(pmdev); + } + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: writing to unsupported register: 0x%02x\n", + __func__, pmdev->code); + break; + } + + return 0; +} + +static void max31785_exit_reset(Object *obj) +{ + PMBusDevice *pmdev =3D PMBUS_DEVICE(obj); + MAX31785State *s =3D MAX31785(obj); + + pmdev->capability =3D MAX31785_DEFAULT_CAPABILITY; + + for (int i =3D MAX31785_MIN_FAN_PAGE; i <=3D MAX31785_MAX_FAN_PAGE; i+= +) { + pmdev->pages[i].vout_mode =3D MAX31785_DEFAULT_VOUT_MODE; + pmdev->pages[i].fan_command_1 =3D MAX31785_DEFAULT_FAN_COMMAND_1; + pmdev->pages[i].revision =3D MAX31785_DEFAULT_PMBUS_REVISION; + pmdev->pages[i].fan_config_1_2 =3D MAX31785_DEFAULT_FAN_CONFIG_1_2= (0); + pmdev->pages[i].read_fan_speed_1 =3D MAX31785_DEFAULT_FAN_SPEED; + pmdev->pages[i].status_fans_1_2 =3D MAX31785_DEFAULT_FAN_STATUS; + } + + for (int i =3D MAX31785_MIN_TEMP_PAGE; i <=3D MAX31785_MAX_TEMP_PAGE; = i++) { + pmdev->pages[i].vout_mode =3D MAX31785_DEFAULT_VOUT_MODE; + pmdev->pages[i].revision =3D MAX31785_DEFAULT_PMBUS_REVISION; + pmdev->pages[i].ot_fault_limit =3D MAX31785_DEFAULT_OT_FAULT_LIMIT; + pmdev->pages[i].ot_warn_limit =3D MAX31785_DEFAULT_OT_WARN_LIMIT; + } + + for (int i =3D MAX31785_MIN_ADC_VOLTAGE_PAGE; + i <=3D MAX31785_MAX_ADC_VOLTAGE_PAGE; + i++) { + pmdev->pages[i].vout_mode =3D MAX31785_DEFAULT_VOUT_MODE; + pmdev->pages[i].revision =3D MAX31785_DEFAULT_PMBUS_REVISION; + pmdev->pages[i].vout_scale_monitor =3D + MAX31785_DEFAULT_VOUT_SCALE_MONITOR; + pmdev->pages[i].vout_ov_fault_limit =3D MAX31785_DEFAULT_OV_FAULT_= LIMIT; + pmdev->pages[i].vout_ov_warn_limit =3D MAX31785_DEFAULT_OV_WARN_LI= MIT; + } + + s->mfr_location =3D MAX31785_DEFAULT_TEXT; + s->mfr_date =3D MAX31785_DEFAULT_TEXT; + s->mfr_serial =3D MAX31785_DEFAULT_TEXT; +} + +static const VMStateDescription vmstate_max31785 =3D { + .name =3D TYPE_MAX31785, + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]){ + VMSTATE_PMBUS_DEVICE(parent, MAX31785State), + VMSTATE_UINT16_ARRAY(mfr_mode, MAX31785State, + MAX31785_TOTAL_NUM_PAGES), + VMSTATE_UINT16_ARRAY(vout_peak, MAX31785State, + MAX31785_TOTAL_NUM_PAGES), + VMSTATE_UINT16_ARRAY(temperature_peak, MAX31785State, + MAX31785_TOTAL_NUM_PAGES), + VMSTATE_UINT16_ARRAY(vout_min, MAX31785State, + MAX31785_TOTAL_NUM_PAGES), + VMSTATE_UINT8_ARRAY(fault_response, MAX31785State, + MAX31785_TOTAL_NUM_PAGES), + VMSTATE_UINT32_ARRAY(time_count, MAX31785State, + MAX31785_TOTAL_NUM_PAGES), + VMSTATE_UINT16_ARRAY(temp_sensor_config, MAX31785State, + MAX31785_TOTAL_NUM_PAGES), + VMSTATE_UINT16_ARRAY(fan_config, MAX31785State, + MAX31785_TOTAL_NUM_PAGES), + VMSTATE_UINT16_ARRAY(read_fan_pwm, MAX31785State, + MAX31785_TOTAL_NUM_PAGES), + VMSTATE_UINT16_ARRAY(fan_fault_limit, MAX31785State, + MAX31785_TOTAL_NUM_PAGES), + VMSTATE_UINT16_ARRAY(fan_warn_limit, MAX31785State, + MAX31785_TOTAL_NUM_PAGES), + VMSTATE_UINT16_ARRAY(fan_run_time, MAX31785State, + MAX31785_TOTAL_NUM_PAGES), + VMSTATE_UINT16_ARRAY(fan_pwm_avg, MAX31785State, + MAX31785_TOTAL_NUM_PAGES), + VMSTATE_UINT64_ARRAY(fan_pwm2rpm, MAX31785State, + MAX31785_TOTAL_NUM_PAGES), + VMSTATE_UINT64(mfr_location, MAX31785State), + VMSTATE_UINT64(mfr_date, MAX31785State), + VMSTATE_UINT64(mfr_serial, MAX31785State), + VMSTATE_END_OF_LIST() + } +}; + +static void max31785_init(Object *obj) +{ + PMBusDevice *pmdev =3D PMBUS_DEVICE(obj); + + for (int i =3D MAX31785_MIN_FAN_PAGE; i <=3D MAX31785_MAX_FAN_PAGE; i+= +) { + pmbus_page_config(pmdev, i, PB_HAS_VOUT_MODE); + } + + for (int i =3D MAX31785_MIN_TEMP_PAGE; i <=3D MAX31785_MAX_TEMP_PAGE; = i++) { + pmbus_page_config(pmdev, i, PB_HAS_VOUT_MODE | PB_HAS_TEMPERATURE); + } + + for (int i =3D MAX31785_MIN_ADC_VOLTAGE_PAGE; + i <=3D MAX31785_MAX_ADC_VOLTAGE_PAGE; + i++) { + pmbus_page_config(pmdev, i, PB_HAS_VOUT_MODE | PB_HAS_VOUT | + PB_HAS_VOUT_RATING); + } +} + +static void max31785_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + PMBusDeviceClass *k =3D PMBUS_DEVICE_CLASS(klass); + dc->desc =3D "Maxim MAX31785 6-Channel Fan Controller"; + dc->vmsd =3D &vmstate_max31785; + k->write_data =3D max31785_write_data; + k->receive_byte =3D max31785_read_byte; + k->device_num_pages =3D MAX31785_TOTAL_NUM_PAGES; + rc->phases.exit =3D max31785_exit_reset; +} + +static const TypeInfo max31785_info =3D { + .name =3D TYPE_MAX31785, + .parent =3D TYPE_PMBUS_DEVICE, + .instance_size =3D sizeof(MAX31785State), + .instance_init =3D max31785_init, + .class_init =3D max31785_class_init, +}; + +static void max31785_register_types(void) +{ + type_register_static(&max31785_info); +} + +type_init(max31785_register_types) diff --git a/hw/sensor/meson.build b/hw/sensor/meson.build index 12b6992bc845..9e9be602c349 100644 --- a/hw/sensor/meson.build +++ b/hw/sensor/meson.build @@ -6,3 +6,4 @@ softmmu_ss.add(when: 'CONFIG_ADM1272', if_true: files('adm1= 272.c')) softmmu_ss.add(when: 'CONFIG_MAX34451', if_true: files('max34451.c')) softmmu_ss.add(when: 'CONFIG_LSM303DLHC_MAG', if_true: files('lsm303dlhc_m= ag.c')) softmmu_ss.add(when: 'CONFIG_ISL_PMBUS_VR', if_true: files('isl_pmbus_vr.c= ')) +softmmu_ss.add(when: 'CONFIG_MAX31785', if_true: files('max31785.c')) --=20 2.25.1 From nobody Sat May 18 06:04:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656345031622151.96010158296156; Mon, 27 Jun 2022 08:50:31 -0700 (PDT) Received: from localhost ([::1]:59472 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o5r0P-0005mM-Ox for importer@patchew.org; Mon, 27 Jun 2022 11:50:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43226) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o5qxn-0001RR-Od; Mon, 27 Jun 2022 11:47:47 -0400 Received: from alexa-out-sd-01.qualcomm.com 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d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1656344865; x=1687880865; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vdIIQ9ElArb+NfOpDKz5lfW+JLjfm9DYtGhd+ys4DbQ=; b=AjrV/MgFRq+vWhopOxESIUZgkSbN9FxiDc989s2u4v+8FdDIFz1wmaLd zm7rp2GXplHC+I6T163KaR8XFVg1A/8Xn4xiKXDYS+qrEGJAOgl11K6Ue 1/0oyphUmi0ghhRIv9ME4QkT0fj0/KrWatmmPCFBVAAZtrhCVoFpO1vrs 4=; X-QCInternal: smtphost From: Jae Hyun Yoo To: Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Titus Rwantare , Andrew Jeffery , Joel Stanley , Patrick Venture , Hao Wu CC: Graeme Gregory , Maheswara Kurapati , Jae Hyun Yoo , , Subject: [PATCH v2 5/7] hw/arm/aspeed: Add MAX31785 Fan controllers Date: Mon, 27 Jun 2022 08:47:01 -0700 Message-ID: <20220627154703.148943-6-quic_jaehyoo@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627154703.148943-1-quic_jaehyoo@quicinc.com> References: <20220627154703.148943-1-quic_jaehyoo@quicinc.com> MIME-Version: 1.0 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Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1656345032867100003 Content-Type: text/plain; charset="utf-8" From: Maheswara Kurapati Add MAX31785 fan controllers in machines so that the Linux driver populates the sysfs interface. Firework has two MAX31785 Fan controllers at 0x52, and 0x54 on bus 9. Witherspoon has one at 0x52 on bus 3. Rainier has one at 0x52 on bus 7. Signed-off-by: Maheswara Kurapati Signed-off-by: Jae Hyun Yoo Reviewed-by: C=C3=A9dric Le Goater --- Changes in v2: * Added PMBUS and MAX31785 config selection under ASPEED_SOC. (Titus) * Moved machine updating part from the previous patch. (Cedric) hw/arm/Kconfig | 2 ++ hw/arm/aspeed.c | 8 ++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 219262a8da36..15fa79afd33a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -455,6 +455,8 @@ config ASPEED_SOC select EMC141X select UNIMP select LED + select PMBUS + select MAX31785 =20 config MPS2 bool diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 342cf39c9747..9c07db70f2fc 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -619,7 +619,6 @@ static void witherspoon_bmc_i2c_init(AspeedMachineState= *bmc) LEDState *led; =20 /* Bus 3: TODO bmp280@77 */ - /* Bus 3: TODO max31785@52 */ dev =3D DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); qdev_prop_set_string(dev, "description", "pca1"); i2c_slave_realize_and_unref(I2C_SLAVE(dev), @@ -635,6 +634,7 @@ static void witherspoon_bmc_i2c_init(AspeedMachineState= *bmc) qdev_get_gpio_in(DEVICE(led), 0)); } i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x= 76); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", = 0x52); i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x= 4c); i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x= 4c); =20 @@ -779,13 +779,13 @@ static void rainier_bmc_i2c_init(AspeedMachineState *= bmc) create_pca9552(soc, 7, 0x31); create_pca9552(soc, 7, 0x32); create_pca9552(soc, 7, 0x33); - /* Bus 7: TODO max31785@52 */ create_pca9552(soc, 7, 0x60); create_pca9552(soc, 7, 0x61); i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x= 76); /* Bus 7: TODO si7021-a20@20 */ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 0x48); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", = 0x52); aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); =20 @@ -1007,6 +1007,10 @@ static void qcom_dc_scm_firework_i2c_init(AspeedMach= ineState *bmc) qcom_dc_scm_bmc_i2c_init(bmc); =20 /* Now create the Firework specific hardware */ + + /* I2C9 Fan Controller (MAX31785) */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", = 0x52); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", = 0x54); } =20 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) --=20 2.25.1 From nobody Sat May 18 06:04:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165634505372528.743897716586616; Mon, 27 Jun 2022 08:50:53 -0700 (PDT) Received: from localhost ([::1]:60096 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o5r0l-0006BG-NF for importer@patchew.org; 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Mon, 27 Jun 2022 08:47:39 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1656344865; x=1687880865; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p55ZwZ1mqA0kD6fdzYGXMJEn54U1NSdpfOpvP1qSRxE=; b=ITFw7guqYFMz4WHXwaELe9pMg86LhdHGEudY6ZeX8qHITMthxvEriMwY ODI1KZguxSXUwlRmySeb23l99ilDvzBSCnjKIRb1ziLCO1XChacAfUGYm 25Gzde5ifpooTTIemqgCQ4rSbe8Zp/PLMyjKZJiVMoGQ5JV79SD7NAfBm g=; X-QCInternal: smtphost From: Jae Hyun Yoo To: Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Titus Rwantare , Andrew Jeffery , Joel Stanley , Patrick Venture , Hao Wu CC: Graeme Gregory , Maheswara Kurapati , Jae Hyun Yoo , , Subject: [PATCH v2 6/7] hw/arm/aspeed: firework: Add Thermal Diodes Date: Mon, 27 Jun 2022 08:47:02 -0700 Message-ID: <20220627154703.148943-7-quic_jaehyoo@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220627154703.148943-1-quic_jaehyoo@quicinc.com> References: <20220627154703.148943-1-quic_jaehyoo@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.46.98.28; envelope-from=quic_jaehyoo@quicinc.com; helo=alexa-out.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1656345054910100001 Content-Type: text/plain; charset="utf-8" From: Maheswara Kurapati Add Thermal Diodes for Firework machine. Signed-off-by: Maheswara Kurapati Signed-off-by: Jae Hyun Yoo Reviewed-by: C=C3=A9dric Le Goater --- Changes in v2: * Refined code to avoid retouching by the next patch. (Joel) hw/arm/aspeed.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 9c07db70f2fc..cfc322ee30e9 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1002,12 +1002,22 @@ static void qcom_dc_scm_bmc_i2c_init(AspeedMachineS= tate *bmc) static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc =3D &bmc->soc; + I2CSlave *therm_mux; =20 /* Create the generic DC-SCM hardware */ qcom_dc_scm_bmc_i2c_init(bmc); =20 /* Now create the Firework specific hardware */ =20 + /* I2C8 Thermal Diodes*/ + therm_mux =3D i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), + "pca9548", 0x70); + i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, = 0x4C); + i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, = 0x4C); + i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, = 0x48); + i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, = 0x48); + i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, = 0x48); + /* I2C9 Fan Controller (MAX31785) */ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", = 0x52); i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", = 0x54); --=20 2.25.1 From nobody Sat May 18 06:04:07 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656345234788565.7781496974196; Mon, 27 Jun 2022 08:53:54 -0700 (PDT) Received: from localhost ([::1]:40360 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o5r3h-0003Vt-Ps for importer@patchew.org; Mon, 27 Jun 2022 11:53:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43220) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o5qxn-0001RP-Jy; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=quic_jaehyoo@quicinc.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1656345235284100001 Content-Type: text/plain; charset="utf-8" Add 2-level cascaded I2C MUXes for SOC VR channels into the Firework machine. Signed-off-by: Jae Hyun Yoo Reviewed-by: C=C3=A9dric Le Goater --- Changes in v2: * None hw/arm/aspeed.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index cfc322ee30e9..1708a8f3408d 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1002,13 +1002,21 @@ static void qcom_dc_scm_bmc_i2c_init(AspeedMachineS= tate *bmc) static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc =3D &bmc->soc; - I2CSlave *therm_mux; + I2CSlave *therm_mux, *cpuvr_mux; =20 /* Create the generic DC-SCM hardware */ qcom_dc_scm_bmc_i2c_init(bmc); =20 /* Now create the Firework specific hardware */ =20 + /* I2C7 CPUVR MUX */ + cpuvr_mux =3D i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), + "pca9546", 0x70); + i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", = 0x72); + i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", = 0x72); + i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", = 0x72); + i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", = 0x72); + /* I2C8 Thermal Diodes*/ therm_mux =3D i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9548", 0x70); --=20 2.25.1