From nobody Mon Feb 9 06:50:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1656335718210100.4296742594978; Mon, 27 Jun 2022 06:15:18 -0700 (PDT) Received: from localhost ([::1]:50922 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o5oaD-00030E-7e for importer@patchew.org; Mon, 27 Jun 2022 09:15:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56692) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o5oYh-0001MP-Bc; Mon, 27 Jun 2022 09:13:44 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:38309) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o5oYd-0004V1-Ir; Mon, 27 Jun 2022 09:13:42 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LWp7x1RPQz4xLX; Mon, 27 Jun 2022 23:13:33 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LWp7t6Bktz4xDH; Mon, 27 Jun 2022 23:13:30 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Andrew Jeffery , Joel Stanley , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH v4] aspeed: Set the dram container at the SoC level Date: Mon, 27 Jun 2022 15:13:27 +0200 Message-Id: <20220627131327.741192-1-clg@kaod.org> X-Mailer: git-send-email 2.35.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=MnSX=XC=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1656335720341100001 Currently, the Aspeed machines allocate a ram container region in which the machine ram region is mapped. See commit ad1a9782186d ("aspeed: add a RAM memory region container"). An extra region is mapped after ram in the ram container to catch invalid access done by FW. That's how FW determines the size of ram. See commit ebe31c0a8ef7 ("aspeed: add a max_ram_size property to the memory controller"). Let's move all the logic under the SoC where it should be. It will also ease the work on multi SoC support. Reviewed-by: Peter Delevoryas Message-Id: <20220623202123.3972977-1-clg@kaod.org> Signed-off-by: C=C3=A9dric Le Goater --- Changes in v4: - Fix the zero size case for unimp device (sigh):=20 Unexpected error in unimp_realize() at ../hw/misc/unimp.c:57: qemu-system-arm: property 'size' not specified or zero Changes in v3: - Create RAM after SDMC has been realized to get correct values of RAM size and max-size - Size the RAM container region to max-size. We don't need more. Changes in v2: - handle errors include/hw/arm/aspeed_soc.h | 2 ++ hw/arm/aspeed.c | 39 ++--------------------------- hw/arm/aspeed_ast2600.c | 7 ++++-- hw/arm/aspeed_soc.c | 49 +++++++++++++++++++++++++++++++++++-- 4 files changed, 56 insertions(+), 41 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 02a5a9ffcbd3..e8a104823d35 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -50,6 +50,7 @@ struct AspeedSoCState { A15MPPrivState a7mpcore; ARMv7MState armv7m; MemoryRegion *dram_mr; + MemoryRegion dram_container; MemoryRegion sram; AspeedVICState vic; AspeedRtcState rtc; @@ -165,5 +166,6 @@ enum { =20 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); void aspeed_soc_uart_init(AspeedSoCState *s); +bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); =20 #endif /* ASPEED_SOC_H */ diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index a06f7c1b62a9..dc09773b0ba5 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -174,27 +174,6 @@ struct AspeedMachineState { #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 =20 -/* - * The max ram region is for firmwares that scan the address space - * with load/store to guess how much RAM the SoC has. - */ -static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) -{ - return 0; -} - -static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, - unsigned size) -{ - /* Discard writes */ -} - -static const MemoryRegionOps max_ram_ops =3D { - .read =3D max_ram_read, - .write =3D max_ram_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; - #define AST_SMP_MAILBOX_BASE 0x1e6e2180 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) @@ -324,20 +303,16 @@ static void aspeed_machine_init(MachineState *machine) AspeedMachineClass *amc =3D ASPEED_MACHINE_GET_CLASS(machine); AspeedSoCClass *sc; DriveInfo *drive0 =3D drive_get(IF_MTD, 0, 0); - ram_addr_t max_ram_size; int i; NICInfo *nd =3D &nd_table[0]; =20 - memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", - 4 * GiB); - memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); - object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_na= me); =20 sc =3D ASPEED_SOC_GET_CLASS(&bmc->soc); =20 /* - * This will error out if isize is not supported by memory controller. + * This will error out if the RAM size is not supported by the + * memory controller of the SoC. */ object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_s= ize, &error_fatal); @@ -369,16 +344,6 @@ static void aspeed_machine_init(MachineState *machine) amc->uart_default); qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); =20 - memory_region_add_subregion(get_system_memory(), - sc->memmap[ASPEED_DEV_SDRAM], - &bmc->ram_container); - - max_ram_size =3D object_property_get_uint(OBJECT(&bmc->soc), "max-ram-= size", - &error_abort); - memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, - "max_ram", max_ram_size - machine->ram_size); - memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &b= mc->max_ram); - aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ? bmc->fmc_model : amc->fmc_m= odel, amc->num_cs, 0); diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index b0a4199b6960..bb5927c36bbf 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -197,8 +197,6 @@ static void aspeed_soc_ast2600_init(Object *obj) object_initialize_child(obj, "sdmc", &s->sdmc, typename); object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), "ram-size"); - object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), - "max-ram-size"); =20 for (i =3D 0; i < sc->wdts_num; i++) { snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); @@ -443,6 +441,11 @@ static void aspeed_soc_ast2600_realize(DeviceState *de= v, Error **errp) sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); } =20 + /* RAM */ + if (!aspeed_soc_dram_init(s, errp)) { + return; + } + /* Net */ for (i =3D 0; i < sc->macs_num; i++) { object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 30574d4276ab..3e6055ac9129 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -11,6 +11,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/units.h" #include "qapi/error.h" #include "hw/misc/unimp.h" #include "hw/arm/aspeed_soc.h" @@ -191,8 +192,6 @@ static void aspeed_soc_init(Object *obj) object_initialize_child(obj, "sdmc", &s->sdmc, typename); object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), "ram-size"); - object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), - "max-ram-size"); =20 for (i =3D 0; i < sc->wdts_num; i++) { snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); @@ -369,6 +368,11 @@ static void aspeed_soc_realize(DeviceState *dev, Error= **errp) sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); } =20 + /* RAM */ + if (!aspeed_soc_dram_init(s, errp)) { + return; + } + /* Net */ for (i =3D 0; i < sc->macs_num; i++) { object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, @@ -561,3 +565,44 @@ void aspeed_soc_uart_init(AspeedSoCState *s) serial_hd(i), DEVICE_LITTLE_ENDIAN); } } + +/* + * SDMC should be realized first to get correct RAM size and max size + * values + */ +bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp) +{ + AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + ram_addr_t ram_size, max_ram_size; + + ram_size =3D object_property_get_uint(OBJECT(&s->sdmc), "ram-size", + &error_abort); + max_ram_size =3D object_property_get_uint(OBJECT(&s->sdmc), "max-ram-s= ize", + &error_abort); + + memory_region_init(&s->dram_container, OBJECT(s), "ram-container", + max_ram_size); + memory_region_add_subregion(&s->dram_container, 0, s->dram_mr); + + /* + * Add a memory region beyond the RAM region to let firmwares scan + * the address space with load/store and guess how much RAM the + * SoC has. + */ + if (ram_size < max_ram_size) { + DeviceState *dev =3D qdev_new(TYPE_UNIMPLEMENTED_DEVICE); + + qdev_prop_set_string(dev, "name", "ram-empty"); + qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size); + if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { + return false; + } + + memory_region_add_subregion_overlap(&s->dram_container, ram_size, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -100= 0); + } + + memory_region_add_subregion(get_system_memory(), + sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); + return true; +} --=20 2.35.3