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bh=4TMmuSs0tpeZrpniB1q8VYEUn26OxnBpeVS/MTt5lOQ=; b=j/HBfyuYDejAjPqD2Iekq4Mdj4IaLiZ/r5G47DNlEgpTb5quHHQKjw6k b4y/0RnBuQSQFirgOBXZZsW+DjhN+Ly3wsFYyNAmTwQbW5DQNdIFRbNh+ xEF2pbrRh0qCSFJc2QjAFxMe9q8/YVi9su3YRR9wDbwaek7399vtrkxNS A=; X-QCInternal: smtphost From: Jae Hyun Yoo To: Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Titus Rwantare , Andrew Jeffery , Joel Stanley CC: Graeme Gregory , Maheswara Kurapati , , Subject: [PATCH 4/9] hw/arm/aspeed: add Qualcomm Firework machine and FRU device Date: Wed, 22 Jun 2022 10:28:25 -0700 Message-ID: <20220622172830.101210-5-quic_jaehyoo@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220622172830.101210-1-quic_jaehyoo@quicinc.com> References: <20220622172830.101210-1-quic_jaehyoo@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=quic_jaehyoo@quicinc.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1655919172865100001 Content-Type: text/plain; charset="utf-8" From: Graeme Gregory Add base for Qualcomm Firework machine and add its FRU device which is defined by DC-SCM to be fixed address 0x50. Signed-off-by: Graeme Gregory --- hw/arm/aspeed.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 36d6b2c33e48..0e6edd2be4fa 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1017,6 +1017,35 @@ static void qcom_dc_scm_bmc_i2c_init(AspeedMachineSt= ate *bmc) qcom_dc_scm_fru_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x53, 128 * 10= 24); } =20 +static void qcom_firework_fru_init(I2CBus *bus, uint8_t addr, uint32_t rsi= ze) +{ + I2CSlave *i2c_dev =3D i2c_slave_new("at24c-eeprom", addr); + DeviceState *dev =3D DEVICE(i2c_dev); + /* Use First Index for DC-SCM FRU */ + DriveInfo *dinfo =3D drive_get(IF_NONE, 0, 1); + + qdev_prop_set_uint32(dev, "rom-size", rsize); + + if (dinfo) { + qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); + } + + i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort); +} + +static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc =3D &bmc->soc; + + /* Create the generic DC-SCM hardware */ + qcom_dc_scm_bmc_i2c_init(bmc); + + /* Now create the Firework specific hardware */ + + /* I2C4 */ + qcom_firework_fru_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x50, 128 * 1= 024); +} + static bool aspeed_get_mmio_exec(Object *obj, Error **errp) { return ASPEED_MACHINE(obj)->mmio_exec; @@ -1489,6 +1518,26 @@ static void aspeed_machine_qcom_dc_scm_v1_class_init= (ObjectClass *oc, aspeed_soc_num_cpus(amc->soc_name); }; =20 +static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, + void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; + amc->soc_name =3D "ast2600-a3"; + amc->hw_strap1 =3D QCOM_DC_SCM_V1_BMC_HW_STRAP1; + amc->hw_strap2 =3D QCOM_DC_SCM_V1_BMC_HW_STRAP2; + amc->fmc_model =3D "n25q512a"; + amc->spi_model =3D "n25q512a"; + amc->num_cs =3D 2; + amc->macs_mask =3D ASPEED_MAC2_ON | ASPEED_MAC3_ON; + amc->i2c_init =3D qcom_dc_scm_firework_i2c_init; + mc->default_ram_size =3D 1 * GiB; + mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D + aspeed_soc_num_cpus(amc->soc_name); +}; + static const TypeInfo aspeed_machine_types[] =3D { { .name =3D MACHINE_TYPE_NAME("palmetto-bmc"), @@ -1534,6 +1583,10 @@ static const TypeInfo aspeed_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_qcom_dc_scm_v1_class_init, + }, { + .name =3D MACHINE_TYPE_NAME("qcom-firework"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_machine_qcom_firework_class_init, }, { .name =3D MACHINE_TYPE_NAME("fp5280g2-bmc"), .parent =3D TYPE_ASPEED_MACHINE, --=20 2.25.1