From nobody Tue May 21 14:31:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1655895731183385.5495652196963; Wed, 22 Jun 2022 04:02:11 -0700 (PDT) Received: from localhost ([::1]:59198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3y7e-0001HS-1N for importer@patchew.org; Wed, 22 Jun 2022 07:02:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49056) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o3xvu-00082u-JP for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:50:02 -0400 Received: from mail.loongson.cn ([114.242.206.163]:55334 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3xvr-0004kq-Fd for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:50:02 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxL0838rJi+BtUAA--.28846S3; Wed, 22 Jun 2022 18:43:03 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, maobibo@loongson.cn, mark.cave-ayland@ilande.co.uk, mst@redhat.com, imammedo@redhat.com, ani@anisinha.ca, f4bug@amsat.org, peter.maydell@linaro.org, chenhuacai@loongson.cn Subject: [PATCH 01/10] hw/loongarch: rename macro prefix LS_PCI to LS7A_PCI Date: Wed, 22 Jun 2022 18:42:52 +0800 Message-Id: <20220622104301.804447-2-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220622104301.804447-1-yangxiaojuan@loongson.cn> References: <20220622104301.804447-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf9DxL0838rJi+BtUAA--.28846S3 X-Coremail-Antispam: 1UD129KBjvJXoWxJr15JF4UXFy5Gr47Ww48JFb_yoW8Xw4kpr nxCF97KrW0kFs7JF1vyF12gr1DJayqk3W7ua1xZw4FkFZ7Zr1DZwnrJan8tFWUJF4kXr90 qa4vkw4Sg3WDJw7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1655895731845100001 Content-Type: text/plain; charset="utf-8" Rename macro LS_PCIECFG_xxx to LS7A_PCI_CFG_xxx to keep consistency with other macros. Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson --- hw/loongarch/loongson3.c | 4 ++-- include/hw/pci-host/ls7a.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c index bd20ebbb78..18cb2f61da 100644 --- a/hw/loongarch/loongson3.c +++ b/hw/loongarch/loongson3.c @@ -121,8 +121,8 @@ static void loongarch_devices_init(DeviceState *pch_pic) ecam_alias =3D g_new0(MemoryRegion, 1); ecam_reg =3D sysbus_mmio_get_region(d, 0); memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", - ecam_reg, 0, LS_PCIECFG_SIZE); - memory_region_add_subregion(get_system_memory(), LS_PCIECFG_BASE, + ecam_reg, 0, LS7A_PCI_CFG_SIZE); + memory_region_add_subregion(get_system_memory(), LS7A_PCI_CFG_BASE, ecam_alias); =20 /* Map PCI mem space */ diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h index 08c5f78be2..53e9b18f3a 100644 --- a/include/hw/pci-host/ls7a.h +++ b/include/hw/pci-host/ls7a.h @@ -18,8 +18,8 @@ #define LS7A_PCI_MEM_BASE 0x40000000UL #define LS7A_PCI_MEM_SIZE 0x40000000UL #define LS7A_PCI_IO_OFFSET 0x4000 -#define LS_PCIECFG_BASE 0x20000000 -#define LS_PCIECFG_SIZE 0x08000000 +#define LS7A_PCI_CFG_BASE 0x20000000 +#define LS7A_PCI_CFG_SIZE 0x08000000 #define LS7A_PCI_IO_BASE 0x18004000UL #define LS7A_PCI_IO_SIZE 0xC000 =20 --=20 2.31.1 From nobody Tue May 21 14:31:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1655894792951714.1712796353573; Wed, 22 Jun 2022 03:46:32 -0700 (PDT) Received: from localhost ([::1]:52892 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3xsV-00027I-DW for importer@patchew.org; Wed, 22 Jun 2022 06:46:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47858) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o3xpU-0007vd-TC for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:43:24 -0400 Received: from mail.loongson.cn ([114.242.206.163]:53548 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3xpR-0003xg-K7 for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:43:24 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxL0838rJi+BtUAA--.28846S4; Wed, 22 Jun 2022 18:43:04 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, maobibo@loongson.cn, mark.cave-ayland@ilande.co.uk, mst@redhat.com, imammedo@redhat.com, ani@anisinha.ca, f4bug@amsat.org, peter.maydell@linaro.org, chenhuacai@loongson.cn Subject: [PATCH 02/10] hw/loongarch: Add fw_cfg table support Date: Wed, 22 Jun 2022 18:42:53 +0800 Message-Id: <20220622104301.804447-3-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220622104301.804447-1-yangxiaojuan@loongson.cn> References: <20220622104301.804447-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf9DxL0838rJi+BtUAA--.28846S4 X-Coremail-Antispam: 1UD129KBjvJXoW3GF1rGrykXw48Cw4kJF4xWFg_yoW7KF47pF y3ZFWrGr4kJr17Jrs3J345Xr1fJws2kF17Way7ur4FkF17Gr1UZFnYk390vFyUJ3ykJa4Y qr9Yy3yFgFs5J3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1655894794808100002 Content-Type: text/plain; charset="utf-8" Add fw_cfg table for loongarch virt machine, including memmap table. Signed-off-by: Xiaojuan Yang --- hw/loongarch/fw_cfg.c | 33 ++++++++++++++++++++++++++ hw/loongarch/fw_cfg.h | 15 ++++++++++++ hw/loongarch/loongson3.c | 47 ++++++++++++++++++++++++++++++++++++- hw/loongarch/meson.build | 3 +++ include/hw/loongarch/virt.h | 3 +++ 5 files changed, 100 insertions(+), 1 deletion(-) create mode 100644 hw/loongarch/fw_cfg.c create mode 100644 hw/loongarch/fw_cfg.h diff --git a/hw/loongarch/fw_cfg.c b/hw/loongarch/fw_cfg.c new file mode 100644 index 0000000000..f6503d5607 --- /dev/null +++ b/hw/loongarch/fw_cfg.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU fw_cfg helpers (LoongArch specific) + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "hw/loongarch/fw_cfg.h" +#include "hw/loongarch/virt.h" +#include "hw/nvram/fw_cfg.h" +#include "sysemu/sysemu.h" + +static void fw_cfg_boot_set(void *opaque, const char *boot_device, + Error **errp) +{ + fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); +} + +FWCfgState *loongarch_fw_cfg_init(ram_addr_t ram_size, MachineState *ms) +{ + FWCfgState *fw_cfg; + int max_cpus =3D ms->smp.max_cpus; + int smp_cpus =3D ms->smp.cpus; + + fw_cfg =3D fw_cfg_init_mem_wide(VIRT_FWCFG_BASE + 8, VIRT_FWCFG_BASE, = 8, 0, NULL); + fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); + + qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); + return fw_cfg; +} diff --git a/hw/loongarch/fw_cfg.h b/hw/loongarch/fw_cfg.h new file mode 100644 index 0000000000..7c0de4db4a --- /dev/null +++ b/hw/loongarch/fw_cfg.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU fw_cfg helpers (LoongArch specific) + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#ifndef HW_LOONGARCH_FW_CFG_H +#define HW_LOONGARCH_FW_CFG_H + +#include "hw/boards.h" +#include "hw/nvram/fw_cfg.h" + +FWCfgState *loongarch_fw_cfg_init(ram_addr_t ram_size, MachineState *ms); +#endif diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c index 18cb2f61da..e570919f48 100644 --- a/hw/loongarch/loongson3.c +++ b/hw/loongarch/loongson3.c @@ -28,13 +28,46 @@ #include "hw/pci-host/ls7a.h" #include "hw/pci-host/gpex.h" #include "hw/misc/unimp.h" - +#include "hw/loongarch/fw_cfg.h" #include "target/loongarch/cpu.h" =20 #define PM_BASE 0x10080000 #define PM_SIZE 0x100 #define PM_CTRL 0x10 =20 +struct memmap_entry { + uint64_t address; + uint64_t length; + uint32_t type; + uint32_t reserved; +}; + +static struct memmap_entry *memmap_table; +static unsigned memmap_entries; + +static int memmap_add_entry(uint64_t address, uint64_t length, uint32_t ty= pe) +{ + int i; + + for (i =3D 0; i < memmap_entries; i++) { + if (memmap_table[i].address =3D=3D address) { + fprintf(stderr, "%s address:0x%lx length:0x%lx already exists\= n", + __func__, address, length); + return 0; + } + } + + memmap_table =3D g_renew(struct memmap_entry, memmap_table, + memmap_entries + 1); + memmap_table[memmap_entries].address =3D cpu_to_le64(address); + memmap_table[memmap_entries].length =3D cpu_to_le64(length); + memmap_table[memmap_entries].type =3D cpu_to_le32(type); + memmap_entries++; + + return memmap_entries; +} + + /* * This is a placeholder for missing ACPI, * and will eventually be replaced. @@ -327,15 +360,27 @@ static void loongarch_init(MachineState *machine) machine->ram, 0, 256 * MiB); memory_region_add_subregion(address_space_mem, offset, &lams->lowmem); offset +=3D 256 * MiB; + memmap_add_entry(0, 256 * MiB, 1); highram_size =3D ram_size - 256 * MiB; memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem", machine->ram, offset, highram_size); memory_region_add_subregion(address_space_mem, 0x90000000, &lams->high= mem); + memmap_add_entry(0x90000000, highram_size, 1); /* Add isa io region */ memory_region_init_alias(&lams->isa_io, NULL, "isa-io", get_system_io(), 0, LOONGARCH_ISA_IO_SIZE); memory_region_add_subregion(address_space_mem, LOONGARCH_ISA_IO_BASE, &lams->isa_io); + /* fw_cfg init */ + lams->fw_cfg =3D loongarch_fw_cfg_init(ram_size, machine); + rom_set_fw(lams->fw_cfg); + + if (lams->fw_cfg !=3D NULL) { + fw_cfg_add_file(lams->fw_cfg, "etc/memmap", + memmap_table, + sizeof(struct memmap_entry) * (memmap_entries)); + } + if (kernel_filename) { loaderparams.ram_size =3D ram_size; loaderparams.kernel_filename =3D kernel_filename; diff --git a/hw/loongarch/meson.build b/hw/loongarch/meson.build index cecb1a5d65..81131c9237 100644 --- a/hw/loongarch/meson.build +++ b/hw/loongarch/meson.build @@ -1,4 +1,7 @@ loongarch_ss =3D ss.source_set() +loongarch_ss.add(files( + 'fw_cfg.c', +)) loongarch_ss.add(when: 'CONFIG_LOONGARCH_VIRT', if_true: files('loongson3.= c')) =20 hw_arch +=3D {'loongarch': loongarch_ss} diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 09a816191c..9fec1f8a5c 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -17,6 +17,7 @@ =20 #define LOONGARCH_ISA_IO_BASE 0x18000000UL #define LOONGARCH_ISA_IO_SIZE 0x0004000 +#define VIRT_FWCFG_BASE 0x1e020000UL =20 struct LoongArchMachineState { /*< private >*/ @@ -26,6 +27,8 @@ struct LoongArchMachineState { MemoryRegion lowmem; MemoryRegion highmem; MemoryRegion isa_io; + /* State for other subsystems/APIs: */ + FWCfgState *fw_cfg; }; =20 #define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("virt") --=20 2.31.1 From nobody Tue May 21 14:31:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1655894998740231.64657709843118; Wed, 22 Jun 2022 03:49:58 -0700 (PDT) Received: from localhost ([::1]:60452 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3xvp-0007He-61 for importer@patchew.org; Wed, 22 Jun 2022 06:49:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47936) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o3xpb-000848-W6 for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:43:32 -0400 Received: from mail.loongson.cn ([114.242.206.163]:53544 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3xpZ-0003yG-TA for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:43:31 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxL0838rJi+BtUAA--.28846S5; Wed, 22 Jun 2022 18:43:04 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, maobibo@loongson.cn, mark.cave-ayland@ilande.co.uk, mst@redhat.com, imammedo@redhat.com, ani@anisinha.ca, f4bug@amsat.org, peter.maydell@linaro.org, chenhuacai@loongson.cn Subject: [PATCH 03/10] hw/loongarch: Add uefi bios loading support Date: Wed, 22 Jun 2022 18:42:54 +0800 Message-Id: <20220622104301.804447-4-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220622104301.804447-1-yangxiaojuan@loongson.cn> References: <20220622104301.804447-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf9DxL0838rJi+BtUAA--.28846S5 X-Coremail-Antispam: 1UD129KBjvJXoWxGryUKr47WF4xtFWkuw45ZFb_yoW5Xr4kpF y7CFn8Wrs5GrsxWrs3K345urn5Jrs7Ca47WF47Cr4FkF13ur1DZrW8J3s0yFyUAa95WFyj qF9Yqw4xW3WUJ3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1655894999433100001 Content-Type: text/plain; charset="utf-8" Add uefi bios loading support, now only uefi bios is porting to loongarch virt machine. Signed-off-by: Xiaojuan Yang --- hw/loongarch/loongson3.c | 34 ++++++++++++++++++++++++++++++++++ include/hw/loongarch/virt.h | 4 ++++ 2 files changed, 38 insertions(+) diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c index e570919f48..ac4a7e4143 100644 --- a/hw/loongarch/loongson3.c +++ b/hw/loongarch/loongson3.c @@ -312,6 +312,37 @@ static void loongarch_irq_init(LoongArchMachineState *= lams) loongarch_devices_init(pch_pic); } =20 +static void loongarch_firmware_init(LoongArchMachineState *lams) +{ + char *filename =3D MACHINE(lams)->firmware; + char *bios_name =3D NULL; + int bios_size; + + lams->bios_loaded =3D false; + if (filename) { + bios_name =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); + if (!bios_name) { + error_report("Could not find ROM image '%s'", filename); + exit(1); + } + + bios_size =3D load_image_targphys(bios_name, VIRT_BIOS_BASE, VIRT_= BIOS_SIZE); + if (bios_size < 0) { + error_report("Could not load ROM image '%s'", bios_name); + exit(1); + } + + g_free(bios_name); + + memory_region_init_ram(&lams->bios, NULL, "loongarch.bios", + VIRT_BIOS_SIZE, &error_fatal); + memory_region_set_readonly(&lams->bios, true); + memory_region_add_subregion(get_system_memory(), VIRT_BIOS_BASE, &= lams->bios); + lams->bios_loaded =3D true; + } + +} + static void reset_load_elf(void *opaque) { LoongArchCPU *cpu =3D opaque; @@ -371,6 +402,9 @@ static void loongarch_init(MachineState *machine) get_system_io(), 0, LOONGARCH_ISA_IO_SIZE); memory_region_add_subregion(address_space_mem, LOONGARCH_ISA_IO_BASE, &lams->isa_io); + /* load the BIOS image. */ + loongarch_firmware_init(lams); + /* fw_cfg init */ lams->fw_cfg =3D loongarch_fw_cfg_init(ram_size, machine); rom_set_fw(lams->fw_cfg); diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 9fec1f8a5c..ec37d86e44 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -18,6 +18,8 @@ #define LOONGARCH_ISA_IO_BASE 0x18000000UL #define LOONGARCH_ISA_IO_SIZE 0x0004000 #define VIRT_FWCFG_BASE 0x1e020000UL +#define VIRT_BIOS_BASE 0x1c000000UL +#define VIRT_BIOS_SIZE (4 * MiB) =20 struct LoongArchMachineState { /*< private >*/ @@ -27,6 +29,8 @@ struct LoongArchMachineState { MemoryRegion lowmem; MemoryRegion highmem; MemoryRegion isa_io; + MemoryRegion bios; + bool bios_loaded; /* State for other subsystems/APIs: */ FWCfgState *fw_cfg; }; --=20 2.31.1 From nobody Tue May 21 14:31:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1655894791891652.0412500610885; Wed, 22 Jun 2022 03:46:31 -0700 (PDT) Received: from localhost ([::1]:52936 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3xsU-000297-40 for importer@patchew.org; Wed, 22 Jun 2022 06:46:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47884) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o3xpW-0007vw-Cs for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:43:26 -0400 Received: from mail.loongson.cn ([114.242.206.163]:53552 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3xpU-0003xy-73 for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:43:26 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxL0838rJi+BtUAA--.28846S6; Wed, 22 Jun 2022 18:43:05 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, maobibo@loongson.cn, mark.cave-ayland@ilande.co.uk, mst@redhat.com, imammedo@redhat.com, ani@anisinha.ca, f4bug@amsat.org, peter.maydell@linaro.org, chenhuacai@loongson.cn Subject: [PATCH 04/10] hw/loongarch: Add linux kernel booting support Date: Wed, 22 Jun 2022 18:42:55 +0800 Message-Id: <20220622104301.804447-5-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220622104301.804447-1-yangxiaojuan@loongson.cn> References: <20220622104301.804447-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf9DxL0838rJi+BtUAA--.28846S6 X-Coremail-Antispam: 1UD129KBjvJXoWxGryUAF17Ar1ruF4rGryrtFb_yoWrtrWkpF ZxWF1Fqrs5AFn3Aw13tryUury5C34kCayag3W7Cr4SyFn8WryUuw15W34YvFyj9a95WF1Y qFZ0qrWag3WDJrJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1655894794804100001 Content-Type: text/plain; charset="utf-8" There are two situations to start system by kernel file. If exists bios option, system will boot from loaded bios file, else system will boot from hardcoded auxcode, and jump to kernel elf entry. Signed-off-by: Xiaojuan Yang --- hw/loongarch/loongson3.c | 109 +++++++++++++++++++++++++++++++++------ 1 file changed, 94 insertions(+), 15 deletions(-) diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c index ac4a7e4143..c381a9c016 100644 --- a/hw/loongarch/loongson3.c +++ b/hw/loongarch/loongson3.c @@ -109,6 +109,8 @@ static const MemoryRegionOps loongarch_virt_pm_ops =3D { static struct _loaderparams { uint64_t ram_size; const char *kernel_filename; + const char *kernel_cmdline; + const char *initrd_filename; } loaderparams; =20 static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr) @@ -354,18 +356,97 @@ static void reset_load_elf(void *opaque) } } =20 +/* Load an image file into an fw_cfg entry identified by key. */ +static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key, + uint16_t data_key, const char *image_name, + bool try_decompress) +{ + size_t size =3D -1; + uint8_t *data; + + if (image_name =3D=3D NULL) { + return; + } + + if (try_decompress) { + size =3D load_image_gzipped_buffer(image_name, + LOAD_IMAGE_MAX_GUNZIP_BYTES, &dat= a); + } + + if (size =3D=3D (size_t)-1) { + gchar *contents; + gsize length; + + if (!g_file_get_contents(image_name, &contents, &length, NULL)) { + error_report("failed to load \"%s\"", image_name); + exit(1); + } + size =3D length; + data =3D (uint8_t *)contents; + } + + fw_cfg_add_i32(fw_cfg, size_key, size); + fw_cfg_add_bytes(fw_cfg, data_key, data, size); +} + +static void fw_cfg_add_kernel_info(FWCfgState *fw_cfg) +{ + /* + * Expose the kernel, the command line, and the initrd in fw_cfg. + * We don't process them here at all, it's all left to the + * firmware. + */ + load_image_to_fw_cfg(fw_cfg, + FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, + loaderparams.kernel_filename, + false); + + if (loaderparams.initrd_filename) { + load_image_to_fw_cfg(fw_cfg, + FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, + loaderparams.initrd_filename, false); + } + + if (loaderparams.kernel_cmdline) { + fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, + strlen(loaderparams.kernel_cmdline) + 1); + fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, + loaderparams.kernel_cmdline); + } +} + +static void loongarch_firmware_boot(LoongArchMachineState *lams) +{ + fw_cfg_add_kernel_info(lams->fw_cfg); +} + +static void loongarch_direct_kernel_boot(LoongArchMachineState *lams) +{ + MachineState *machine =3D MACHINE(lams); + int64_t kernel_addr =3D 0; + LoongArchCPU *lacpu; + int i; + + kernel_addr =3D load_kernel_info(); + if (!machine->firmware) { + for (i =3D 0; i < machine->smp.cpus; i++) { + lacpu =3D LOONGARCH_CPU(qemu_get_cpu(i)); + lacpu->env.load_elf =3D true; + lacpu->env.elf_address =3D kernel_addr; + qemu_register_reset(reset_load_elf, lacpu); + } + } +} + static void loongarch_init(MachineState *machine) { const char *cpu_model =3D machine->cpu_type; - const char *kernel_filename =3D machine->kernel_filename; ram_addr_t offset =3D 0; ram_addr_t ram_size =3D machine->ram_size; uint64_t highram_size =3D 0; MemoryRegion *address_space_mem =3D get_system_memory(); LoongArchMachineState *lams =3D LOONGARCH_MACHINE(machine); - LoongArchCPU *lacpu; int i; - int64_t kernel_addr =3D 0; =20 if (!cpu_model) { cpu_model =3D LOONGARCH_CPU_TYPE_NAME("la464"); @@ -414,18 +495,16 @@ static void loongarch_init(MachineState *machine) memmap_table, sizeof(struct memmap_entry) * (memmap_entries)); } - - if (kernel_filename) { - loaderparams.ram_size =3D ram_size; - loaderparams.kernel_filename =3D kernel_filename; - kernel_addr =3D load_kernel_info(); - if (!machine->firmware) { - for (i =3D 0; i < machine->smp.cpus; i++) { - lacpu =3D LOONGARCH_CPU(qemu_get_cpu(i)); - lacpu->env.load_elf =3D true; - lacpu->env.elf_address =3D kernel_addr; - qemu_register_reset(reset_load_elf, lacpu); - } + loaderparams.ram_size =3D ram_size; + loaderparams.kernel_filename =3D machine->kernel_filename; + loaderparams.kernel_cmdline =3D machine->kernel_cmdline; + loaderparams.initrd_filename =3D machine->initrd_filename; + /* load the kernel. */ + if (loaderparams.kernel_filename) { + if (lams->bios_loaded) { + loongarch_firmware_boot(lams); + } else { + loongarch_direct_kernel_boot(lams); } } /* Initialize the IO interrupt subsystem */ --=20 2.31.1 From nobody Tue May 21 14:31:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165589499112561.638041621399225; Wed, 22 Jun 2022 03:49:51 -0700 (PDT) Received: from localhost ([::1]:60338 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3xvi-0007D0-4i for importer@patchew.org; Wed, 22 Jun 2022 06:49:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48038) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o3xph-0008Gq-TY for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:43:37 -0400 Received: from mail.loongson.cn ([114.242.206.163]:53550 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3xpR-0003xk-H7 for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:43:37 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxL0838rJi+BtUAA--.28846S7; Wed, 22 Jun 2022 18:43:05 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, maobibo@loongson.cn, mark.cave-ayland@ilande.co.uk, mst@redhat.com, imammedo@redhat.com, ani@anisinha.ca, f4bug@amsat.org, peter.maydell@linaro.org, chenhuacai@loongson.cn Subject: [PATCH 05/10] hw/loongarch: Add smbios support Date: Wed, 22 Jun 2022 18:42:56 +0800 Message-Id: <20220622104301.804447-6-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220622104301.804447-1-yangxiaojuan@loongson.cn> References: <20220622104301.804447-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf9DxL0838rJi+BtUAA--.28846S7 X-Coremail-Antispam: 1UD129KBjvJXoWxGry8GFy7ZF4kXr15Jw1rtFb_yoW5Cr47pF y3CFn5urs5Xr1fKrZxt343uF15Xrs3Kry2qF4avw40ka9Ikr1UuF48A3s0yFyUJ3ykG34j qFn5Kw13W3WUX3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1655894993208100001 Content-Type: text/plain; charset="utf-8" Add smbios support for loongarch virt machine, and put them into fw_cfg table so that bios can parse them quickly. The weblink of smbios spec: https://www.dmtf.org/dsp/DSP0134, the version is 3.6.0. Signed-off-by: Xiaojuan Yang --- hw/loongarch/Kconfig | 1 + hw/loongarch/loongson3.c | 36 ++++++++++++++++++++++++++++++++++++ include/hw/loongarch/virt.h | 1 + 3 files changed, 38 insertions(+) diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index 35b6680772..610552e522 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -14,3 +14,4 @@ config LOONGARCH_VIRT select LOONGARCH_PCH_MSI select LOONGARCH_EXTIOI select LS7A_RTC + select SMBIOS diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c index c381a9c016..04251aed0b 100644 --- a/hw/loongarch/loongson3.c +++ b/hw/loongarch/loongson3.c @@ -30,11 +30,45 @@ #include "hw/misc/unimp.h" #include "hw/loongarch/fw_cfg.h" #include "target/loongarch/cpu.h" +#include "hw/firmware/smbios.h" =20 #define PM_BASE 0x10080000 #define PM_SIZE 0x100 #define PM_CTRL 0x10 =20 +static void virt_build_smbios(LoongArchMachineState *lams) +{ + MachineState *ms =3D MACHINE(lams); + MachineClass *mc =3D MACHINE_GET_CLASS(lams); + uint8_t *smbios_tables, *smbios_anchor; + size_t smbios_tables_len, smbios_anchor_len; + const char *product =3D "QEMU Virtual Machine"; + + if (!lams->fw_cfg) { + return; + } + + smbios_set_defaults("QEMU", product, mc->name, false, + true, SMBIOS_ENTRY_POINT_TYPE_64); + + smbios_get_tables(ms, NULL, 0, &smbios_tables, &smbios_tables_len, + &smbios_anchor, &smbios_anchor_len, &error_fatal); + + if (smbios_anchor) { + fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables", + smbios_tables, smbios_tables_len); + fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor", + smbios_anchor, smbios_anchor_len); + } +} + +static void virt_machine_done(Notifier *notifier, void *data) +{ + LoongArchMachineState *lams =3D container_of(notifier, + LoongArchMachineState, machine_don= e); + virt_build_smbios(lams); +} + struct memmap_entry { uint64_t address; uint64_t length; @@ -509,6 +543,8 @@ static void loongarch_init(MachineState *machine) } /* Initialize the IO interrupt subsystem */ loongarch_irq_init(lams); + lams->machine_done.notify =3D virt_machine_done; + qemu_add_machine_init_done_notifier(&lams->machine_done); } =20 static void loongarch_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index ec37d86e44..9b7cdfae78 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -33,6 +33,7 @@ struct LoongArchMachineState { bool bios_loaded; /* State for other subsystems/APIs: */ FWCfgState *fw_cfg; + Notifier machine_done; }; =20 #define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("virt") --=20 2.31.1 From nobody Tue May 21 14:31:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1655895192322541.0607068523262; Wed, 22 Jun 2022 03:53:12 -0700 (PDT) Received: from localhost ([::1]:36478 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3xyw-0001yY-Jd for importer@patchew.org; Wed, 22 Jun 2022 06:53:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47986) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o3xpe-00089R-Hx for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:43:34 -0400 Received: from mail.loongson.cn ([114.242.206.163]:53554 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3xpa-0003xh-M4 for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:43:34 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxL0838rJi+BtUAA--.28846S8; Wed, 22 Jun 2022 18:43:05 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, maobibo@loongson.cn, mark.cave-ayland@ilande.co.uk, mst@redhat.com, imammedo@redhat.com, ani@anisinha.ca, f4bug@amsat.org, peter.maydell@linaro.org, chenhuacai@loongson.cn Subject: [PATCH 06/10] hw/loongarch: Add acpi ged support Date: Wed, 22 Jun 2022 18:42:57 +0800 Message-Id: <20220622104301.804447-7-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220622104301.804447-1-yangxiaojuan@loongson.cn> References: <20220622104301.804447-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf9DxL0838rJi+BtUAA--.28846S8 X-Coremail-Antispam: 1UD129KBjvAXoWfCw1xAw4UArW7Ww1DGFW5trb_yoW5WF4DXo Z3JFWrW3W8Xryj9rZYkrn8X3y2gr18KF4Dtr93CF4kGan3Aw4UGry3Gws5uw12y3Z0kry7 Xryrtwn3ArZ7CF1xn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjDUYxBIdaVFxhVjvjDU0xZFpf9x0zRUUUUUUUUU= X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1655895194791100001 Content-Type: text/plain; charset="utf-8" Loongarch virt machine uses general hardware reduces acpi method, rather than LS7A acpi device. Now only power management function is used in acpi ged device, memory hotplug will be added later. Also acpi tables such as RSDP/RSDT/FADT etc. The acpi table has submited to acpi spec, and will release soon. Signed-off-by: Xiaojuan Yang --- hw/loongarch/Kconfig | 2 + hw/loongarch/acpi-build.c | 609 ++++++++++++++++++++++++++++++++++++ hw/loongarch/loongson3.c | 78 ++++- hw/loongarch/meson.build | 1 + include/hw/loongarch/virt.h | 13 + include/hw/pci-host/ls7a.h | 4 + 6 files changed, 704 insertions(+), 3 deletions(-) create mode 100644 hw/loongarch/acpi-build.c diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index 610552e522..a99aa387c3 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -15,3 +15,5 @@ config LOONGARCH_VIRT select LOONGARCH_EXTIOI select LS7A_RTC select SMBIOS + select ACPI_PCI + select ACPI_HW_REDUCED diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c new file mode 100644 index 0000000000..6663823fd9 --- /dev/null +++ b/hw/loongarch/acpi-build.c @@ -0,0 +1,609 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Support for generating ACPI tables and passing them to Guests + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/bitmap.h" +#include "hw/pci/pci.h" +#include "hw/core/cpu.h" +#include "target/loongarch/cpu.h" +#include "hw/acpi/acpi-defs.h" +#include "hw/acpi/acpi.h" +#include "hw/nvram/fw_cfg.h" +#include "hw/acpi/bios-linker-loader.h" +#include "migration/vmstate.h" +#include "hw/mem/memory-device.h" +#include "sysemu/reset.h" + +/* Supported chipsets: */ +#include "hw/pci-host/ls7a.h" +#include "hw/loongarch/virt.h" +#include "hw/acpi/aml-build.h" + +#include "hw/acpi/utils.h" +#include "hw/acpi/pci.h" + +#include "qom/qom-qobject.h" + +#include "hw/acpi/generic_event_device.h" + +#define ACPI_BUILD_ALIGN_SIZE 0x1000 +#define ACPI_BUILD_TABLE_SIZE 0x20000 + +#ifdef DEBUG_ACPI_BUILD +#define ACPI_BUILD_DPRINTF(fmt, ...) \ + do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) +#else +#define ACPI_BUILD_DPRINTF(fmt, ...) +#endif + +/* build FADT */ +static void init_common_fadt_data(AcpiFadtData *data) +{ + AcpiFadtData fadt =3D { + /* ACPI 5.0: 4.1 Hardware-Reduced ACPI */ + .rev =3D 5, + .flags =3D ((1 << ACPI_FADT_F_HW_REDUCED_ACPI) | + (1 << ACPI_FADT_F_RESET_REG_SUP)), + + /* ACPI 5.0: 4.8.3.7 Sleep Control and Status Registers */ + .sleep_ctl =3D { + .space_id =3D AML_AS_SYSTEM_MEMORY, + .bit_width =3D 8, + .address =3D VIRT_GED_REG_ADDR + ACPI_GED_REG_SLEEP_CTL, + }, + .sleep_sts =3D { + .space_id =3D AML_AS_SYSTEM_MEMORY, + .bit_width =3D 8, + .address =3D VIRT_GED_REG_ADDR + ACPI_GED_REG_SLEEP_STS, + }, + + /* ACPI 5.0: 4.8.3.6 Reset Register */ + .reset_reg =3D { + .space_id =3D AML_AS_SYSTEM_MEMORY, + .bit_width =3D 8, + .address =3D VIRT_GED_REG_ADDR + ACPI_GED_REG_RESET, + }, + .reset_val =3D ACPI_GED_RESET_VALUE, + }; + *data =3D fadt; +} + +static void acpi_align_size(GArray *blob, unsigned align) +{ + /* + * Align size to multiple of given size. This reduces the chance + * we need to change size in the future (breaking cross version migrat= ion). + */ + g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); +} + +/* build FACS */ +static void +build_facs(GArray *table_data) +{ + const char *sig =3D "FACS"; + const uint8_t reserved[40] =3D {}; + + g_array_append_vals(table_data, sig, 4); /* Signature */ + build_append_int_noprefix(table_data, 64, 4); /* Length */ + build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ + build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector= */ + build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ + build_append_int_noprefix(table_data, 0, 4); /* Flags */ + g_array_append_vals(table_data, reserved, 40); /* Reserved */ +} + +/* build MADT */ +static void +build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *= lams) +{ + MachineState *ms =3D MACHINE(lams); + int i; + AcpiTable table =3D { .sig =3D "APIC", .rev =3D 1, .oem_id =3D lams->o= em_id, + .oem_table_id =3D lams->oem_table_id }; + + acpi_table_begin(&table, table_data); + + /* Local APIC Address */ + build_append_int_noprefix(table_data, 0, 4); + build_append_int_noprefix(table_data, 1 /* PCAT_COMPAT */, 4); /* Flag= s */ + + for (i =3D 0; i < ms->smp.cpus; i++) { + /* Processor Core Interrupt Controller Structure */ + build_append_int_noprefix(table_data, 17, 1); /* Type */ + build_append_int_noprefix(table_data, 15, 1); /* Length */ + build_append_int_noprefix(table_data, 1, 1); /* Version */ + build_append_int_noprefix(table_data, i + 1, 4); /* ACPI Processor= ID */ + build_append_int_noprefix(table_data, i, 4); /* Core ID */ + build_append_int_noprefix(table_data, 1, 4); /* Flags */ + } + + /* Extend I/O Interrupt Controller Structure */ + build_append_int_noprefix(table_data, 20, 1); /* Type */ + build_append_int_noprefix(table_data, 13, 1); /* Length */ + build_append_int_noprefix(table_data, 1, 1); /* Version */ + build_append_int_noprefix(table_data, 3, 1); /* Cascade */ + build_append_int_noprefix(table_data, 0, 1); /* Node */ + build_append_int_noprefix(table_data, 0xffff, 8); /* Node map */ + + /* MSI Interrupt Controller Structure */ + build_append_int_noprefix(table_data, 21, 1); /* Type */ + build_append_int_noprefix(table_data, 19, 1); /* Length */ + build_append_int_noprefix(table_data, 1, 1); /* Version */ + build_append_int_noprefix(table_data, LS7A_PCH_MSI_ADDR_LOW, 8);/* Add= ress */ + build_append_int_noprefix(table_data, 0x40, 4); /* Start */ + build_append_int_noprefix(table_data, 0xc0, 4); /* Count */ + + /* Bridge I/O Interrupt Controller Structure */ + build_append_int_noprefix(table_data, 22, 1); /* Type */ + build_append_int_noprefix(table_data, 17, 1); /* Length */ + build_append_int_noprefix(table_data, 1, 1); /* Version */ + build_append_int_noprefix(table_data, LS7A_PCH_REG_BASE, 8);/* Address= */ + build_append_int_noprefix(table_data, 0x1000, 2); /* Size */ + build_append_int_noprefix(table_data, 0, 2); /* Id */ + build_append_int_noprefix(table_data, 0x40, 2); /* Base */ + + acpi_table_end(linker, &table); +} + +/* build SRAT */ +static void +build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) +{ + uint64_t i; + LoongArchMachineState *lams =3D LOONGARCH_MACHINE(machine); + MachineState *ms =3D MACHINE(lams); + AcpiTable table =3D { .sig =3D "SRAT", .rev =3D 1, .oem_id =3D lams->o= em_id, + .oem_table_id =3D lams->oem_table_id }; + + acpi_table_begin(&table, table_data); + build_append_int_noprefix(table_data, 1, 4); /* Reserved */ + build_append_int_noprefix(table_data, 0, 8); /* Reserved */ + + for (i =3D 0; i < ms->smp.cpus; ++i) { + /* Processor Local APIC/SAPIC Affinity Structure */ + build_append_int_noprefix(table_data, 0, 1); /* Type */ + build_append_int_noprefix(table_data, 16, 1); /* Length */ + /* Proximity Domain [7:0] */ + build_append_int_noprefix(table_data, 0, 1); + build_append_int_noprefix(table_data, i, 1); /* APIC ID */ + /* Flags, Table 5-36 */ + build_append_int_noprefix(table_data, 1, 4); + build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ + /* Proximity Domain [31:8] */ + build_append_int_noprefix(table_data, 0, 3); + build_append_int_noprefix(table_data, 0, 4); /* Reserved */ + } + + build_srat_memory(table_data, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, + 0, MEM_AFFINITY_ENABLED); + + build_srat_memory(table_data, VIRT_HIGHMEM_BASE, machine->ram_size - V= IRT_LOWMEM_SIZE, + 0, MEM_AFFINITY_ENABLED); + + acpi_table_end(linker, &table); +} + +typedef +struct AcpiBuildState { + /* Copy of table in RAM (for patching). */ + MemoryRegion *table_mr; + /* Is table patched? */ + uint8_t patched; + void *rsdp; + MemoryRegion *rsdp_mr; + MemoryRegion *linker_mr; +} AcpiBuildState; + +static void build_gpex_pci0_int(Aml *table) +{ + Aml *sb_scope =3D aml_scope("_SB"); + Aml *pci0_scope =3D aml_scope("PCI0"); + Aml *prt_pkg =3D aml_varpackage(128); + int slot, pin; + + for (slot =3D 0; slot < PCI_SLOT_MAX; slot++) { + for (pin =3D 0; pin < PCI_NUM_PINS; pin++) { + Aml *pkg =3D aml_package(4); + aml_append(pkg, aml_int((slot << 16) | 0xFFFF)); + aml_append(pkg, aml_int(pin)); + aml_append(pkg, aml_int(0)); + aml_append(pkg, aml_int(80 + (slot + pin) % 4)); + aml_append(prt_pkg, pkg); + } + } + aml_append(pci0_scope, aml_name_decl("_PRT", prt_pkg)); + aml_append(sb_scope, pci0_scope); + aml_append(table, sb_scope); +} + +static void build_dbg_aml(Aml *table) +{ + Aml *field; + Aml *method; + Aml *while_ctx; + Aml *scope =3D aml_scope("\\"); + Aml *buf =3D aml_local(0); + Aml *len =3D aml_local(1); + Aml *idx =3D aml_local(2); + + aml_append(scope, + aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01)); + field =3D aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); + aml_append(field, aml_named_field("DBGB", 8)); + aml_append(scope, field); + + method =3D aml_method("DBUG", 1, AML_NOTSERIALIZED); + + aml_append(method, aml_to_hexstring(aml_arg(0), buf)); + aml_append(method, aml_to_buffer(buf, buf)); + aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len)); + aml_append(method, aml_store(aml_int(0), idx)); + + while_ctx =3D aml_while(aml_lless(idx, len)); + aml_append(while_ctx, + aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB"))); + aml_append(while_ctx, aml_increment(idx)); + aml_append(method, while_ctx); + aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB"))); + aml_append(scope, method); + aml_append(table, scope); +} + +static Aml *build_ls7a_osc_method(void) +{ + Aml *if_ctx; + Aml *if_ctx2; + Aml *else_ctx; + Aml *method; + Aml *a_cwd1 =3D aml_name("CDW1"); + Aml *a_ctrl =3D aml_local(0); + + method =3D aml_method("_OSC", 4, AML_NOTSERIALIZED); + aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW= 1")); + + if_ctx =3D aml_if(aml_equal( + aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); + aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW= 2")); + aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW= 3")); + aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); + + /* + * Always allow native PME, AER (no dependencies) + * Allow SHPC (PCI bridges can have SHPC controller) + */ + aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); + + if_ctx2 =3D aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); + /* Unknown revision */ + aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); + aml_append(if_ctx, if_ctx2); + + if_ctx2 =3D aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); + /* Capabilities bits were masked */ + aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); + aml_append(if_ctx, if_ctx2); + + /* Update DWORD3 in the buffer */ + aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); + aml_append(method, if_ctx); + + else_ctx =3D aml_else(); + /* Unrecognized UUID */ + aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); + aml_append(method, else_ctx); + + aml_append(method, aml_return(aml_arg(3))); + return method; +} + +static void build_ls7a_uart_device_aml(Aml *table) +{ + Aml *dev; + Aml *crs; + Aml *pkg0, *pkg1, *pkg2; + uint32_t uart_irq =3D LS7A_UART_IRQ; + + Aml *scope =3D aml_scope("_SB"); + dev =3D aml_device("COMA"); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501"))); + aml_append(dev, aml_name_decl("_UID", aml_int(0))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + crs =3D aml_resource_template(); + aml_append(crs, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, + 0, 0x1FE001E0, 0x1FE001E7, 0, 0x8)); + aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, + AML_SHARED, &uart_irq, 1)); + aml_append(dev, aml_name_decl("_CRS", crs)); + pkg0 =3D aml_package(0x2); + aml_append(pkg0, aml_int(0x05F5E100)); + aml_append(pkg0, aml_string("clock-frenquency")); + pkg1 =3D aml_package(0x1); + aml_append(pkg1, pkg0); + pkg2 =3D aml_package(0x2); + aml_append(pkg2, aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301")); + aml_append(pkg2, pkg1); + aml_append(dev, aml_name_decl("_DSD", pkg2)); + aml_append(scope, dev); + aml_append(table, scope); +} + +/* build DSDT */ +static void +build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine) +{ + Aml *dsdt, *sb_scope, *scope, *dev, *crs, *pkg; + int root_bus_limit =3D 0x7F; + LoongArchMachineState *lams =3D LOONGARCH_MACHINE(machine); + AcpiTable table =3D { .sig =3D "DSDT", .rev =3D 1, .oem_id =3D lams->o= em_id, + .oem_table_id =3D lams->oem_table_id }; + + acpi_table_begin(&table, table_data); + + dsdt =3D init_aml_allocator(); + + build_dbg_aml(dsdt); + + sb_scope =3D aml_scope("_SB"); + dev =3D aml_device("PCI0"); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); + aml_append(dev, aml_name_decl("_ADR", aml_int(0))); + aml_append(dev, aml_name_decl("_BBN", aml_int(0))); + aml_append(dev, aml_name_decl("_UID", aml_int(1))); + aml_append(dev, build_ls7a_osc_method()); + aml_append(sb_scope, dev); + aml_append(dsdt, sb_scope); + + build_gpex_pci0_int(dsdt); + build_ls7a_uart_device_aml(dsdt); + if (lams->acpi_ged) { + build_ged_aml(dsdt, "\\_SB."GED_DEVICE, + HOTPLUG_HANDLER(lams->acpi_ged), + LS7A_SCI_IRQ - PCH_PIC_IRQ_OFFSET, AML_SYSTEM_MEMORY, + VIRT_GED_EVT_ADDR); + } + + scope =3D aml_scope("\\_SB.PCI0"); + /* Build PCI0._CRS */ + crs =3D aml_resource_template(); + aml_append(crs, + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + 0x0000, 0x0, root_bus_limit, + 0x0000, root_bus_limit + 1)); + aml_append(crs, + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, AML_ENTIRE_RANGE, + 0x0000, 0x0000, 0xFFFF, 0x18000000, 0x10000)); + aml_append(crs, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_CACHEABLE, AML_READ_WRITE, + 0, LS7A_PCI_MEM_BASE, + LS7A_PCI_MEM_BASE + LS7A_PCI_MEM_SIZE - 1, + 0, LS7A_PCI_MEM_BASE)); + aml_append(scope, aml_name_decl("_CRS", crs)); + aml_append(dsdt, scope); + + /* System State Package */ + scope =3D aml_scope("\\"); + pkg =3D aml_package(4); + aml_append(pkg, aml_int(ACPI_GED_SLP_TYP_S5)); + aml_append(pkg, aml_int(0)); /* ignored */ + aml_append(pkg, aml_int(0)); /* reserved */ + aml_append(pkg, aml_int(0)); /* reserved */ + aml_append(scope, aml_name_decl("_S5", pkg)); + aml_append(dsdt, scope); + /* Copy AML table into ACPI tables blob and patch header there */ + g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); + acpi_table_end(linker, &table); + free_aml_allocator(); +} + +static void acpi_build(AcpiBuildTables *tables, MachineState *machine) +{ + LoongArchMachineState *lams =3D LOONGARCH_MACHINE(machine); + GArray *table_offsets; + AcpiFadtData fadt_data; + unsigned facs, rsdt, fadt, dsdt; + uint8_t *u; + size_t aml_len =3D 0; + GArray *tables_blob =3D tables->table_data; + + init_common_fadt_data(&fadt_data); + + table_offsets =3D g_array_new(false, true, sizeof(uint32_t)); + ACPI_BUILD_DPRINTF("init ACPI tables\n"); + + bios_linker_loader_alloc(tables->linker, + ACPI_BUILD_TABLE_FILE, tables_blob, + 64, false); + + /* + * FACS is pointed to by FADT. + * We place it first since it's the only table that has alignment + * requirements. + */ + facs =3D tables_blob->len; + build_facs(tables_blob); + + /* DSDT is pointed to by FADT */ + dsdt =3D tables_blob->len; + build_dsdt(tables_blob, tables->linker, machine); + + /* + * Count the size of the DSDT, we will need it for + * legacy sizing of ACPI tables. + */ + aml_len +=3D tables_blob->len - dsdt; + + /* ACPI tables pointed to by RSDT */ + fadt =3D tables_blob->len; + acpi_add_table(table_offsets, tables_blob); + fadt_data.facs_tbl_offset =3D &facs; + fadt_data.dsdt_tbl_offset =3D &dsdt; + fadt_data.xdsdt_tbl_offset =3D &dsdt; + build_fadt(tables_blob, tables->linker, &fadt_data, + lams->oem_id, lams->oem_table_id); + aml_len +=3D tables_blob->len - fadt; + + acpi_add_table(table_offsets, tables_blob); + build_madt(tables_blob, tables->linker, lams); + + acpi_add_table(table_offsets, tables_blob); + build_srat(tables_blob, tables->linker, machine); + + acpi_add_table(table_offsets, tables_blob); + { + AcpiMcfgInfo mcfg =3D { + .base =3D cpu_to_le64(LS7A_PCI_CFG_BASE), + .size =3D cpu_to_le64(LS7A_PCI_CFG_SIZE), + }; + build_mcfg(tables_blob, tables->linker, &mcfg, lams->oem_id, + lams->oem_table_id); + } + + /* Add tables supplied by user (if any) */ + for (u =3D acpi_table_first(); u; u =3D acpi_table_next(u)) { + unsigned len =3D acpi_table_len(u); + + acpi_add_table(table_offsets, tables_blob); + g_array_append_vals(tables_blob, u, len); + } + + /* RSDT is pointed to by RSDP */ + rsdt =3D tables_blob->len; + build_rsdt(tables_blob, tables->linker, table_offsets, + lams->oem_id, lams->oem_table_id); + + /* RSDP is in FSEG memory, so allocate it separately */ + { + AcpiRsdpData rsdp_data =3D { + .revision =3D 0, + .oem_id =3D lams->oem_id, + .xsdt_tbl_offset =3D NULL, + .rsdt_tbl_offset =3D &rsdt, + }; + build_rsdp(tables->rsdp, tables->linker, &rsdp_data); + } + + /* + * The align size is 128, warn if 64k is not enough therefore + * the align size could be resized. + */ + if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { + warn_report("ACPI table size %u exceeds %d bytes," + " migration may not work", + tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); + error_printf("Try removing CPUs, NUMA nodes, memory slots" + " or PCI bridges."); + } + + acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); + + /* Cleanup memory that's no longer used. */ + g_array_free(table_offsets, true); +} + +static void acpi_ram_update(MemoryRegion *mr, GArray *data) +{ + uint32_t size =3D acpi_data_len(data); + + /* + * Make sure RAM size is correct - in case it got changed + * e.g. by migration + */ + memory_region_ram_resize(mr, size, &error_abort); + + memcpy(memory_region_get_ram_ptr(mr), data->data, size); + memory_region_set_dirty(mr, 0, size); +} + +static void acpi_build_update(void *build_opaque) +{ + AcpiBuildState *build_state =3D build_opaque; + AcpiBuildTables tables; + + /* No state to update or already patched? Nothing to do. */ + if (!build_state || build_state->patched) { + return; + } + build_state->patched =3D 1; + + acpi_build_tables_init(&tables); + + acpi_build(&tables, MACHINE(qdev_get_machine())); + + acpi_ram_update(build_state->table_mr, tables.table_data); + acpi_ram_update(build_state->rsdp_mr, tables.rsdp); + acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); + + acpi_build_tables_cleanup(&tables, true); +} + +static void acpi_build_reset(void *build_opaque) +{ + AcpiBuildState *build_state =3D build_opaque; + build_state->patched =3D 0; +} + +static const VMStateDescription vmstate_acpi_build =3D { + .name =3D "acpi_build", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8(patched, AcpiBuildState), + VMSTATE_END_OF_LIST() + }, +}; + +void loongarch_acpi_setup(LoongArchMachineState *lams) +{ + AcpiBuildTables tables; + AcpiBuildState *build_state; + + if (!lams->fw_cfg) { + ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); + return; + } + + if (!loongarch_is_acpi_enabled(lams)) { + ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); + return; + } + + build_state =3D g_malloc0(sizeof *build_state); + + acpi_build_tables_init(&tables); + acpi_build(&tables, MACHINE(lams)); + + /* Now expose it all to Guest */ + build_state->table_mr =3D acpi_add_rom_blob(acpi_build_update, + build_state, tables.table_da= ta, + ACPI_BUILD_TABLE_FILE); + assert(build_state->table_mr !=3D NULL); + + build_state->linker_mr =3D + acpi_add_rom_blob(acpi_build_update, build_state, + tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); + + build_state->rsdp_mr =3D acpi_add_rom_blob(acpi_build_update, + build_state, tables.rsdp, + ACPI_BUILD_RSDP_FILE); + + qemu_register_reset(acpi_build_reset, build_state); + acpi_build_reset(build_state); + vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); + + /* + * Cleanup tables but don't free the memory: we track it + * in build_state. + */ + acpi_build_tables_cleanup(&tables, false); +} diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c index 04251aed0b..4465d87beb 100644 --- a/hw/loongarch/loongson3.c +++ b/hw/loongarch/loongson3.c @@ -31,6 +31,10 @@ #include "hw/loongarch/fw_cfg.h" #include "target/loongarch/cpu.h" #include "hw/firmware/smbios.h" +#include "hw/acpi/aml-build.h" +#include "qapi/qapi-visit-common.h" +#include "hw/acpi/generic_event_device.h" +#include "hw/mem/nvdimm.h" =20 #define PM_BASE 0x10080000 #define PM_SIZE 0x100 @@ -67,6 +71,7 @@ static void virt_machine_done(Notifier *notifier, void *d= ata) LoongArchMachineState *lams =3D container_of(notifier, LoongArchMachineState, machine_don= e); virt_build_smbios(lams); + loongarch_acpi_setup(lams); } =20 struct memmap_entry { @@ -101,7 +106,6 @@ static int memmap_add_entry(uint64_t address, uint64_t = length, uint32_t type) return memmap_entries; } =20 - /* * This is a placeholder for missing ACPI, * and will eventually be replaced. @@ -172,7 +176,32 @@ static int64_t load_kernel_info(void) return kernel_entry; } =20 -static void loongarch_devices_init(DeviceState *pch_pic) +static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachine= State *lams) +{ + DeviceState *dev; + MachineState *ms =3D MACHINE(lams); + uint32_t event =3D ACPI_GED_PWR_DOWN_EVT; + + if (ms->ram_slots) { + event |=3D ACPI_GED_MEM_HOTPLUG_EVT; + } + dev =3D qdev_new(TYPE_ACPI_GED); + qdev_prop_set_uint32(dev, "ged-event", event); + + /* ged event */ + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); + /* memory hotplug */ + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); + /* ged regs used for reset and power down */ + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); + + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, + qdev_get_gpio_in(pch_pic, LS7A_SCI_IRQ - PCH_PIC_IR= Q_OFFSET)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + return dev; +} + +static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineS= tate *lams) { DeviceState *gpex_dev; SysBusDevice *d; @@ -248,6 +277,8 @@ static void loongarch_devices_init(DeviceState *pch_pic) memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops, NULL, "loongarch_virt_pm", PM_SIZE); memory_region_add_subregion(get_system_memory(), PM_BASE, pm_mem); + /* acpi ged */ + lams->acpi_ged =3D create_acpi_ged(pch_pic, lams); } =20 static void loongarch_irq_init(LoongArchMachineState *lams) @@ -345,7 +376,7 @@ static void loongarch_irq_init(LoongArchMachineState *l= ams) qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_STA= RT)); } =20 - loongarch_devices_init(pch_pic); + loongarch_devices_init(pch_pic, lams); } =20 static void loongarch_firmware_init(LoongArchMachineState *lams) @@ -547,6 +578,40 @@ static void loongarch_init(MachineState *machine) qemu_add_machine_init_done_notifier(&lams->machine_done); } =20 +bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) +{ + if (lams->acpi =3D=3D ON_OFF_AUTO_OFF) { + return false; + } + return true; +} + +static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + LoongArchMachineState *lams =3D LOONGARCH_MACHINE(obj); + OnOffAuto acpi =3D lams->acpi; + + visit_type_OnOffAuto(v, name, &acpi, errp); +} + +static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + LoongArchMachineState *lams =3D LOONGARCH_MACHINE(obj); + + visit_type_OnOffAuto(v, name, &lams->acpi, errp); +} + +static void loongarch_machine_initfn(Object *obj) +{ + LoongArchMachineState *lams =3D LOONGARCH_MACHINE(obj); + + lams->acpi =3D ON_OFF_AUTO_AUTO; + lams->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); + lams->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); +} + static void loongarch_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -562,6 +627,12 @@ static void loongarch_class_init(ObjectClass *oc, void= *data) mc->block_default_type =3D IF_VIRTIO; mc->default_boot_order =3D "c"; mc->no_cdrom =3D 1; + + object_class_property_add(oc, "acpi", "OnOffAuto", + loongarch_get_acpi, loongarch_set_acpi, + NULL, NULL); + object_class_property_set_description(oc, "acpi", + "Enable ACPI"); } =20 static const TypeInfo loongarch_machine_types[] =3D { @@ -570,6 +641,7 @@ static const TypeInfo loongarch_machine_types[] =3D { .parent =3D TYPE_MACHINE, .instance_size =3D sizeof(LoongArchMachineState), .class_init =3D loongarch_class_init, + .instance_init =3D loongarch_machine_initfn, } }; =20 diff --git a/hw/loongarch/meson.build b/hw/loongarch/meson.build index 81131c9237..3e7cbcfc05 100644 --- a/hw/loongarch/meson.build +++ b/hw/loongarch/meson.build @@ -3,5 +3,6 @@ loongarch_ss.add(files( 'fw_cfg.c', )) loongarch_ss.add(when: 'CONFIG_LOONGARCH_VIRT', if_true: files('loongson3.= c')) +loongarch_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi-build.c')) =20 hw_arch +=3D {'loongarch': loongarch_ss} diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 9b7cdfae78..fb4a4f4e7b 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -21,6 +21,13 @@ #define VIRT_BIOS_BASE 0x1c000000UL #define VIRT_BIOS_SIZE (4 * MiB) =20 +#define VIRT_LOWMEM_BASE 0 +#define VIRT_LOWMEM_SIZE 0x10000000 +#define VIRT_HIGHMEM_BASE 0x90000000 +#define VIRT_GED_EVT_ADDR 0x100e0000 +#define VIRT_GED_MEM_ADDR (VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN) +#define VIRT_GED_REG_ADDR (VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN) + struct LoongArchMachineState { /*< private >*/ MachineState parent_obj; @@ -34,8 +41,14 @@ struct LoongArchMachineState { /* State for other subsystems/APIs: */ FWCfgState *fw_cfg; Notifier machine_done; + OnOffAuto acpi; + char *oem_id; + char *oem_table_id; + DeviceState *acpi_ged; }; =20 #define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("virt") OBJECT_DECLARE_SIMPLE_TYPE(LoongArchMachineState, LOONGARCH_MACHINE) +bool loongarch_is_acpi_enabled(LoongArchMachineState *lams); +void loongarch_acpi_setup(LoongArchMachineState *lams); #endif diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h index 53e9b18f3a..95ef775089 100644 --- a/include/hw/pci-host/ls7a.h +++ b/include/hw/pci-host/ls7a.h @@ -23,6 +23,9 @@ #define LS7A_PCI_IO_BASE 0x18004000UL #define LS7A_PCI_IO_SIZE 0xC000 =20 +#define LS7A_PCI_MEM_BASE 0x40000000UL +#define LS7A_PCI_MEM_SIZE 0x40000000UL + #define LS7A_PCH_REG_BASE 0x10000000UL #define LS7A_IOAPIC_REG_BASE (LS7A_PCH_REG_BASE) #define LS7A_PCH_MSI_ADDR_LOW 0x2FF00000UL @@ -41,4 +44,5 @@ #define LS7A_MISC_REG_BASE (LS7A_PCH_REG_BASE + 0x00080000) #define LS7A_RTC_REG_BASE (LS7A_MISC_REG_BASE + 0x00050100) #define LS7A_RTC_LEN 0x100 +#define LS7A_SCI_IRQ (PCH_PIC_IRQ_OFFSET + 4) #endif --=20 2.31.1 From nobody Tue May 21 14:31:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1655894836192156.96829890998447; Wed, 22 Jun 2022 03:47:16 -0700 (PDT) Received: from localhost ([::1]:53714 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3xtC-0002iW-FZ for importer@patchew.org; Wed, 22 Jun 2022 06:47:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47972) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o3xpd-00088Y-To for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:43:34 -0400 Received: from mail.loongson.cn ([114.242.206.163]:53538 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3xpY-0003xm-6L for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:43:33 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxL0838rJi+BtUAA--.28846S9; Wed, 22 Jun 2022 18:43:06 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, maobibo@loongson.cn, mark.cave-ayland@ilande.co.uk, mst@redhat.com, imammedo@redhat.com, ani@anisinha.ca, f4bug@amsat.org, peter.maydell@linaro.org, chenhuacai@loongson.cn Subject: [PATCH 07/10] hw/loongarch: Add fdt support Date: Wed, 22 Jun 2022 18:42:58 +0800 Message-Id: <20220622104301.804447-8-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220622104301.804447-1-yangxiaojuan@loongson.cn> References: <20220622104301.804447-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf9DxL0838rJi+BtUAA--.28846S9 X-Coremail-Antispam: 1UD129KBjvJXoWxtw1rtry5ArW8Jr13GFWktFb_yoW3Kr1xpF W7AFW7WrW8Xrsrurs7W345uwn3Jr18GFW7Wa17WrWFk34DWw18Zay8Aa9IyF1UJ34jqFyY vFZ0qrySg3WxKFJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1655894838374100001 Content-Type: text/plain; charset="utf-8" Add LoongArch flatted device tree, adding cpu device node, firmware cfg nod= e, pcie node into it, and create fdt rom memory region. Now fdt info is not full since only uefi bios uses fdt, linux kernel does not use fdt. Loongarch Linux kernel uses acpi table which is full in qemu virt machine. Signed-off-by: Xiaojuan Yang --- hw/loongarch/loongson3.c | 136 +++++++++++++++++++++++++++++++++++- include/hw/loongarch/virt.h | 4 ++ target/loongarch/cpu.c | 1 + target/loongarch/cpu.h | 3 + 4 files changed, 141 insertions(+), 3 deletions(-) diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c index 4465d87beb..4b58a76025 100644 --- a/hw/loongarch/loongson3.c +++ b/hw/loongarch/loongson3.c @@ -35,6 +35,129 @@ #include "qapi/qapi-visit-common.h" #include "hw/acpi/generic_event_device.h" #include "hw/mem/nvdimm.h" +#include "sysemu/device_tree.h" +#include + +static void create_fdt(LoongArchMachineState *lams) +{ + MachineState *ms =3D MACHINE(lams); + + ms->fdt =3D create_device_tree(&lams->fdt_size); + if (!ms->fdt) { + error_report("create_device_tree() failed"); + exit(1); + } + + /* Header */ + qemu_fdt_setprop_string(ms->fdt, "/", "compatible", + "linux,dummy-loongson3"); + qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); + qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); +} + +static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) +{ + int num; + const MachineState *ms =3D MACHINE(lams); + int smp_cpus =3D ms->smp.cpus; + + qemu_fdt_add_subnode(ms->fdt, "/cpus"); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); + + /* cpu nodes */ + for (num =3D smp_cpus - 1; num >=3D 0; num--) { + char *nodename =3D g_strdup_printf("/cpus/cpu@%d", num); + LoongArchCPU *cpu =3D LOONGARCH_CPU(qemu_get_cpu(num)); + + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); + qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", + cpu->dtb_compatible); + qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); + qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", + qemu_fdt_alloc_phandle(ms->fdt)); + g_free(nodename); + } + + /*cpu map */ + qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); + + for (num =3D smp_cpus - 1; num >=3D 0; num--) { + char *cpu_path =3D g_strdup_printf("/cpus/cpu@%d", num); + char *map_path; + + if (ms->smp.threads > 1) { + map_path =3D g_strdup_printf( + "/cpus/cpu-map/socket%d/core%d/thread%d", + num / (ms->smp.cores * ms->smp.threads), + (num / ms->smp.threads) % ms->smp.cores, + num % ms->smp.threads); + } else { + map_path =3D g_strdup_printf( + "/cpus/cpu-map/socket%d/core%d", + num / ms->smp.cores, + num % ms->smp.cores); + } + qemu_fdt_add_path(ms->fdt, map_path); + qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); + + g_free(map_path); + g_free(cpu_path); + } +} + +static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams) +{ + char *nodename; + hwaddr base =3D VIRT_FWCFG_BASE; + const MachineState *ms =3D MACHINE(lams); + + nodename =3D g_strdup_printf("/fw_cfg@%" PRIx64, base); + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_string(ms->fdt, nodename, + "compatible", "qemu,fw-cfg-mmio"); + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", + 2, base, 2, 0x8); + qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); + g_free(nodename); +} + +static void fdt_add_pcie_node(const LoongArchMachineState *lams) +{ + char *nodename; + hwaddr base_mmio =3D LS7A_PCI_MEM_BASE; + hwaddr size_mmio =3D LS7A_PCI_MEM_SIZE; + hwaddr base_pio =3D LS7A_PCI_IO_BASE; + hwaddr size_pio =3D LS7A_PCI_IO_SIZE; + hwaddr base_pcie =3D LS7A_PCI_CFG_BASE; + hwaddr size_pcie =3D LS7A_PCI_CFG_SIZE; + hwaddr base =3D base_pcie; + + const MachineState *ms =3D MACHINE(lams); + + nodename =3D g_strdup_printf("/pcie@%" PRIx64, base); + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_string(ms->fdt, nodename, + "compatible", "pci-host-ecam-generic"); + qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); + qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); + qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); + qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); + qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, + PCIE_MMCFG_BUS(LS7A_PCI_CFG_SIZE - 1)); + qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", + 2, base_pcie, 2, size_pcie); + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", + 1, FDT_PCI_RANGE_IOPORT, 2, LS7A_PCI_IO_O= FFSET, + 2, base_pio, 2, size_pio, + 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, + 2, base_mmio, 2, size_mmio); + g_free(nodename); + qemu_fdt_dumpdtb(ms->fdt, lams->fdt_size); +} + =20 #define PM_BASE 0x10080000 #define PM_SIZE 0x100 @@ -526,12 +649,12 @@ static void loongarch_init(MachineState *machine) error_report("ram_size must be greater than 1G."); exit(1); } - + create_fdt(lams); /* Init CPUs */ for (i =3D 0; i < machine->smp.cpus; i++) { cpu_create(machine->cpu_type); } - + fdt_add_cpu_nodes(lams); /* Add memory region */ memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram", machine->ram, 0, 256 * MiB); @@ -554,12 +677,12 @@ static void loongarch_init(MachineState *machine) /* fw_cfg init */ lams->fw_cfg =3D loongarch_fw_cfg_init(ram_size, machine); rom_set_fw(lams->fw_cfg); - if (lams->fw_cfg !=3D NULL) { fw_cfg_add_file(lams->fw_cfg, "etc/memmap", memmap_table, sizeof(struct memmap_entry) * (memmap_entries)); } + fdt_add_fw_cfg_node(lams); loaderparams.ram_size =3D ram_size; loaderparams.kernel_filename =3D machine->kernel_filename; loaderparams.kernel_cmdline =3D machine->kernel_cmdline; @@ -576,6 +699,13 @@ static void loongarch_init(MachineState *machine) loongarch_irq_init(lams); lams->machine_done.notify =3D virt_machine_done; qemu_add_machine_init_done_notifier(&lams->machine_done); + fdt_add_pcie_node(lams); + + /* load fdt */ + MemoryRegion *fdt_rom =3D g_new(MemoryRegion, 1); + memory_region_init_rom(fdt_rom, NULL, "fdt", LA_FDT_SIZE, &error_fatal= ); + memory_region_add_subregion(get_system_memory(), LA_FDT_BASE, fdt_rom); + rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, LA_FDT_BASE); } =20 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index fb4a4f4e7b..f4f24df428 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -28,6 +28,9 @@ #define VIRT_GED_MEM_ADDR (VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN) #define VIRT_GED_REG_ADDR (VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN) =20 +#define LA_FDT_BASE 0x1c400000 +#define LA_FDT_SIZE 0x100000 + struct LoongArchMachineState { /*< private >*/ MachineState parent_obj; @@ -45,6 +48,7 @@ struct LoongArchMachineState { char *oem_id; char *oem_table_id; DeviceState *acpi_ged; + int fdt_size; }; =20 #define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("virt") diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 4c8f96bc3a..401d3fd30a 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -328,6 +328,7 @@ static void loongarch_la464_initfn(Object *obj) env->cpucfg[i] =3D 0x0; } =20 + cpu->dtb_compatible =3D "loongarch,Loongson-3A5000"; env->cpucfg[0] =3D 0x14c010; /* PRID */ =20 uint32_t data =3D 0; diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 71a5036c3c..ce394c3287 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -326,6 +326,9 @@ struct ArchCPU { CPUNegativeOffsetState neg; CPULoongArchState env; QEMUTimer timer; + + /* 'compatible' string for this CPU for Linux device trees */ + const char *dtb_compatible; }; =20 #define TYPE_LOONGARCH_CPU "loongarch-cpu" --=20 2.31.1 From nobody Tue May 21 14:31:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1655894792626139.9129312084291; Wed, 22 Jun 2022 03:46:32 -0700 (PDT) Received: from localhost ([::1]:52970 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3xsV-0002AM-EB for importer@patchew.org; Wed, 22 Jun 2022 06:46:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47866) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o3xpV-0007vk-4n for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:43:25 -0400 Received: from mail.loongson.cn ([114.242.206.163]:53556 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3xpS-0003xi-2D for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:43:24 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxL0838rJi+BtUAA--.28846S10; Wed, 22 Jun 2022 18:43:06 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, maobibo@loongson.cn, mark.cave-ayland@ilande.co.uk, mst@redhat.com, imammedo@redhat.com, ani@anisinha.ca, f4bug@amsat.org, peter.maydell@linaro.org, chenhuacai@loongson.cn Subject: [PATCH 08/10] hw/loongarch: Fix ipi device access of 64bits Date: Wed, 22 Jun 2022 18:42:59 +0800 Message-Id: <20220622104301.804447-9-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220622104301.804447-1-yangxiaojuan@loongson.cn> References: <20220622104301.804447-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf9DxL0838rJi+BtUAA--.28846S10 X-Coremail-Antispam: 1UD129KBjvJXoW3Xr1DWFyfZF1DXr4xKryrXrb_yoWxCFyrpr y7urWa9r48JFZrXa4ktasrXF1DAwn7Wa429a9Ikay09r48Xry29a4vk34qqFyDA3s5GF1Y vr4kC3yaqa1UXaUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1655894794812100003 Content-Type: text/plain; charset="utf-8" 1.In general loongarch ipi device, 32bit registers is emulated, however for anysend/mailsend device only 64bit register access is supported. So separate the ipi memory region into two regions, including 32 bits and 64 bits. 2.By the document of ipi mailsend device, byte is written only when the mas= k bit is 0. The original code discards mask bit and overwrite the data always, th= is patch fixes the issue. Signed-off-by: Xiaojuan Yang --- hw/intc/loongarch_ipi.c | 85 ++++++++++++++++++++++----------- hw/loongarch/loongson3.c | 5 +- include/hw/intc/loongarch_ipi.h | 8 ++-- 3 files changed, 65 insertions(+), 33 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 66bee93675..57d7965289 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -50,35 +50,40 @@ static uint64_t loongarch_ipi_readl(void *opaque, hwadd= r addr, unsigned size) return ret; } =20 -static int get_ipi_data(target_ulong val) +static void send_ipi_data(CPULoongArchState *env, target_ulong val, target= _ulong addr) { int i, mask, data; =20 - data =3D val >> 32; - mask =3D (val >> 27) & 0xf; - + data =3D address_space_ldl(&env->address_space_iocsr, addr, + MEMTXATTRS_UNSPECIFIED, NULL); + mask =3D 0; for (i =3D 0; i < 4; i++) { - if ((mask >> i) & 1) { - data &=3D ~(0xff << (i * 8)); + /* bit 27 - 30 is mask for byte write */ + if (val & (0x1UL << (27 + i))) { + mask |=3D 0xff << (i * 8); } } - return data; + + data &=3D mask; + data |=3D (val >> 32) & ~mask; + address_space_stl(&env->address_space_iocsr, addr, + data, MEMTXATTRS_UNSPECIFIED, NULL); } =20 static void ipi_send(uint64_t val) { int cpuid, data; CPULoongArchState *env; + CPUState *cs; + LoongArchCPU *cpu; =20 cpuid =3D (val >> 16) & 0x3ff; /* IPI status vector */ data =3D 1 << (val & 0x1f); - qemu_mutex_lock_iothread(); - CPUState *cs =3D qemu_get_cpu(cpuid); - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + cs =3D qemu_get_cpu(cpuid); + cpu =3D LOONGARCH_CPU(cs); env =3D &cpu->env; loongarch_cpu_set_irq(cpu, IRQ_IPI, 1); - qemu_mutex_unlock_iothread(); address_space_stl(&env->address_space_iocsr, 0x1008, data, MEMTXATTRS_UNSPECIFIED, NULL); =20 @@ -86,23 +91,23 @@ static void ipi_send(uint64_t val) =20 static void mail_send(uint64_t val) { - int cpuid, data; + int cpuid; hwaddr addr; CPULoongArchState *env; + CPUState *cs; + LoongArchCPU *cpu; =20 cpuid =3D (val >> 16) & 0x3ff; addr =3D 0x1020 + (val & 0x1c); - CPUState *cs =3D qemu_get_cpu(cpuid); - LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + cs =3D qemu_get_cpu(cpuid); + cpu =3D LOONGARCH_CPU(cs); env =3D &cpu->env; - data =3D get_ipi_data(val); - address_space_stl(&env->address_space_iocsr, addr, - data, MEMTXATTRS_UNSPECIFIED, NULL); + send_ipi_data(env, val, addr); } =20 static void any_send(uint64_t val) { - int cpuid, data; + int cpuid; hwaddr addr; CPULoongArchState *env; =20 @@ -111,9 +116,7 @@ static void any_send(uint64_t val) CPUState *cs =3D qemu_get_cpu(cpuid); LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); env =3D &cpu->env; - data =3D get_ipi_data(val); - address_space_stl(&env->address_space_iocsr, addr, - data, MEMTXATTRS_UNSPECIFIED, NULL); + send_ipi_data(env, val, addr); } =20 static void loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_t val, @@ -150,12 +153,6 @@ static void loongarch_ipi_writel(void *opaque, hwaddr = addr, uint64_t val, case IOCSR_IPI_SEND: ipi_send(val); break; - case IOCSR_MAIL_SEND: - mail_send(val); - break; - case IOCSR_ANY_SEND: - any_send(val); - break; default: qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr); break; @@ -172,6 +169,32 @@ static const MemoryRegionOps loongarch_ipi_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 +/* mail send and any send only support writeq */ +static void loongarch_ipi_writeq(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + addr &=3D 0xfff; + switch (addr) { + case MAIL_SEND_OFFSET: + mail_send(val); + break; + case ANY_SEND_OFFSET: + any_send(val); + break; + default: + break; + } +} + +static const MemoryRegionOps loongarch_ipi64_ops =3D { + .write =3D loongarch_ipi_writeq, + .impl.min_access_size =3D 8, + .impl.max_access_size =3D 8, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 8, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + static void loongarch_ipi_init(Object *obj) { int cpu; @@ -185,10 +208,16 @@ static void loongarch_ipi_init(Object *obj) return; } lams =3D LOONGARCH_MACHINE(machine); + for (cpu =3D 0; cpu < MAX_IPI_CORE_NUM; cpu++) { memory_region_init_io(&s->ipi_iocsr_mem[cpu], obj, &loongarch_ipi_= ops, - &lams->ipi_core[cpu], "loongarch_ipi_iocsr", 0= x100); + &lams->ipi_core[cpu], "loongarch_ipi_iocsr",= 0x48); sysbus_init_mmio(sbd, &s->ipi_iocsr_mem[cpu]); + + memory_region_init_io(&s->ipi64_iocsr_mem[cpu], obj, &loongarch_ip= i64_ops, + &lams->ipi_core[cpu], "loongarch_ipi64_iocsr= ", 0x118); + sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem[cpu]); + qdev_init_gpio_out(DEVICE(obj), &lams->ipi_core[cpu].irq, 1); } } diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c index 4b58a76025..a06fed7797 100644 --- a/hw/loongarch/loongson3.c +++ b/hw/loongarch/loongson3.c @@ -453,7 +453,10 @@ static void loongarch_irq_init(LoongArchMachineState *= lams) /* IPI iocsr memory region */ memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX, sysbus_mmio_get_region(SYS_BUS_DEVICE(= ipi), - cpu)); + cpu * 2)); + memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR, + sysbus_mmio_get_region(SYS_BUS_DEVICE(= ipi), + cpu * 2 + 1)); /* extioi iocsr memory region */ memory_region_add_subregion(&env->system_iocsr, APIC_BASE, sysbus_mmio_get_region(SYS_BUS_DEVICE(exti= oi), diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ip= i.h index 996ed7ea93..a98c3dd4a3 100644 --- a/include/hw/intc/loongarch_ipi.h +++ b/include/hw/intc/loongarch_ipi.h @@ -23,9 +23,9 @@ #define IOCSR_IPI_SEND 0x40 #define IOCSR_MAIL_SEND 0x48 #define IOCSR_ANY_SEND 0x158 - -/* IPI system memory address */ -#define IPI_SYSTEM_MEM 0x1fe01000 +#define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND) +#define MAIL_SEND_OFFSET 0 +#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND) =20 #define MAX_IPI_CORE_NUM 4 #define MAX_IPI_MBX_NUM 4 @@ -46,7 +46,7 @@ typedef struct IPICore { struct LoongArchIPI { SysBusDevice parent_obj; MemoryRegion ipi_iocsr_mem[MAX_IPI_CORE_NUM]; - MemoryRegion ipi_system_mem[MAX_IPI_CORE_NUM]; + MemoryRegion ipi64_iocsr_mem[MAX_IPI_CORE_NUM]; }; =20 #endif --=20 2.31.1 From nobody Tue May 21 14:31:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1655895467828738.3587886352402; Wed, 22 Jun 2022 03:57:47 -0700 (PDT) Received: from localhost ([::1]:51114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3y3O-0003vH-QN for importer@patchew.org; Wed, 22 Jun 2022 06:57:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49042) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o3xvt-000805-Bl for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:50:01 -0400 Received: from mail.loongson.cn ([114.242.206.163]:55338 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3xvr-0004ks-Aw for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:50:01 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxL0838rJi+BtUAA--.28846S11; Wed, 22 Jun 2022 18:43:07 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, maobibo@loongson.cn, mark.cave-ayland@ilande.co.uk, mst@redhat.com, imammedo@redhat.com, ani@anisinha.ca, f4bug@amsat.org, peter.maydell@linaro.org, chenhuacai@loongson.cn Subject: [PATCH 09/10] target/loongarch: Fix the meaning of ECFG reg's VS field Date: Wed, 22 Jun 2022 18:43:00 +0800 Message-Id: <20220622104301.804447-10-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220622104301.804447-1-yangxiaojuan@loongson.cn> References: <20220622104301.804447-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf9DxL0838rJi+BtUAA--.28846S11 X-Coremail-Antispam: 1UD129KBjvdXoW7Wry5uw1rCw1rKFW5uw4fAFb_yoW3ZFX_W3 WfuF4kuFyjg3ZFqr4Fk345t345Xr18Ka1q9F92qrZ7Ga45XrsxZw4vgwn7ur12grW7GFnx A347GryYyr4akjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUUUUUUU X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1655895468472100001 Content-Type: text/plain; charset="utf-8" By the manual of LoongArch CSR, the VS field(18:16 bits) of ECFG reg means that the number of instructions between each exception entry is 2^VS. Signed-off-by: Xiaojuan Yang --- target/loongarch/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 401d3fd30a..d1a87e8e1c 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -219,6 +219,10 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); =20 + if (vec_size) { + vec_size =3D (1 << vec_size) * 4; + } + if (cs->exception_index =3D=3D EXCCODE_INT) { /* Interrupt */ uint32_t vector =3D 0; --=20 2.31.1 From nobody Tue May 21 14:31:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1655895309351365.6740935990357; Wed, 22 Jun 2022 03:55:09 -0700 (PDT) Received: from localhost ([::1]:42952 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3y0p-0006eq-ON for importer@patchew.org; Wed, 22 Jun 2022 06:55:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48000) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o3xpf-0008Ag-7x for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:43:35 -0400 Received: from mail.loongson.cn ([114.242.206.163]:53558 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3xpc-0003xj-8K for qemu-devel@nongnu.org; Wed, 22 Jun 2022 06:43:34 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxL0838rJi+BtUAA--.28846S12; Wed, 22 Jun 2022 18:43:07 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, maobibo@loongson.cn, mark.cave-ayland@ilande.co.uk, mst@redhat.com, imammedo@redhat.com, ani@anisinha.ca, f4bug@amsat.org, peter.maydell@linaro.org, chenhuacai@loongson.cn Subject: [PATCH 10/10] target/loongarch: Add lock when writing timer clear reg Date: Wed, 22 Jun 2022 18:43:01 +0800 Message-Id: <20220622104301.804447-11-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220622104301.804447-1-yangxiaojuan@loongson.cn> References: <20220622104301.804447-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf9DxL0838rJi+BtUAA--.28846S12 X-Coremail-Antispam: 1UD129KBjvJXoW7Aw18Zr1kWw4rGr4xZFyDAwb_yoW8WF17pr 9rCrsFgrWkJrZF9a1kZa4Yq3s8Xr45Wr47uan2kryxCw43X3s2qry8J3ZI9F4DGayrXr1F qrnY9a4jvay8XaUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1655895311207100003 Content-Type: text/plain; charset="utf-8" There is such error info when running linux kernel: tcg_handle_interrupt: assertion failed: (qemu_mutex_iothread_locked()). calling stack: #0 in raise () at /lib64/libc.so.6 #1 in abort () at /lib64/libc.so.6 #2 in g_assertion_message_expr.cold () at /lib64/libglib-2.0.so.0 #3 in g_assertion_message_expr () at /lib64/libglib-2.0.so.0 #4 in tcg_handle_interrupt (cpu=3D0x632000030800, mask=3D2) at ../accel= /tcg/tcg-accel-ops.c:79 #5 in cpu_interrupt (cpu=3D0x632000030800, mask=3D2) at ../softmmu/cpus= .c:248 #6 in loongarch_cpu_set_irq (opaque=3D0x632000030800, irq=3D11, level= =3D0) at ../target/loongarch/cpu.c:100 #7 in helper_csrwr_ticlr (env=3D0x632000039440, val=3D1) at ../target/l= oongarch/csr_helper.c:85 #8 in code_gen_buffer () #9 in cpu_tb_exec (cpu=3D0x632000030800, itb=3D0x7fff946ac280, tb_exit= =3D0x7ffe4fcb6c30) at ../accel/tcg/cpu-exec.c:358 Add mutex iothread lock around loongarch_cpu_set_irq in csrwr_ticlr() to fix the bug. Signed-off-by: Xiaojuan Yang --- target/loongarch/csr_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/loongarch/csr_helper.c b/target/loongarch/csr_helper.c index 24a9389364..7e02787895 100644 --- a/target/loongarch/csr_helper.c +++ b/target/loongarch/csr_helper.c @@ -81,7 +81,9 @@ target_ulong helper_csrwr_ticlr(CPULoongArchState *env, t= arget_ulong val) int64_t old_v =3D 0; =20 if (val & 0x1) { + qemu_mutex_lock_iothread(); loongarch_cpu_set_irq(cpu, IRQ_TIMER, 0); + qemu_mutex_unlock_iothread(); } return old_v; } --=20 2.31.1