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([2602:47:d49e:3c01:8adc:a144:6ec2:4d71]) by smtp.gmail.com with ESMTPSA id p66-20020a625b45000000b005252defb016sm3649674pfb.122.2022.06.21.13.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jun 2022 13:46:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h3YLx19yslSTTaLGcQTbBkJC0TNZDbNOKWylq2WnPkw=; b=wXRAJgeu88VAK0d4jbnRHsKr/e7hSkdPgzlcz+QpmuqS3cVaooJ6wm/+BVotY672p+ 80WHm1MqqCa9zvwk9gRaKKsK9yK1R5IrolEeLuFXBQAUUmJgzgdRuGbhuENnRe9srWTF EcJ4/V2jJYwLkH/Z4J1oL6KfnnaPy0tP8AjZkbbMP3M0lgQGjZ0KCDQJFdm7fkfsKNUn gAx158K3//zxJe1xJ8MO1yEAI6tTlzBtiBHG/7P3fakZcDssy0qJHd/xtnhXoEKpUZ8k msjJfq71ufwwyDG+e81YG0qW2+r4Edgp5KOfE+vp5tXo2Sum2QdR26VtLCwcuDXLY0iv 3mfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h3YLx19yslSTTaLGcQTbBkJC0TNZDbNOKWylq2WnPkw=; b=cX547mwzw2D9UzfYtIidO32h1ZylcVWDcL4hGsB+V7k4kPG9QNSgO+XAr3xMadGLLN fx6uzQ4rCQISXj6ukUrxd7WUSPoibcSODZa6IDY2ad1/2CbXRhCyno3gg1KlNq7uYCdt SHu3Pw+DLbrOXJwSNcHiqPWgwbth6IN28V0VSOaFxceLq3zybA9kH4lYtlOp2W3A+MZq LjJzIeJVCmdxtSMdDWvpyx++Z/uvlsucSiHfHexaHsPPMB+/XO23FBVPG724h28Pj0Wa +cpGzfKJCfpWDpxmGAU4WRbxB8uC5pnTyOgYcOocg6bCW2uV8h7tlDWON71wQi2qvYIu 8yIw== X-Gm-Message-State: AJIora/QpmM2dYuI4RWY6LEapxe+UMzLFJUrRu/ERys9rV+wwoWK0PKx tBpdi5pbqYB2bkqu00R1FXfT3hOfisCCRg== X-Google-Smtp-Source: AGRyM1vp/f24bvHX1yf0CJTqSf9XxQ/54rp66jKQeYax1Q5pi8oQWWl1WNSMRuMUkmrvBAylQb2Ntw== X-Received: by 2002:a63:4b02:0:b0:3fc:a31a:304 with SMTP id y2-20020a634b02000000b003fca31a0304mr27235325pga.121.1655844413118; Tue, 21 Jun 2022 13:46:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Peter Maydell Subject: [PULL 9/9] util/cacheflush: Optimize flushing when ppc host has coherent icache Date: Tue, 21 Jun 2022 13:46:43 -0700 Message-Id: <20220621204643.371397-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220621204643.371397-1-richard.henderson@linaro.org> References: <20220621204643.371397-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1655844908005100001 Content-Type: text/plain; charset="utf-8" From: Nicholas Piggin On linux, the AT_HWCAP bit PPC_FEATURE_ICACHE_SNOOP indicates that we can use a simplified 3 instruction flush sequence. Signed-off-by: Nicholas Piggin Message-Id: <20220519141131.29839-1-npiggin@gmail.com> [rth: update after merging cacheflush.c and cacheinfo.c] Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20220621014837.189139-4-richard.henderson@linaro.org> --- util/cacheflush.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/util/cacheflush.c b/util/cacheflush.c index 01b6cb7583..2c2c73e085 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -117,6 +117,10 @@ static void sys_cache_info(int *isize, int *dsize) * Architecture (+ OS) specific cache detection mechanisms. */ =20 +#if defined(__powerpc__) +static bool have_coherent_icache; +#endif + #if defined(__aarch64__) && !defined(CONFIG_DARWIN) /* Apple does not expose CTR_EL0, so we must use system interfaces. */ static uint64_t save_ctr_el0; @@ -156,6 +160,7 @@ static void arch_cache_info(int *isize, int *dsize) if (*dsize =3D=3D 0) { *dsize =3D qemu_getauxval(AT_DCACHEBSIZE); } + have_coherent_icache =3D qemu_getauxval(AT_HWCAP) & PPC_FEATURE_ICACHE= _SNOOP; } =20 #else @@ -298,8 +303,24 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, s= ize_t len) void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) { uintptr_t p, b, e; - size_t dsize =3D qemu_dcache_linesize; - size_t isize =3D qemu_icache_linesize; + size_t dsize, isize; + + /* + * Some processors have coherent caches and support a simplified + * flushing procedure. See + * POWER9 UM, 4.6.2.2 Instruction Cache Block Invalidate (icbi)=20 + * https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k + */ + if (have_coherent_icache) { + asm volatile ("sync\n\t" + "icbi 0,%0\n\t" + "isync" + : : "r"(rx) : "memory"); + return; + } + + dsize =3D qemu_dcache_linesize; + isize =3D qemu_icache_linesize; =20 b =3D rw & ~(dsize - 1); e =3D (rw + len + dsize - 1) & ~(dsize - 1); --=20 2.34.1