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([171.61.69.124]) by smtp.gmail.com with ESMTPSA id w1-20020a62c701000000b0050dc762814asm889025pfg.36.2022.06.11.01.02.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jun 2022 01:02:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BVHViNMuB7xKyupW6LMRK2DTrEYBRxgZhhJyysMzOXI=; b=K2vK2Ekqs2VRw14pfK+188Xunjtf4RMgkIrwvcwCkbQsHeP+UnU+8VqbghVX1GJ31t P/b5bIZyaW9Os5CUr0FI32LIe6GBX4HRnj8TyfChut1dAem1IYpdyMta68Li9UEngHvi ugtbMUS6PdTOTUV0w5FytlKIIL16bIHS9KWFt2q/gkeob33ibfIrWT2RwGkvjEHHBU4d tpBfLg74CQ8qLNlmrstRz4Rrni/jmBgj7IXu2gsYxzYdzju7sijvmAXz3hmYlARMCOeV rjBvBjbZM6KRpdTN9zgO13rY7xWNZu8fDLcp740cA/aJI7tmrHInZOHKJ0nT2MLBbOE5 7CSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BVHViNMuB7xKyupW6LMRK2DTrEYBRxgZhhJyysMzOXI=; b=gClOOM8lpU52K3DRBYQ7yDMUJmWbt+0UVKlbVpYT3wiJpkFUp7L6BHhGaXrgdlLoFS 3Ljp7YrgU86QBAqhxiQuzSzW5yNaqsZe3M+Hx1YAWPTGKe03c7vgM1lYnXNWoRk5C+rO 1eCdeHMnStQu3lgrtonNwGkX5VzJIgHKEmm/J2ApWH7PpqN/XcTEZnNYstLb6E5qp230 28uVTFSSqqnahzaywVwAJe7LKh2yQNmaxfXASa5cYB1Qpu4H15lKB0EiXu4/fNmgCv0d 3P2Wh2U5T6rMPst2mtU00d8Rwxqv3Bd5zWGSi2K1lKEYWySE2CKaXT2eCyMLP4YqmlQD YaFg== X-Gm-Message-State: AOAM531mJcviuZk1rI79+wcUIhb0ZmQ1t3xnYpmS1YHdwKGOdntdr+9Y pCL1BotERZXSwkmEQBKrBaLgng== X-Google-Smtp-Source: ABdhPJzNldIB4DrETIJ2gKBeV35RRXKWNU/cm299ziOfhSws6SwQGrvJG1C37mxT3MqfsG9sz1JxdA== X-Received: by 2002:a17:90b:247:b0:1e6:7f44:e385 with SMTP id fz7-20020a17090b024700b001e67f44e385mr3951162pjb.195.1654934534157; Sat, 11 Jun 2022 01:02:14 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Frank Chang , Alistair Francis , Bin Meng Subject: [PATCH v6 2/4] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher Date: Sat, 11 Jun 2022 13:31:05 +0530 Message-Id: <20220611080107.391981-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220611080107.391981-1-apatel@ventanamicro.com> References: <20220611080107.391981-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=apatel@ventanamicro.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1654935235766100001 Content-Type: text/plain; charset="utf-8" The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For implementation that don't want to implement can simply have a dummy mcountinhibit which is always zero. Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in th= e CSR ops.") Signed-off-by: Anup Patel Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 4d04b20d06..4a55c6a709 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -159,6 +159,9 @@ #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 =20 +/* Machine Counter Setup */ +#define CSR_MCOUNTINHIBIT 0x320 + /* 32-bit only */ #define CSR_MSTATUSH 0x310 =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6dbe9b541f..409a209f14 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3391,6 +3391,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MIE] =3D { "mie", any, NULL, NULL, rmw_mie= }, [CSR_MTVEC] =3D { "mtvec", any, read_mtvec, write_m= tvec }, [CSR_MCOUNTEREN] =3D { "mcounteren", any, read_mcounteren, write_m= counteren }, + [CSR_MCOUNTINHIBIT] =3D { "mcountinhibit", any, read_zero, write_ignor= e, + .min_priv_ver =3D PRIV_VERSIO= N_1_11_0 }, =20 [CSR_MSTATUSH] =3D { "mstatush", any32, read_mstatush, write_m= statush }, =20 --=20 2.34.1