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([171.61.69.124]) by smtp.gmail.com with ESMTPSA id w1-20020a62c701000000b0050dc762814asm889025pfg.36.2022.06.11.01.02.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jun 2022 01:02:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1t39f6wQstMi6nr3UEqkMVKQnbCIeTANssQ+YezQ/DE=; b=QwzDSkSNl95ekSmMZ0CpEQMEcACIEKRoiPE1YM0lGM7KgJl09xW733extMDezABP6C TtRfMGcolU6Gzy2oGtFKxo1nwcfA65cfDHP0Kz/tBYkJ6ttHGJ4WCzm62/XZ6e7+7rbh TqdJOoEr7gOLp1sIYWolb0N3HU3CxpaLV1/G4piEgWhHKct5jqrRHtQ8K1nXHIfbIHcg 8Vr/S51r1GNjCR13K0TrVLunUIj8UB5tOsvoFdBYnqSgJHDCeKEulFieyRS9c7wGr0fc OoEb/p9XLT7krK7HUKepoeoBPBfyJnj4F+NUsYN9CWwNC+D+UjrvF9WkTxR4nMfkchMo fZPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1t39f6wQstMi6nr3UEqkMVKQnbCIeTANssQ+YezQ/DE=; b=ECj1eWegGWAbbBYhxfy9oyEh6Y6uGwBSk5mjsPQF2uUlOlmjFLTe3+cgq7opRFoiTP rFG2Adi992dfAe4UrDk0I7ICAJNfhkUNtOtlDdCyWp70dDnHRvFZcwAje8GEE2umssE6 XDwuLUnaKXIScztMYmDshJ4+uIOs7wlGEr7q8lPBZhdx4h5TOckxiimlGWAbF1iyAwZD hyo0ZfxuT1ih96sNhZgrBvEDQsehlgz9AbsRqWe/jZDoSkEMBnQjfLPYLzKe04LhZRvZ 5YU9B070gQiO0t8PUANfLxUG4nbYharownnKRQ8WiimMRgK/4FNY92DnI7djFIV66uCm MGVg== X-Gm-Message-State: AOAM531vhfjjTFn2f2t+aYRTfKN/EScOBoJ2Ki6vDaJIj+img9UKjVf1 MIazedMsILileEnCG//qthXF0A== X-Google-Smtp-Source: ABdhPJz5tzWejoEK/+azgSLFAsJ56uk7Tw6za2TCbna8yHi9hMH2b68f6ZuX2cSTl1+cWDPWHDRxyg== X-Received: by 2002:a17:90b:1a8f:b0:1e8:7dfe:c4f with SMTP id ng15-20020a17090b1a8f00b001e87dfe0c4fmr3882784pjb.17.1654934529538; Sat, 11 Jun 2022 01:02:09 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Frank Chang , Alistair Francis , Atish Patra , Bin Meng Subject: [PATCH v6 1/4] target/riscv: Don't force update priv spec version to latest Date: Sat, 11 Jun 2022 13:31:04 +0530 Message-Id: <20220611080107.391981-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220611080107.391981-1-apatel@ventanamicro.com> References: <20220611080107.391981-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=apatel@ventanamicro.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1654935529847100001 Content-Type: text/plain; charset="utf-8" The riscv_cpu_realize() sets priv spec version to v1.12 when it is when "env->priv_ver =3D=3D 0" (i.e. default v1.10) because the enum value of priv spec v1.10 is zero. Due to above issue, the sifive_u machine will see priv spec v1.12 instead of priv spec v1.10. To fix this issue, we set latest priv spec version (i.e. v1.12) for base rv64/rv32 cpu and riscv_cpu_realize() will override priv spec version only when "cpu->cfg.priv_spec !=3D NULL". Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Anup Patel Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Atish Patra Reviewed-by: Bin Meng --- target/riscv/cpu.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 05e6521351..8db0f0bd49 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -173,6 +173,8 @@ static void rv64_base_cpu_init(Object *obj) /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); register_cpu_props(DEVICE(obj)); + /* Set latest version of privileged specification */ + set_priv_version(env, PRIV_VERSION_1_12_0); } =20 static void rv64_sifive_u_cpu_init(Object *obj) @@ -204,6 +206,8 @@ static void rv128_base_cpu_init(Object *obj) /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); register_cpu_props(DEVICE(obj)); + /* Set latest version of privileged specification */ + set_priv_version(env, PRIV_VERSION_1_12_0); } #else static void rv32_base_cpu_init(Object *obj) @@ -212,6 +216,8 @@ static void rv32_base_cpu_init(Object *obj) /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); register_cpu_props(DEVICE(obj)); + /* Set latest version of privileged specification */ + set_priv_version(env, PRIV_VERSION_1_12_0); } =20 static void rv32_sifive_u_cpu_init(Object *obj) @@ -524,7 +530,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); CPUClass *cc =3D CPU_CLASS(mcc); - int priv_version =3D 0; + int priv_version =3D -1; Error *local_err =3D NULL; =20 cpu_exec_realizefn(cs, &local_err); @@ -548,10 +554,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) } } =20 - if (priv_version) { + if (priv_version >=3D PRIV_VERSION_1_10_0) { set_priv_version(env, priv_version); - } else if (!env->priv_ver) { - set_priv_version(env, PRIV_VERSION_1_12_0); } =20 if (cpu->cfg.mmu) { --=20 2.34.1