From nobody Sat Feb 7 12:19:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1654935527; cv=none; d=zohomail.com; s=zohoarc; b=ZKpChfwqgBFkZiv7A8/GetRgW7oqLZGT8nuybaOUbPYDFTQn0wDo7r7vU4Ne650kS0E7rEUatTuUoEMSFJA9TO0MWvGmOxSxw7LxRl11XuK2h3z7c2n0dnHfdVKjJNrUDcD2XKKHm2I11dVWVqlxUQxjxeiNYCKYTY4JtBeosfE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654935527; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1t39f6wQstMi6nr3UEqkMVKQnbCIeTANssQ+YezQ/DE=; b=TFIfkeM1Vb96mLqFdB7kjcBMAqZoUej728n4ZiKBvlbgakBCyapK7rhFqRl8SpS+N6LVvKjL0pkXKXpO66gsKWOwSFEY/yStO90bnWEFpnp3Iql3sW7jm2Fh150jZLJYVP3Ao5lrMNRCz23xrU2rA1rqNs/hvE2wsWBbSFl08NA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654935527580488.07680919204915; Sat, 11 Jun 2022 01:18:47 -0700 (PDT) Received: from localhost ([::1]:48706 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzwKU-0007UW-Fs for importer@patchew.org; Sat, 11 Jun 2022 04:18:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54950) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzw4b-0003Jz-87 for qemu-devel@nongnu.org; Sat, 11 Jun 2022 04:02:23 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:45668) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzw4W-00020x-Nm for qemu-devel@nongnu.org; Sat, 11 Jun 2022 04:02:19 -0400 Received: by mail-pl1-x62e.google.com with SMTP id q18so1043818pln.12 for ; Sat, 11 Jun 2022 01:02:10 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.61.69.124]) by smtp.gmail.com with ESMTPSA id w1-20020a62c701000000b0050dc762814asm889025pfg.36.2022.06.11.01.02.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jun 2022 01:02:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1t39f6wQstMi6nr3UEqkMVKQnbCIeTANssQ+YezQ/DE=; b=QwzDSkSNl95ekSmMZ0CpEQMEcACIEKRoiPE1YM0lGM7KgJl09xW733extMDezABP6C TtRfMGcolU6Gzy2oGtFKxo1nwcfA65cfDHP0Kz/tBYkJ6ttHGJ4WCzm62/XZ6e7+7rbh TqdJOoEr7gOLp1sIYWolb0N3HU3CxpaLV1/G4piEgWhHKct5jqrRHtQ8K1nXHIfbIHcg 8Vr/S51r1GNjCR13K0TrVLunUIj8UB5tOsvoFdBYnqSgJHDCeKEulFieyRS9c7wGr0fc OoEb/p9XLT7krK7HUKepoeoBPBfyJnj4F+NUsYN9CWwNC+D+UjrvF9WkTxR4nMfkchMo fZPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1t39f6wQstMi6nr3UEqkMVKQnbCIeTANssQ+YezQ/DE=; b=ECj1eWegGWAbbBYhxfy9oyEh6Y6uGwBSk5mjsPQF2uUlOlmjFLTe3+cgq7opRFoiTP rFG2Adi992dfAe4UrDk0I7ICAJNfhkUNtOtlDdCyWp70dDnHRvFZcwAje8GEE2umssE6 XDwuLUnaKXIScztMYmDshJ4+uIOs7wlGEr7q8lPBZhdx4h5TOckxiimlGWAbF1iyAwZD hyo0ZfxuT1ih96sNhZgrBvEDQsehlgz9AbsRqWe/jZDoSkEMBnQjfLPYLzKe04LhZRvZ 5YU9B070gQiO0t8PUANfLxUG4nbYharownnKRQ8WiimMRgK/4FNY92DnI7djFIV66uCm MGVg== X-Gm-Message-State: AOAM531vhfjjTFn2f2t+aYRTfKN/EScOBoJ2Ki6vDaJIj+img9UKjVf1 MIazedMsILileEnCG//qthXF0A== X-Google-Smtp-Source: ABdhPJz5tzWejoEK/+azgSLFAsJ56uk7Tw6za2TCbna8yHi9hMH2b68f6ZuX2cSTl1+cWDPWHDRxyg== X-Received: by 2002:a17:90b:1a8f:b0:1e8:7dfe:c4f with SMTP id ng15-20020a17090b1a8f00b001e87dfe0c4fmr3882784pjb.17.1654934529538; Sat, 11 Jun 2022 01:02:09 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Frank Chang , Alistair Francis , Atish Patra , Bin Meng Subject: [PATCH v6 1/4] target/riscv: Don't force update priv spec version to latest Date: Sat, 11 Jun 2022 13:31:04 +0530 Message-Id: <20220611080107.391981-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220611080107.391981-1-apatel@ventanamicro.com> References: <20220611080107.391981-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=apatel@ventanamicro.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1654935529847100001 Content-Type: text/plain; charset="utf-8" The riscv_cpu_realize() sets priv spec version to v1.12 when it is when "env->priv_ver =3D=3D 0" (i.e. default v1.10) because the enum value of priv spec v1.10 is zero. Due to above issue, the sifive_u machine will see priv spec v1.12 instead of priv spec v1.10. To fix this issue, we set latest priv spec version (i.e. v1.12) for base rv64/rv32 cpu and riscv_cpu_realize() will override priv spec version only when "cpu->cfg.priv_spec !=3D NULL". Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Anup Patel Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Atish Patra Reviewed-by: Bin Meng --- target/riscv/cpu.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 05e6521351..8db0f0bd49 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -173,6 +173,8 @@ static void rv64_base_cpu_init(Object *obj) /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); register_cpu_props(DEVICE(obj)); + /* Set latest version of privileged specification */ + set_priv_version(env, PRIV_VERSION_1_12_0); } =20 static void rv64_sifive_u_cpu_init(Object *obj) @@ -204,6 +206,8 @@ static void rv128_base_cpu_init(Object *obj) /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); register_cpu_props(DEVICE(obj)); + /* Set latest version of privileged specification */ + set_priv_version(env, PRIV_VERSION_1_12_0); } #else static void rv32_base_cpu_init(Object *obj) @@ -212,6 +216,8 @@ static void rv32_base_cpu_init(Object *obj) /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); register_cpu_props(DEVICE(obj)); + /* Set latest version of privileged specification */ + set_priv_version(env, PRIV_VERSION_1_12_0); } =20 static void rv32_sifive_u_cpu_init(Object *obj) @@ -524,7 +530,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); CPUClass *cc =3D CPU_CLASS(mcc); - int priv_version =3D 0; + int priv_version =3D -1; Error *local_err =3D NULL; =20 cpu_exec_realizefn(cs, &local_err); @@ -548,10 +554,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) } } =20 - if (priv_version) { + if (priv_version >=3D PRIV_VERSION_1_10_0) { set_priv_version(env, priv_version); - } else if (!env->priv_ver) { - set_priv_version(env, PRIV_VERSION_1_12_0); } =20 if (cpu->cfg.mmu) { --=20 2.34.1 From nobody Sat Feb 7 12:19:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1654935234; cv=none; d=zohomail.com; s=zohoarc; b=RKJAcE5T1MXBPgF57W3GSgIds7iQhND+HIHGyWIBLBUKLWPAPSmnXnZbkhxVXGzM5QiG1xucOrWJMCcXbgVZNQGxNmJ59s8efkdTfLiP/oPmGAf4vzPoyz1MOm5QDeoiANHv4D4ya6MQ1ohCnyz5oJuxBmEGLmpi7oZa5+paCqo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654935234; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BVHViNMuB7xKyupW6LMRK2DTrEYBRxgZhhJyysMzOXI=; b=mOFOpSgzjmvurMrC1Kg5gQz/kyeFwcS+5fSbUwPVHmngET2KVwOkYhmNlET0GvtULnwu3yZMv7cl5GRv8REPwjguSRsA5Tq77JeVGTzGL+nZjKxsKcFBlkTULaQOkEDGBpUTueWsz5FjHjtJOY0ZuGpl78AtNkDaEN0lOYGdlyU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654935234780643.5692046688125; Sat, 11 Jun 2022 01:13:54 -0700 (PDT) Received: from localhost ([::1]:42200 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzwFl-00031Z-OR for importer@patchew.org; Sat, 11 Jun 2022 04:13:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54960) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzw4b-0003K2-Ck for qemu-devel@nongnu.org; Sat, 11 Jun 2022 04:02:23 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:36474) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzw4Y-00021E-Li for qemu-devel@nongnu.org; Sat, 11 Jun 2022 04:02:21 -0400 Received: by mail-pl1-x62a.google.com with SMTP id u18so1080687plb.3 for ; Sat, 11 Jun 2022 01:02:15 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.61.69.124]) by smtp.gmail.com with ESMTPSA id w1-20020a62c701000000b0050dc762814asm889025pfg.36.2022.06.11.01.02.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jun 2022 01:02:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BVHViNMuB7xKyupW6LMRK2DTrEYBRxgZhhJyysMzOXI=; b=K2vK2Ekqs2VRw14pfK+188Xunjtf4RMgkIrwvcwCkbQsHeP+UnU+8VqbghVX1GJ31t P/b5bIZyaW9Os5CUr0FI32LIe6GBX4HRnj8TyfChut1dAem1IYpdyMta68Li9UEngHvi ugtbMUS6PdTOTUV0w5FytlKIIL16bIHS9KWFt2q/gkeob33ibfIrWT2RwGkvjEHHBU4d tpBfLg74CQ8qLNlmrstRz4Rrni/jmBgj7IXu2gsYxzYdzju7sijvmAXz3hmYlARMCOeV rjBvBjbZM6KRpdTN9zgO13rY7xWNZu8fDLcp740cA/aJI7tmrHInZOHKJ0nT2MLBbOE5 7CSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BVHViNMuB7xKyupW6LMRK2DTrEYBRxgZhhJyysMzOXI=; b=gClOOM8lpU52K3DRBYQ7yDMUJmWbt+0UVKlbVpYT3wiJpkFUp7L6BHhGaXrgdlLoFS 3Ljp7YrgU86QBAqhxiQuzSzW5yNaqsZe3M+Hx1YAWPTGKe03c7vgM1lYnXNWoRk5C+rO 1eCdeHMnStQu3lgrtonNwGkX5VzJIgHKEmm/J2ApWH7PpqN/XcTEZnNYstLb6E5qp230 28uVTFSSqqnahzaywVwAJe7LKh2yQNmaxfXASa5cYB1Qpu4H15lKB0EiXu4/fNmgCv0d 3P2Wh2U5T6rMPst2mtU00d8Rwxqv3Bd5zWGSi2K1lKEYWySE2CKaXT2eCyMLP4YqmlQD YaFg== X-Gm-Message-State: AOAM531mJcviuZk1rI79+wcUIhb0ZmQ1t3xnYpmS1YHdwKGOdntdr+9Y pCL1BotERZXSwkmEQBKrBaLgng== X-Google-Smtp-Source: ABdhPJzNldIB4DrETIJ2gKBeV35RRXKWNU/cm299ziOfhSws6SwQGrvJG1C37mxT3MqfsG9sz1JxdA== X-Received: by 2002:a17:90b:247:b0:1e6:7f44:e385 with SMTP id fz7-20020a17090b024700b001e67f44e385mr3951162pjb.195.1654934534157; Sat, 11 Jun 2022 01:02:14 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Frank Chang , Alistair Francis , Bin Meng Subject: [PATCH v6 2/4] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher Date: Sat, 11 Jun 2022 13:31:05 +0530 Message-Id: <20220611080107.391981-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220611080107.391981-1-apatel@ventanamicro.com> References: <20220611080107.391981-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=apatel@ventanamicro.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1654935235766100001 Content-Type: text/plain; charset="utf-8" The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For implementation that don't want to implement can simply have a dummy mcountinhibit which is always zero. Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in th= e CSR ops.") Signed-off-by: Anup Patel Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 4d04b20d06..4a55c6a709 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -159,6 +159,9 @@ #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 =20 +/* Machine Counter Setup */ +#define CSR_MCOUNTINHIBIT 0x320 + /* 32-bit only */ #define CSR_MSTATUSH 0x310 =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6dbe9b541f..409a209f14 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3391,6 +3391,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MIE] =3D { "mie", any, NULL, NULL, rmw_mie= }, [CSR_MTVEC] =3D { "mtvec", any, read_mtvec, write_m= tvec }, [CSR_MCOUNTEREN] =3D { "mcounteren", any, read_mcounteren, write_m= counteren }, + [CSR_MCOUNTINHIBIT] =3D { "mcountinhibit", any, read_zero, write_ignor= e, + .min_priv_ver =3D PRIV_VERSIO= N_1_11_0 }, =20 [CSR_MSTATUSH] =3D { "mstatush", any32, read_mstatush, write_m= statush }, =20 --=20 2.34.1 From nobody Sat Feb 7 12:19:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1654935041; cv=none; d=zohomail.com; s=zohoarc; b=KUcUXtz20iX+RJtCNFG8N0g9LqfoP/3iV7pB7R0wUjQTjLWRerXSIOJbIibaWyW2OjG5jOvYEBGmI+6JOggsgwTZP4vA8s96RiwxYXDathDThwam0bYdbgQ8m06/TvfnKH9EbMPIfeXoE9G4ZhgGCk2DLz+IBZgTARaIS4ZJPS4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654935041; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=i9ke3AYUGcAWv+fjyF0jLI3DRp9k9U+qqGkWC4Z5lKw=; b=NzZheMS3nEJx1OhExxIug9dpXNTZr0R5efVgzlrU1JXx6+yBSitAMNJW4+aw7J1qsKGqOW+uxl6w13s1qV0x73c2xPmY8hmPn4Lonfz/iNGL0AWQLEBdeIQ4lkYSvVEmlSkceMfhrMHdhEkBcbw6rnId5MjkAH4drqI5nCueUcQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654935041322493.2783752241942; Sat, 11 Jun 2022 01:10:41 -0700 (PDT) Received: from localhost ([::1]:35630 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nzwCd-0006y8-Me for importer@patchew.org; Sat, 11 Jun 2022 04:10:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54998) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nzw4d-0003KA-GZ for qemu-devel@nongnu.org; Sat, 11 Jun 2022 04:02:24 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:45797) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nzw4a-00021O-UF for qemu-devel@nongnu.org; Sat, 11 Jun 2022 04:02:23 -0400 Received: by mail-pg1-x52a.google.com with SMTP id 184so1161781pga.12 for ; Sat, 11 Jun 2022 01:02:19 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.61.69.124]) by smtp.gmail.com with ESMTPSA id w1-20020a62c701000000b0050dc762814asm889025pfg.36.2022.06.11.01.02.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jun 2022 01:02:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=i9ke3AYUGcAWv+fjyF0jLI3DRp9k9U+qqGkWC4Z5lKw=; b=m01auRIcwcx9AJgNuYESVFGg7xCcPX9Fq8rLpJsJwBwa7cdNg2jeOc1gQnPilyKuoR MergRsmJ2y95jB5kKqyvQFd8+1c9RHpmFxJaLOX1mk1lfVxDdKO0DCwrXpbgApBHd8QQ 8c/xssXMKMXhuyqrw7r/nB6RgXxY0/Y5uVA2kC/h+csuuFDuTtOM+MIO2JyXuxYEuz61 dCvC1ztD0aWHjZWYf54mefgT0SS7JJUrk0Aykr3E0wUwWoxh71eljiDd0/Ipy9M2bYFi Li0QG4FDykdzYoU5M1eVoWNmv6UmgEVdRb1HVfeQhpUDQ8dtDQtQqC467AbQ8qeG2Z07 8BVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=i9ke3AYUGcAWv+fjyF0jLI3DRp9k9U+qqGkWC4Z5lKw=; b=8OipNrUmdKUBCPwxm0Hzg312l89BpbxpIxQMML2U+rVC034CL8tgtOoR4m3cKuM6pe dWLBWmDUM05x623csmlHLwaRzyUL4gQFAkZ21QBBDs0NSrVdjcP7RItbj724SznrhQvK l3FG+U2lK2bygkVXkqKepoM9o6edVPrvMkuO/etyFmPUiWhIcQJy6ogUX0PFdwY89dFt K+ThCIAmXtHVOG1FJFmB1CvUn8Byrqd+3RDg3N0YR/meeVUPSqyiiYXXLVnGwVHdT1N1 KKjEYRE9syWGoubB2KVYlYLOyWGzfR9H2BYqK1e4bPrFnUb3qVs0JRoMEK78QU8IySJ+ 0VbQ== X-Gm-Message-State: AOAM533CL6VN3Sd/EFfhzsh6yR4ELkrqB/9sj/sp9An5oeiWNMFJQPYx 6aQLKjxvm3mVzEc1pu9Rpmb7XA== X-Google-Smtp-Source: ABdhPJzBC4215yO1SpmtSbth8n9KB7JGNUS43d74r1o78atWgZUrU0ZSm03T9bbgyZoV8ZFqr9QX2Q== X-Received: by 2002:a62:7b94:0:b0:51b:c723:5724 with SMTP id w142-20020a627b94000000b0051bc7235724mr47891990pfc.8.1654934538089; Sat, 11 Jun 2022 01:02:18 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v6 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() Date: Sat, 11 Jun 2022 13:31:06 +0530 Message-Id: <20220611080107.391981-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220611080107.391981-1-apatel@ventanamicro.com> References: <20220611080107.391981-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=apatel@ventanamicro.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1654935042702100001 Content-Type: text/plain; charset="utf-8" We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 3 + target/riscv/cpu_helper.c | 214 ++++++++++++++++++++++++++++++++++++-- target/riscv/instmap.h | 45 ++++++++ 3 files changed, 256 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7d6397acdf..cac9e1876c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -271,6 +271,9 @@ struct CPUArchState { /* Signals whether the current exception occurred with two-stage addre= ss translation active. */ bool two_stage_lookup; + /* Signals whether the current exception occurred while doing two-stage + address translation for the VS-stage page table walk. */ + bool two_stage_indirect_lookup; =20 target_ulong scounteren; target_ulong mcounteren; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4a6700c890..3c8ebecf84 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -22,6 +22,7 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "exec/exec-all.h" +#include "instmap.h" #include "tcg/tcg-op.h" #include "trace.h" #include "semihosting/common-semi.h" @@ -1057,7 +1058,8 @@ restart: =20 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, MMUAccessType access_type, bool pmp_violat= ion, - bool first_stage, bool two_stage) + bool first_stage, bool two_stage, + bool two_stage_indirect) { CPUState *cs =3D env_cpu(env); int page_fault_exceptions, vm; @@ -1107,6 +1109,7 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, } env->badaddr =3D address; env->two_stage_lookup =3D two_stage; + env->two_stage_indirect_lookup =3D two_stage_indirect; } =20 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) @@ -1152,6 +1155,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hw= addr physaddr, env->badaddr =3D addr; env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); + env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); } =20 @@ -1177,6 +1181,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, env->badaddr =3D addr; env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); + env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); } =20 @@ -1192,6 +1197,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, bool pmp_violation =3D false; bool first_stage_error =3D true; bool two_stage_lookup =3D false; + bool two_stage_indirect_error =3D false; int ret =3D TRANSLATE_FAIL; int mode =3D mmu_idx; /* default TLB page size */ @@ -1229,6 +1235,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, */ if (ret =3D=3D TRANSLATE_G_STAGE_FAIL) { first_stage_error =3D false; + two_stage_indirect_error =3D true; access_type =3D MMU_DATA_LOAD; } =20 @@ -1312,12 +1319,182 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr addres= s, int size, raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error, riscv_cpu_virt_enabled(env) || - riscv_cpu_two_stage_lookup(mmu_idx)); + riscv_cpu_two_stage_lookup(mmu_idx), + two_stage_indirect_error); cpu_loop_exit_restore(cs, retaddr); } =20 return true; } + +static target_ulong riscv_transformed_insn(CPURISCVState *env, + target_ulong insn, + bool addr_offset_nonzero, + target_ulong taddr) +{ + target_ulong xinsn =3D 0, xinsn_access_bits =3D 0; + + /* + * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to + * be uncompressed. The Quadrant 1 of RVC instruction space need + * not be transformed because these instructions won't generate + * any load/store trap. + */ + + if ((insn & 0x3) !=3D 0x3) { + /* Transform 16bit instruction into 32bit instruction */ + switch (GET_C_OP(insn)) { + case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ + switch (GET_C_FUNC(insn)) { + case OPC_RISC_C_FUNC_FLD_LQ: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FLD (RV32/64) */ + xinsn =3D OPC_RISC_FLD; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn_access_bits =3D 3; + } + break; + case OPC_RISC_C_FUNC_LW: /* C.LW */ + xinsn =3D OPC_RISC_LW; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn_access_bits =3D 2; + break; + case OPC_RISC_C_FUNC_FLW_LD: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FLW (RV32) */ + xinsn =3D OPC_RISC_FLW; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn_access_bits =3D 2; + } else { /* C.LD (RV64/RV128) */ + xinsn =3D OPC_RISC_LD; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn_access_bits =3D 3; + } + break; + case OPC_RISC_C_FUNC_FSD_SQ: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FSD (RV32/64) */ + xinsn =3D OPC_RISC_FSD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn_access_bits =3D 3; + } + break; + case OPC_RISC_C_FUNC_SW: /* C.SW */ + xinsn =3D OPC_RISC_SW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn_access_bits =3D 2; + break; + case OPC_RISC_C_FUNC_FSW_SD: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FSW (RV32) */ + xinsn =3D OPC_RISC_FSW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn_access_bits =3D 2; + } else { /* C.SD (RV64/RV128) */ + xinsn =3D OPC_RISC_SD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn_access_bits =3D 3; + } + break; + default: + break; + } + break; + case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ + switch (GET_C_FUNC(insn)) { + case OPC_RISC_C_FUNC_FLDSP_LQSP: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FLDSP (RV32/64) */ + xinsn =3D OPC_RISC_FLD; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + xinsn_access_bits =3D 3; + } + break; + case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ + xinsn =3D OPC_RISC_LW; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + xinsn_access_bits =3D 2; + break; + case OPC_RISC_C_FUNC_FLWSP_LDSP: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FLWSP (RV32) */ + xinsn =3D OPC_RISC_FLW; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + xinsn_access_bits =3D 2; + } else { /* C.LDSP (RV64/RV128) */ + xinsn =3D OPC_RISC_LD; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + xinsn_access_bits =3D 3; + } + break; + case OPC_RISC_C_FUNC_FSDSP_SQSP: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FSDSP (RV32/64) */ + xinsn =3D OPC_RISC_FSD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn_access_bits =3D 3; + } + break; + case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ + xinsn =3D OPC_RISC_SW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn_access_bits =3D 2; + break; + case 7: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FSWSP (RV32) */ + xinsn =3D OPC_RISC_FSW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn_access_bits =3D 2; + } else { /* C.SDSP (RV64/RV128) */ + xinsn =3D OPC_RISC_SD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn_access_bits =3D 3; + } + break; + default: + break; + } + break; + default: + break; + } + + /* + * Clear Bit1 of transformed instruction to indicate that + * original insruction was a 16bit instruction + */ + xinsn &=3D ~((target_ulong)0x2); + } else { + /* Transform 32bit (or wider) instructions */ + switch (MASK_OP_MAJOR(insn)) { + case OPC_RISC_ATOMIC: + xinsn =3D insn; + xinsn_access_bits =3D GET_FUNCT3(xinsn); + break; + case OPC_RISC_LOAD: + case OPC_RISC_FP_LOAD: + xinsn =3D insn; + xinsn_access_bits =3D GET_FUNCT3(xinsn); + xinsn =3D SET_I_IMM(xinsn, 0); + break; + case OPC_RISC_STORE: + case OPC_RISC_FP_STORE: + xinsn =3D insn; + xinsn_access_bits =3D GET_FUNCT3(xinsn); + xinsn =3D SET_S_IMM(xinsn, 0); + break; + case OPC_RISC_SYSTEM: + if (MASK_OP_SYSTEM(insn) =3D=3D OPC_RISC_HLVHSV) { + xinsn =3D insn; + xinsn_access_bits =3D 1 << ((GET_FUNCT7(xinsn) >> 1) & 0x= 3); + } + break; + default: + break; + } + } + + if (addr_offset_nonzero) { + xinsn =3D SET_RS1(xinsn, taddr & ((1 << xinsn_access_bits) - 1)); + } else { + xinsn =3D SET_RS1(xinsn, 0); + } + + return xinsn; +} #endif /* !CONFIG_USER_ONLY */ =20 /* @@ -1342,6 +1519,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong cause =3D cs->exception_index & RISCV_EXCP_INT_MASK; uint64_t deleg =3D async ? env->mideleg : env->medeleg; target_ulong tval =3D 0; + target_ulong tinst =3D 0; target_ulong htval =3D 0; target_ulong mtval2 =3D 0; =20 @@ -1357,18 +1535,39 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { - case RISCV_EXCP_INST_GUEST_PAGE_FAULT: case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: - case RISCV_EXCP_INST_ADDR_MIS: - case RISCV_EXCP_INST_ACCESS_FAULT: case RISCV_EXCP_LOAD_ADDR_MIS: case RISCV_EXCP_STORE_AMO_ADDR_MIS: case RISCV_EXCP_LOAD_ACCESS_FAULT: case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: - case RISCV_EXCP_INST_PAGE_FAULT: case RISCV_EXCP_LOAD_PAGE_FAULT: case RISCV_EXCP_STORE_PAGE_FAULT: + write_gva =3D env->two_stage_lookup; + tval =3D env->badaddr; + if (env->two_stage_indirect_lookup) { + /* + * special pseudoinstruction for G-stage fault taken while + * doing VS-stage page table walk. + */ + tinst =3D (riscv_cpu_xlen(env) =3D=3D 32) ? 0x00002000 : 0= x00003000; + } else { + /* + * The "Addr. Offset" field in transformed instruction is + * non-zero only for misaligned load/store traps. + */ + if (cause =3D=3D RISCV_EXCP_LOAD_ADDR_MIS || + cause =3D=3D RISCV_EXCP_STORE_AMO_ACCESS_FAULT) { + tinst =3D riscv_transformed_insn(env, env->bins, true,= tval); + } else { + tinst =3D riscv_transformed_insn(env, env->bins, false= , tval); + } + } + break; + case RISCV_EXCP_INST_GUEST_PAGE_FAULT: + case RISCV_EXCP_INST_ADDR_MIS: + case RISCV_EXCP_INST_ACCESS_FAULT: + case RISCV_EXCP_INST_PAGE_FAULT: write_gva =3D env->two_stage_lookup; tval =3D env->badaddr; break; @@ -1450,6 +1649,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->sepc =3D env->pc; env->stval =3D tval; env->htval =3D htval; + env->htinst =3D tinst; env->pc =3D (env->stvec >> 2 << 2) + ((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_S); @@ -1480,6 +1680,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mepc =3D env->pc; env->mtval =3D tval; env->mtval2 =3D mtval2; + env->mtinst =3D tinst; env->pc =3D (env->mtvec >> 2 << 2) + ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_M); @@ -1492,6 +1693,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) */ =20 env->two_stage_lookup =3D false; + env->two_stage_indirect_lookup =3D false; #endif cs->exception_index =3D RISCV_EXCP_NONE; /* mark handled to qemu */ } diff --git a/target/riscv/instmap.h b/target/riscv/instmap.h index 40b6d2b64d..f877530576 100644 --- a/target/riscv/instmap.h +++ b/target/riscv/instmap.h @@ -184,6 +184,8 @@ enum { OPC_RISC_CSRRWI =3D OPC_RISC_SYSTEM | (0x5 << 12), OPC_RISC_CSRRSI =3D OPC_RISC_SYSTEM | (0x6 << 12), OPC_RISC_CSRRCI =3D OPC_RISC_SYSTEM | (0x7 << 12), + + OPC_RISC_HLVHSV =3D OPC_RISC_SYSTEM | (0x4 << 12), }; =20 #define MASK_OP_FP_LOAD(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) @@ -310,12 +312,20 @@ enum { | (extract32(inst, 12, 8) << 12) \ | (sextract64(inst, 31, 1) << 20)) =20 +#define GET_FUNCT3(inst) extract32(inst, 12, 3) +#define GET_FUNCT7(inst) extract32(inst, 25, 7) #define GET_RM(inst) extract32(inst, 12, 3) #define GET_RS3(inst) extract32(inst, 27, 5) #define GET_RS1(inst) extract32(inst, 15, 5) #define GET_RS2(inst) extract32(inst, 20, 5) #define GET_RD(inst) extract32(inst, 7, 5) #define GET_IMM(inst) sextract64(inst, 20, 12) +#define SET_RS1(inst, val) deposit32(inst, 15, 5, val) +#define SET_RS2(inst, val) deposit32(inst, 20, 5, val) +#define SET_RD(inst, val) deposit32(inst, 7, 5, val) +#define SET_I_IMM(inst, val) deposit32(inst, 20, 12, val) +#define SET_S_IMM(inst, val) \ + deposit32(deposit32(inst, 7, 5, val), 25, 7, (val) >> 5) =20 /* RVC decoding macros */ #define GET_C_IMM(inst) (extract32(inst, 2, 5) \ @@ -346,6 +356,8 @@ enum { | (extract32(inst, 5, 1) << 6)) #define GET_C_LD_IMM(inst) ((extract16(inst, 10, 3) << 3) \ | (extract16(inst, 5, 2) << 6)) +#define GET_C_SW_IMM(inst) GET_C_LW_IMM(inst) +#define GET_C_SD_IMM(inst) GET_C_LD_IMM(inst) #define GET_C_J_IMM(inst) ((extract32(inst, 3, 3) << 1) \ | (extract32(inst, 11, 1) << 4) \ | (extract32(inst, 2, 1) << 5) \ @@ -366,4 +378,37 @@ enum { #define GET_C_RS1S(inst) (8 + extract16(inst, 7, 3)) #define GET_C_RS2S(inst) (8 + extract16(inst, 2, 3)) =20 +#define GET_C_FUNC(inst) extract32(inst, 13, 3) +#define GET_C_OP(inst) extract32(inst, 0, 2) + +enum { + /* RVC Quadrants */ + OPC_RISC_C_OP_QUAD0 =3D 0x0, + OPC_RISC_C_OP_QUAD1 =3D 0x1, + OPC_RISC_C_OP_QUAD2 =3D 0x2 +}; + +enum { + /* RVC Quadrant 0 */ + OPC_RISC_C_FUNC_ADDI4SPN =3D 0x0, + OPC_RISC_C_FUNC_FLD_LQ =3D 0x1, + OPC_RISC_C_FUNC_LW =3D 0x2, + OPC_RISC_C_FUNC_FLW_LD =3D 0x3, + OPC_RISC_C_FUNC_FSD_SQ =3D 0x5, + OPC_RISC_C_FUNC_SW =3D 0x6, + OPC_RISC_C_FUNC_FSW_SD =3D 0x7 +}; + +enum { + /* RVC Quadrant 2 */ + OPC_RISC_C_FUNC_SLLI_SLLI64 =3D 0x0, + OPC_RISC_C_FUNC_FLDSP_LQSP =3D 0x1, + OPC_RISC_C_FUNC_LWSP =3D 0x2, + OPC_RISC_C_FUNC_FLWSP_LDSP =3D 0x3, + OPC_RISC_C_FUNC_JR_MV_EBREAK_JALR_ADD =3D 0x4, + OPC_RISC_C_FUNC_FSDSP_SQSP =3D 0x5, + OPC_RISC_C_FUNC_SWSP =3D 0x6, + OPC_RISC_C_FUNC_FSWSP_SDSP =3D 0x7 +}; + #endif --=20 2.34.1 From nobody Sat Feb 7 12:19:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1654935042; cv=none; d=zohomail.com; s=zohoarc; b=ZOqZ2QDzPqL4Hw1XrY8N1nsTP+KZhIBVPxTjIJURq0oBNpkI/5TMycPiT3SUY1nrjWZu8p1rLTEN0dxCrCxUePdqSPToIIjeg+G31LFCmWbqfdjdQjg00vZdZejbGSuDQ4dYlrBlzOv1BGjp6siZIMFhArgz8vCslQ/GZXDbxo8= ARC-Message-Signature: i=1; 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([171.61.69.124]) by smtp.gmail.com with ESMTPSA id w1-20020a62c701000000b0050dc762814asm889025pfg.36.2022.06.11.01.02.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jun 2022 01:02:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bT8Lyq+ZYT12WD1AjkmxS7vGoWu+xHrdF0EpZMa0gbI=; b=VFkjLGXsc3x6EG6sO0CmzDl1bSfeaTC29o1ws7rU7IOC8ptw2pA8xd6V+hZGAnL8+9 mfGNFT2lAh4NSrUtx2NZyRiVkuNk+rE0vHQsXeBTYxqpo4/qQTem3ycl/J46ff+61x2m V7OcyZKxIVq4kfj//QBLvvsT9pVrOtCCfsLvX49JLnNrmp29ggL5VTvFvA1AJjRvWLPP JUcm6hTeGbMu80YRgz9ATTvFQSIs2Sb2Gj/EdhdY1NuHutEk/oeku3HixaSGtB4gPeoy +1QSa1lrv9XYcgDBERKW2gXkpAqKXCu0T+1Z1g5VS3CuUeSSlPE7IrOFKG3EpSUa/ASF eJJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bT8Lyq+ZYT12WD1AjkmxS7vGoWu+xHrdF0EpZMa0gbI=; b=Yl6nYYL/u5DADIsRs3pLpFNE1BxaS5uYbFUMeQ7ciK3hs93NtBXd9krtaHjIOP6dEI MvOdnx79Lur6AXctydc/Ki/dzUHzDxIP22whxEYEzINc3teHsdpJFdElyKcJUImxv7CX 7X989uTCNJT7+QA7yWE78jMvnjcUdDmddtVzWXpe3Qz5Dm1RiXEZf2TxE5R1gRA99ISL goRfr0AWP52dtd8O+LyGSj2e0wn1ViBeKVuQCtu/IVhCWpdIC+p1mxbhy+yuV1oJTZA8 e1+uARoI2FoIPevk0tpoTF/6UjE8b2QW0Voi0qBocIuV9fh6TCwPMhR0THBwdX0fGOmm 9yJQ== X-Gm-Message-State: AOAM5313A0b5r5Vtf8nS/y5OoTYp+Nno5Ea3iOIeH6qzDf5+xJJV0tw6 5WOox2LUd/PTSYqVDbRfQbVeqw== X-Google-Smtp-Source: ABdhPJwEyn3MbvhuNNWcZEU3XRn7+/cYifhn5751cQVvPgqvEhXGwCjNo53xZ6VsTN6ccliq4xetyg== X-Received: by 2002:a17:902:6901:b0:168:9bb4:7adb with SMTP id j1-20020a170902690100b001689bb47adbmr16699206plk.147.1654934542162; Sat, 11 Jun 2022 01:02:22 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v6 4/4] target/riscv: Force disable extensions if priv spec version does not match Date: Sat, 11 Jun 2022 13:31:07 +0530 Message-Id: <20220611080107.391981-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220611080107.391981-1-apatel@ventanamicro.com> References: <20220611080107.391981-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1654935043938100003 Content-Type: text/plain; charset="utf-8" We should disable extensions in riscv_cpu_realize() if minimum required priv spec version is not satisfied. This also ensures that machines with priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter extensions. Fixes: a775398be2e9 ("target/riscv: Add isa extenstion strings to the devic= e tree") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 144 +++++++++++++++++++++++++++------------------ 1 file changed, 88 insertions(+), 56 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8db0f0bd49..a17bc98662 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -43,9 +43,82 @@ static const char riscv_single_letter_exts[] =3D "IEMAFD= QCPVH"; =20 struct isa_ext_data { const char *name; - bool enabled; + bool multi_letter; + int min_version; + int ext_enable_offset; }; =20 +#define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ +{#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} + +/** + * Here are the ordering rules of extension naming defined by RISC-V + * specification : + * 1. All extensions should be separated from other multi-letter extensions + * by an underscore. + * 2. The first letter following the 'Z' conventionally indicates the most + * closely related alphabetical extension category, IMAFDQLCBKJTPVH. + * If multiple 'Z' extensions are named, they should be ordered first + * by category, then alphabetically within a category. + * 3. Standard supervisor-level extensions (starts with 'S') should be + * listed after standard unprivileged extensions. If multiple + * supervisor-level extensions are listed, they should be ordered + * alphabetically. + * 4. Non-standard extensions (starts with 'X') must be listed after all + * standard extensions. They must be separated from other multi-letter + * extensions by an underscore. + */ +static const struct isa_ext_data isa_edata_arr[] =3D { + ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), + ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), + ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), + ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), + ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), + ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), + ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), + ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), + ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), + ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), + ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), + ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), + ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), + ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), + ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), + ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), + ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), + ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), + ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), + ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), + ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), + ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), + ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), + ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), + ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), + ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), + ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), + ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), + ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), + ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), + ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), +}; + +static bool isa_ext_is_enabled(RISCVCPU *cpu, + const struct isa_ext_data *edata) +{ + bool *ext_enabled =3D (void *)&cpu->cfg + edata->ext_enable_offset; + + return *ext_enabled; +} + +static void isa_ext_update_enabled(RISCVCPU *cpu, + const struct isa_ext_data *edata, bool = en) +{ + bool *ext_enabled =3D (void *)&cpu->cfg + edata->ext_enable_offset; + + *ext_enabled =3D en; +} + const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -530,7 +603,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); CPUClass *cc =3D CPU_CLASS(mcc); - int priv_version =3D -1; + int i, priv_version =3D -1; Error *local_err =3D NULL; =20 cpu_exec_realizefn(cs, &local_err); @@ -558,6 +631,17 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) set_priv_version(env, priv_version); } =20 + /* Force disable extensions if priv spec version does not match */ + for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { + if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && + (env->priv_ver < isa_edata_arr[i].min_version)) { + isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); + warn_report("disabling %s extension for hart 0x%lx because " + "privilege spec version does not match", + isa_edata_arr[i].name, (unsigned long)env->mhartid= ); + } + } + if (cpu->cfg.mmu) { riscv_set_feature(env, RISCV_FEATURE_MMU); } @@ -1050,67 +1134,15 @@ static void riscv_cpu_class_init(ObjectClass *c, vo= id *data) device_class_set_props(dc, riscv_cpu_properties); } =20 -#define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop} - static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_st= r_len) { char *old =3D *isa_str; char *new =3D *isa_str; int i; =20 - /** - * Here are the ordering rules of extension naming defined by RISC-V - * specification : - * 1. All extensions should be separated from other multi-letter exten= sions - * by an underscore. - * 2. The first letter following the 'Z' conventionally indicates the = most - * closely related alphabetical extension category, IMAFDQLCBKJTPVH. - * If multiple 'Z' extensions are named, they should be ordered fir= st - * by category, then alphabetically within a category. - * 3. Standard supervisor-level extensions (starts with 'S') should be - * listed after standard unprivileged extensions. If multiple - * supervisor-level extensions are listed, they should be ordered - * alphabetically. - * 4. Non-standard extensions (starts with 'X') must be listed after a= ll - * standard extensions. They must be separated from other multi-let= ter - * extensions by an underscore. - */ - struct isa_ext_data isa_edata_arr[] =3D { - ISA_EDATA_ENTRY(zicsr, ext_icsr), - ISA_EDATA_ENTRY(zifencei, ext_ifencei), - ISA_EDATA_ENTRY(zmmul, ext_zmmul), - ISA_EDATA_ENTRY(zfh, ext_zfh), - ISA_EDATA_ENTRY(zfhmin, ext_zfhmin), - ISA_EDATA_ENTRY(zfinx, ext_zfinx), - ISA_EDATA_ENTRY(zdinx, ext_zdinx), - ISA_EDATA_ENTRY(zba, ext_zba), - ISA_EDATA_ENTRY(zbb, ext_zbb), - ISA_EDATA_ENTRY(zbc, ext_zbc), - ISA_EDATA_ENTRY(zbkb, ext_zbkb), - ISA_EDATA_ENTRY(zbkc, ext_zbkc), - ISA_EDATA_ENTRY(zbkx, ext_zbkx), - ISA_EDATA_ENTRY(zbs, ext_zbs), - ISA_EDATA_ENTRY(zk, ext_zk), - ISA_EDATA_ENTRY(zkn, ext_zkn), - ISA_EDATA_ENTRY(zknd, ext_zknd), - ISA_EDATA_ENTRY(zkne, ext_zkne), - ISA_EDATA_ENTRY(zknh, ext_zknh), - ISA_EDATA_ENTRY(zkr, ext_zkr), - ISA_EDATA_ENTRY(zks, ext_zks), - ISA_EDATA_ENTRY(zksed, ext_zksed), - ISA_EDATA_ENTRY(zksh, ext_zksh), - ISA_EDATA_ENTRY(zkt, ext_zkt), - ISA_EDATA_ENTRY(zve32f, ext_zve32f), - ISA_EDATA_ENTRY(zve64f, ext_zve64f), - ISA_EDATA_ENTRY(zhinx, ext_zhinx), - ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin), - ISA_EDATA_ENTRY(svinval, ext_svinval), - ISA_EDATA_ENTRY(svnapot, ext_svnapot), - ISA_EDATA_ENTRY(svpbmt, ext_svpbmt), - }; - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_edata_arr[i].enabled) { + if (isa_edata_arr[i].multi_letter && + isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { new =3D g_strconcat(old, "_", isa_edata_arr[i].name, NULL); g_free(old); old =3D new; --=20 2.34.1