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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bp11-20020a5d5a8b000000b0020c5253d926sm14276053wrb.114.2022.06.10.09.08.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jun 2022 09:08:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jGmiRIM8sBqhYKDszmqKuZEm8XU+zLyNsnQMu6jqnPs=; b=nI6/4LpFo9PElCjcf3klAgDE7gvQAMEzueqvJ6apFClQjrkAgncLxFWA8nuGSTTEoA 9cafNiYv/y/SbGl6SeSfSq1HKgjtdhp490haXV8AseqH/Kp0qp4BkskXeazs8WZbW3Hc mWg8COYkaE5/tN8mSj2v00svGFnTUDBGNzj7v6K7CEin772INXkkjWm9iEjmQMjOYDob dt2etacNemtxC/RfFgVLpOkeEMT8O3KPYx4wwmG6B6CdE0IkRUueYzl8+Jxchw76BwGm uxrpHi9+/YdOUbJWk/179hlpzV+fTQWNJ+79IcQ5wWltg4wcrEyWFe9xqS5Z0BYC4CKJ qgLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jGmiRIM8sBqhYKDszmqKuZEm8XU+zLyNsnQMu6jqnPs=; b=gYlqR5a56I92+XMOsXaa2DRlGlk/OmhW/l/mIrWqJlEUYN4w2w8CExCbYhKtvokQZH nzx2nYW4WuAKkW37gub6Mw9FARuKPGl8jmdXFLPd/jbIfuADGyDk7k2MJIld0MiMej2I phyLALtnK57rjC8XbT4LKIGluREDUxH49kQOBDiqXRltXX6cT7ylJ+wkkGhSjhiIWpff Nr+6IRCQ44yf59pViZnW0r5153wYOwEndAvM+nNk/k1Bhw/2HTFgut4DiXXkJRHzhHgp 52TOS9e5ccPE3KnnxBeHQbUYCOkA7vCJVcHwKkLzb6zLj9vx+W/+S9qqseLgOoncqAlI WoPw== X-Gm-Message-State: AOAM5338CnJsNI0ZoV7KDr+MzuoEcL0y8RtyVYmWxzupj0hj1DcShXeS RiTtlJKP2cVq2+uZqjSJFj+X5jR9Ynu32Q== X-Google-Smtp-Source: ABdhPJxL6Pbx2ClP/KSG9iAEUufVG+CozedWfdnAI7huvwUtBILDHxI+AZPYkIvfzgaL5o2O3Qhffw== X-Received: by 2002:a05:600c:128c:b0:39c:4c58:f37a with SMTP id t12-20020a05600c128c00b0039c4c58f37amr469824wmd.7.1654877282255; Fri, 10 Jun 2022 09:08:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/28] target/arm: Adjust format test in scr_write Date: Fri, 10 Jun 2022 17:07:35 +0100 Message-Id: <20220610160738.2230762-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220610160738.2230762-1-peter.maydell@linaro.org> References: <20220610160738.2230762-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654879478728100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Because reset always initializes the AA64 version, SCR_EL3, test the mode of EL3 instead of the type of the cpreg. Signed-off-by: Richard Henderson Message-id: 20220609214657.1217913-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b95aa534741..ff9f9fe6ee4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1738,12 +1738,14 @@ static void scr_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) uint32_t valid_mask =3D 0x3fff; ARMCPU *cpu =3D env_archcpu(env); =20 - if (ri->state =3D=3D ARM_CP_STATE_AA64) { - if (arm_feature(env, ARM_FEATURE_AARCH64) && - !cpu_isar_feature(aa64_aa32_el1, cpu)) { - value |=3D SCR_FW | SCR_AW; /* these two bits are RES1. = */ - } - valid_mask &=3D ~SCR_NET; + /* + * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset alw= ays + * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64. + * Instead, choose the format based on the mode of EL3. + */ + if (arm_el_is_aa64(env, 3)) { + value |=3D SCR_FW | SCR_AW; /* RES1 */ + valid_mask &=3D ~SCR_NET; /* RES0 */ =20 if (cpu_isar_feature(aa64_ras, cpu)) { valid_mask |=3D SCR_TERR; --=20 2.25.1