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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Jonathan Cameron , Ben Widawsky , Ben Widawsky Subject: [PULL 45/54] hw/cxl: Fix missing write mask for HDM decoder target list registers Message-ID: <20220610075631.367501-46-mst@redhat.com> References: <20220610075631.367501-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220610075631.367501-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1654854386072100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jonathan Cameron Without being able to write these registers, no interleaving is possible. More refined checks of HDM register state on commit to follow. Signed-off-by: Jonathan Cameron Reviewed-by: Ben Widawsky Message-Id: <20220608130804.25795-1-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/cxl/cxl-component-utils.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index 7985c9bfca..3edd303a33 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -154,7 +154,8 @@ static void ras_init_common(uint32_t *reg_state, uint32= _t *write_msk) reg_state[R_CXL_RAS_ERR_CAP_CTRL] =3D 0x00; } =20 -static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk) +static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, + enum reg_type type) { int decoder_count =3D 1; int i; @@ -174,6 +175,14 @@ static void hdm_init_common(uint32_t *reg_state, uint3= 2_t *write_msk) write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] =3D 0xf0000000; write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] =3D 0xffffffff; write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] =3D 0x13ff; + if (type =3D=3D CXL2_DEVICE || + type =3D=3D CXL2_TYPE3_DEVICE || + type =3D=3D CXL2_LOGICAL_DEVICE) { + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] =3D 0x= f0000000; + } else { + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] =3D 0x= ffffffff; + } + write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] =3D 0xffff= ffff; } } =20 @@ -239,7 +248,7 @@ void cxl_component_register_init_common(uint32_t *reg_s= tate, uint32_t *write_msk } =20 init_cap_reg(HDM, 5, 1); - hdm_init_common(reg_state, write_msk); + hdm_init_common(reg_state, write_msk, type); =20 if (caps < 5) { return; --=20 MST