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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1654835307; x=1657427308; bh=4KxUHtujHhzszJ2LfE PZIVRhMFu+gs8du6hXV7lE2ws=; b=DJxpQdp/KK/sUa7IrLY61LScp3YEUQ4Qc1 4FMGWVwOScmPYHYt0EjEklonhtrbtaiEFxaNEv2b9oCvPjx06T773vurWERRMF/Z K+K981AZx47qM/QTBjnkp2CJnpJc0ly4pDN9R4apu0V+3xw9K9ysgcUF88fH5Cus h0RK3A1n8Yo2NvwIVaoV1Vd8/10aPaYJcsbUylSYSI6LYwKigCFnJkTDw5tntmwf 7vw4k7eWbP5lBkaY4kdjvJ20op/fokCCt04KMFvWhf9eT+UXsqtir6wbrRMoNJIb wwjZ4mEIJcVeLi2ATOMDSqDIRdZYxC2wiiqAf82J2U/tRGODe1rg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, eopXD , eop Chen , Frank Chang , Weiwei Li , Alistair Francis Subject: [PULL 17/25] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions Date: Fri, 10 Jun 2022 14:26:47 +1000 Message-Id: <20220610042655.2021686-18-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220610042655.2021686-1-alistair.francis@opensource.wdc.com> References: <20220610042655.2021686-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=1538de18e=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1654836105515100003 Content-Type: text/plain; charset="utf-8" From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis Message-Id: <165449614532.19704.7000832880482980398-10@git.sr.ht> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 20 ++++++++++++++++++++ target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++++---- 2 files changed, 28 insertions(+), 4 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a64506bf02..128238786e 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1969,6 +1969,9 @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState = *env, \ uint32_t desc) \ { \ uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ @@ -1976,6 +1979,8 @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState = *env, \ *((ETYPE *)vd + H(i)) =3D s1; \ } \ env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t, H1) @@ -1988,12 +1993,17 @@ void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVSt= ate *env, \ uint32_t desc) \ { \ uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ *((ETYPE *)vd + H(i)) =3D (ETYPE)s1; \ } \ env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t, H1) @@ -2006,6 +2016,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ @@ -2013,6 +2026,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ *((ETYPE *)vd + H(i)) =3D *(vt + H(i)); \ } \ env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t, H1) @@ -2025,6 +2040,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ @@ -2034,6 +2052,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ *((ETYPE *)vd + H(i)) =3D d; \ } \ env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index dbe687fb73..e75a2fd196 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2086,12 +2086,13 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_= v_v *a) vext_check_isa_ill(s) && /* vmv.v.v has rs2 =3D 0 and vm =3D 1 */ vext_check_sss(s, a->rd, a->rs1, 0, 1)) { - if (s->vl_eq_vlmax) { + if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), MAXSZ(s), MAXSZ(s)); } else { uint32_t data =3D FIELD_DP32(0, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); static gen_helper_gvec_2_ptr * const fns[4] =3D { gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h, gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d, @@ -2126,7 +2127,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) =20 s1 =3D get_gpr(s, a->rs1, EXT_SIGN); =20 - if (s->vl_eq_vlmax) { + if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), s1); } else { @@ -2134,6 +2135,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) TCGv_i64 s1_i64 =3D tcg_temp_new_i64(); TCGv_ptr dest =3D tcg_temp_new_ptr(); uint32_t data =3D FIELD_DP32(0, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); static gen_helper_vmv_vx * const fns[4] =3D { gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h, gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, @@ -2163,7 +2165,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) /* vmv.v.i has rs2 =3D 0 and vm =3D 1 */ vext_check_ss(s, a->rd, 0, 1)) { int64_t simm =3D sextract64(a->rs1, 0, 5); - if (s->vl_eq_vlmax) { + if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), simm); mark_vs_dirty(s); @@ -2172,6 +2174,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) TCGv_i64 s1; TCGv_ptr dest; uint32_t data =3D FIELD_DP32(0, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); static gen_helper_vmv_vx * const fns[4] =3D { gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h, gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, @@ -2743,7 +2746,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) =20 TCGv_i64 t1; =20 - if (s->vl_eq_vlmax) { + if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { t1 =3D tcg_temp_new_i64(); /* NaN-box f[rs1] */ do_nanbox(s, t1, cpu_fpr[a->rs1]); @@ -2755,6 +2758,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) TCGv_ptr dest; TCGv_i32 desc; uint32_t data =3D FIELD_DP32(0, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); static gen_helper_vmv_vx * const fns[3] =3D { gen_helper_vmv_v_x_h, gen_helper_vmv_v_x_w, --=20 2.36.1