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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 37/55] linux-user/aarch64: Introduce sve_vq
Date: Thu, 9 Jun 2022 10:05:19 +0100
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From: Richard Henderson <richard.henderson@linaro.org>
Add an interface function to extract the digested vector length
rather than the raw zcr_el[1] value. This fixes an incorrect
return from do_prctl_set_vl where we didn't take into account
the set of vector lengths supported by the cpu.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
linux-user/aarch64/target_prctl.h | 20 +++++++++++++-------
target/arm/cpu.h | 11 +++++++++++
linux-user/aarch64/signal.c | 4 ++--
3 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_=
prctl.h
index 3f5a5d3933a..1d440ffbea4 100644
--- a/linux-user/aarch64/target_prctl.h
+++ b/linux-user/aarch64/target_prctl.h
@@ -10,7 +10,7 @@ static abi_long do_prctl_get_vl(CPUArchState *env)
{
ARMCPU *cpu =3D env_archcpu(env);
if (cpu_isar_feature(aa64_sve, cpu)) {
- return ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16;
+ return sve_vq(env) * 16;
}
return -TARGET_EINVAL;
}
@@ -25,18 +25,24 @@ static abi_long do_prctl_set_vl(CPUArchState *env, abi_=
long arg2)
*/
if (cpu_isar_feature(aa64_sve, env_archcpu(env))
&& arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) {
- ARMCPU *cpu =3D env_archcpu(env);
uint32_t vq, old_vq;
=20
- old_vq =3D (env->vfp.zcr_el[1] & 0xf) + 1;
- vq =3D MAX(arg2 / 16, 1);
- vq =3D MIN(vq, cpu->sve_max_vq);
+ old_vq =3D sve_vq(env);
=20
+ /*
+ * Bound the value of arg2, so that we know that it fits into
+ * the 4-bit field in ZCR_EL1. Rely on the hflags rebuild to
+ * sort out the length supported by the cpu.
+ */
+ vq =3D MAX(arg2 / 16, 1);
+ vq =3D MIN(vq, ARM_MAX_VQ);
+ env->vfp.zcr_el[1] =3D vq - 1;
+ arm_rebuild_hflags(env);
+
+ vq =3D sve_vq(env);
if (vq < old_vq) {
aarch64_sve_narrow_vq(env, vq);
}
- env->vfp.zcr_el[1] =3D vq - 1;
- arm_rebuild_hflags(env);
return vq * 16;
}
return -TARGET_EINVAL;
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index e791ffdd6b6..f5af88b686d 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3286,6 +3286,17 @@ static inline int cpu_mmu_index(CPUARMState *env, bo=
ol ifetch)
return EX_TBFLAG_ANY(env->hflags, MMUIDX);
}
=20
+/**
+ * sve_vq
+ * @env: the cpu context
+ *
+ * Return the VL cached within env->hflags, in units of quadwords.
+ */
+static inline int sve_vq(CPUARMState *env)
+{
+ return EX_TBFLAG_A64(env->hflags, VL) + 1;
+}
+
static inline bool bswap_code(bool sctlr_b)
{
#ifdef CONFIG_USER_ONLY
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index 7de4c96eb9d..7da0e36c6d4 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -315,7 +315,7 @@ static int target_restore_sigframe(CPUARMState *env,
=20
case TARGET_SVE_MAGIC:
if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
- vq =3D (env->vfp.zcr_el[1] & 0xf) + 1;
+ vq =3D sve_vq(env);
sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq)=
, 16);
if (!sve && size =3D=3D sve_size) {
sve =3D (struct target_sve_context *)ctx;
@@ -434,7 +434,7 @@ static void target_setup_frame(int usig, struct target_=
sigaction *ka,
=20
/* SVE state needs saving only if it exists. */
if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
- vq =3D (env->vfp.zcr_el[1] & 0xf) + 1;
+ vq =3D sve_vq(env);
sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
sve_ofs =3D alloc_sigframe_space(sve_size, &layout);
}
--=20
2.25.1