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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id c13-20020adffb0d000000b002183cf9cd69sm11349796wrr.15.2022.06.09.02.06.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:06:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vIokLa9eFuxFiVW77KIrOZU1hdMYpdkzIffZFBXlcuc=; b=CQqjOu4DBavLPFvIx3KuaWUMdGxL+Q8upq+K2k83UjjqO8avt4fANTtmgyGvENzIlq bG0OrlgLufrp6AgPdkr3t7qpHgZT3zuQ0D439n6RukPJIZ5SNUbNuii8qTdWPz4QrjOc AVyfC+7kAnk1V2x0ArAjV/RvAQPp5LZDf7QDUl5OU0xmxWSu8YuI5eQ7vQPoLJSchP90 6T7Y0mBlOzlufl6Zmeo9GhOjGs7ZMvTSMn38YuuxleiRWjt4KOzE7Jq5mHjsB9mtMCQl VCtBi165GQz4C2P5vrROmlxyzPwcVyWR7OCnoRXhzMeWWd9DlAvr8x0e35IlhqfvVckp W2jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654769090272100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-19-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 2 -- target/arm/helper.c | 25 ------------------------- target/arm/ptw.c | 25 +++++++++++++++++++++++++ 3 files changed, 25 insertions(+), 27 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index 28b8cb9fb89..fba650d01ca 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -11,8 +11,6 @@ =20 #ifndef CONFIG_USER_ONLY =20 -extern const uint8_t pamax_map[7]; - bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx); bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx); uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn); diff --git a/target/arm/helper.c b/target/arm/helper.c index d2b196ff3e5..563e34ecded 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10814,31 +10814,6 @@ bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64,= int level, } #endif /* !CONFIG_USER_ONLY */ =20 -/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. = */ -const uint8_t pamax_map[] =3D { - [0] =3D 32, - [1] =3D 36, - [2] =3D 40, - [3] =3D 42, - [4] =3D 44, - [5] =3D 48, - [6] =3D 52, -}; - -/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ -unsigned int arm_pamax(ARMCPU *cpu) -{ - unsigned int parange =3D - FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); - - /* - * id_aa64mmfr0 is a read-only register so values outside of the - * supported mappings can be considered an implementation error. - */ - assert(parange < ARRAY_SIZE(pamax_map)); - return pamax_map[parange]; -} - int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) { if (regime_has_2_ranges(mmu_idx)) { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e4b860d2aee..d754273fa16 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -23,6 +23,31 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_= t address, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs) __attribute__((nonnull)); =20 +/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. = */ +static const uint8_t pamax_map[] =3D { + [0] =3D 32, + [1] =3D 36, + [2] =3D 40, + [3] =3D 42, + [4] =3D 44, + [5] =3D 48, + [6] =3D 52, +}; + +/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ +unsigned int arm_pamax(ARMCPU *cpu) +{ + unsigned int parange =3D + FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); + + /* + * id_aa64mmfr0 is a read-only register so values outside of the + * supported mappings can be considered an implementation error. + */ + assert(parange < ARRAY_SIZE(pamax_map)); + return pamax_map[parange]; +} + static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_= idx) { return (regime_sctlr(env, mmu_idx) & SCTLR_EE) !=3D 0; --=20 2.25.1