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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654767089931100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 4 --- target/arm/helper.c | 85 --------------------------------------------- target/arm/ptw.c | 85 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+), 89 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index 349b842d3ce..324a9dde140 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -33,10 +33,6 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx= , int ap) return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); } =20 -bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - ARMMMUFaultInfo *fi); bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, diff --git a/target/arm/helper.c b/target/arm/helper.c index 4a588220250..5d010190108 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12274,91 +12274,6 @@ bool get_phys_addr_pmsav8(CPUARMState *env, uint32= _t address, return ret; } =20 -bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - ARMMMUFaultInfo *fi) -{ - int n; - uint32_t mask; - uint32_t base; - bool is_user =3D regime_is_user(env, mmu_idx); - - if (regime_translation_disabled(env, mmu_idx)) { - /* MPU disabled. */ - *phys_ptr =3D address; - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return false; - } - - *phys_ptr =3D address; - for (n =3D 7; n >=3D 0; n--) { - base =3D env->cp15.c6_region[n]; - if ((base & 1) =3D=3D 0) { - continue; - } - mask =3D 1 << ((base >> 1) & 0x1f); - /* Keep this shift separate from the above to avoid an - (undefined) << 32. */ - mask =3D (mask << 1) - 1; - if (((base ^ address) & ~mask) =3D=3D 0) { - break; - } - } - if (n < 0) { - fi->type =3D ARMFault_Background; - return true; - } - - if (access_type =3D=3D MMU_INST_FETCH) { - mask =3D env->cp15.pmsav5_insn_ap; - } else { - mask =3D env->cp15.pmsav5_data_ap; - } - mask =3D (mask >> (n * 4)) & 0xf; - switch (mask) { - case 0: - fi->type =3D ARMFault_Permission; - fi->level =3D 1; - return true; - case 1: - if (is_user) { - fi->type =3D ARMFault_Permission; - fi->level =3D 1; - return true; - } - *prot =3D PAGE_READ | PAGE_WRITE; - break; - case 2: - *prot =3D PAGE_READ; - if (!is_user) { - *prot |=3D PAGE_WRITE; - } - break; - case 3: - *prot =3D PAGE_READ | PAGE_WRITE; - break; - case 5: - if (is_user) { - fi->type =3D ARMFault_Permission; - fi->level =3D 1; - return true; - } - *prot =3D PAGE_READ; - break; - case 6: - *prot =3D PAGE_READ; - break; - default: - /* Bad permission. */ - fi->type =3D ARMFault_Permission; - fi->level =3D 1; - return true; - } - *prot |=3D PAGE_EXEC; - return false; -} - /* Combine either inner or outer cacheability attributes for normal * memory, according to table D4-42 and pseudocode procedure * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6a1f4b549d8..5c32648a16a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -289,6 +289,91 @@ do_fault: return true; } =20 +static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_= idx, + hwaddr *phys_ptr, int *prot, + ARMMMUFaultInfo *fi) +{ + int n; + uint32_t mask; + uint32_t base; + bool is_user =3D regime_is_user(env, mmu_idx); + + if (regime_translation_disabled(env, mmu_idx)) { + /* MPU disabled. */ + *phys_ptr =3D address; + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return false; + } + + *phys_ptr =3D address; + for (n =3D 7; n >=3D 0; n--) { + base =3D env->cp15.c6_region[n]; + if ((base & 1) =3D=3D 0) { + continue; + } + mask =3D 1 << ((base >> 1) & 0x1f); + /* Keep this shift separate from the above to avoid an + (undefined) << 32. */ + mask =3D (mask << 1) - 1; + if (((base ^ address) & ~mask) =3D=3D 0) { + break; + } + } + if (n < 0) { + fi->type =3D ARMFault_Background; + return true; + } + + if (access_type =3D=3D MMU_INST_FETCH) { + mask =3D env->cp15.pmsav5_insn_ap; + } else { + mask =3D env->cp15.pmsav5_data_ap; + } + mask =3D (mask >> (n * 4)) & 0xf; + switch (mask) { + case 0: + fi->type =3D ARMFault_Permission; + fi->level =3D 1; + return true; + case 1: + if (is_user) { + fi->type =3D ARMFault_Permission; + fi->level =3D 1; + return true; + } + *prot =3D PAGE_READ | PAGE_WRITE; + break; + case 2: + *prot =3D PAGE_READ; + if (!is_user) { + *prot |=3D PAGE_WRITE; + } + break; + case 3: + *prot =3D PAGE_READ | PAGE_WRITE; + break; + case 5: + if (is_user) { + fi->type =3D ARMFault_Permission; + fi->level =3D 1; + return true; + } + *prot =3D PAGE_READ; + break; + case 6: + *prot =3D PAGE_READ; + break; + default: + /* Bad permission. */ + fi->type =3D ARMFault_Permission; + fi->level =3D 1; + return true; + } + *prot |=3D PAGE_EXEC; + return false; +} + /** * get_phys_addr - get the physical address for this virtual address * --=20 2.25.1