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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654766652449100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20220604040607.269301-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.h | 11 +-- target/arm/helper.c | 161 +------------------------------------------- target/arm/ptw.c | 153 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 161 insertions(+), 164 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index 2dbd97b8cbf..349b842d3ce 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -25,15 +25,18 @@ bool get_level1_table_address(CPUARMState *env, ARMMMUI= dx mmu_idx, uint32_t *table, uint32_t address); int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap, int domain_prot); +int simple_ap_to_rw_prot_is_user(int ap, bool is_user); + +static inline int +simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) +{ + return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); +} =20 bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, ARMMMUFaultInfo *fi); -bool get_phys_addr_v6(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, ARMMMUFaultInfo *fi); bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, diff --git a/target/arm/helper.c b/target/arm/helper.c index 321716914b1..4a588220250 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10631,7 +10631,7 @@ int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_i= dx, int ap, int domain_prot) * @ap: The 2-bit simple AP (AP[2:1]) * @is_user: TRUE if accessing from PL0 */ -static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) +int simple_ap_to_rw_prot_is_user(int ap, bool is_user) { switch (ap) { case 0: @@ -10647,12 +10647,6 @@ static inline int simple_ap_to_rw_prot_is_user(int= ap, bool is_user) } } =20 -static inline int -simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) -{ - return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); -} - /* Translate S2 section/page access permissions to protection flags * * @env: CPUARMState @@ -10939,159 +10933,6 @@ uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, b= ool is_secure, return 0; } =20 -bool get_phys_addr_v6(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, ARMMMUFaultInfo *fi) -{ - CPUState *cs =3D env_cpu(env); - ARMCPU *cpu =3D env_archcpu(env); - int level =3D 1; - uint32_t table; - uint32_t desc; - uint32_t xn; - uint32_t pxn =3D 0; - int type; - int ap; - int domain =3D 0; - int domain_prot; - hwaddr phys_addr; - uint32_t dacr; - bool ns; - - /* Pagetable walk. */ - /* Lookup l1 descriptor. */ - if (!get_level1_table_address(env, mmu_idx, &table, address)) { - /* Section translation fault if page walk is disabled by PD0 or PD= 1 */ - fi->type =3D ARMFault_Translation; - goto do_fault; - } - desc =3D arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); - if (fi->type !=3D ARMFault_None) { - goto do_fault; - } - type =3D (desc & 3); - if (type =3D=3D 0 || (type =3D=3D 3 && !cpu_isar_feature(aa32_pxn, cpu= ))) { - /* Section translation fault, or attempt to use the encoding - * which is Reserved on implementations without PXN. - */ - fi->type =3D ARMFault_Translation; - goto do_fault; - } - if ((type =3D=3D 1) || !(desc & (1 << 18))) { - /* Page or Section. */ - domain =3D (desc >> 5) & 0x0f; - } - if (regime_el(env, mmu_idx) =3D=3D 1) { - dacr =3D env->cp15.dacr_ns; - } else { - dacr =3D env->cp15.dacr_s; - } - if (type =3D=3D 1) { - level =3D 2; - } - domain_prot =3D (dacr >> (domain * 2)) & 3; - if (domain_prot =3D=3D 0 || domain_prot =3D=3D 2) { - /* Section or Page domain fault */ - fi->type =3D ARMFault_Domain; - goto do_fault; - } - if (type !=3D 1) { - if (desc & (1 << 18)) { - /* Supersection. */ - phys_addr =3D (desc & 0xff000000) | (address & 0x00ffffff); - phys_addr |=3D (uint64_t)extract32(desc, 20, 4) << 32; - phys_addr |=3D (uint64_t)extract32(desc, 5, 4) << 36; - *page_size =3D 0x1000000; - } else { - /* Section. */ - phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); - *page_size =3D 0x100000; - } - ap =3D ((desc >> 10) & 3) | ((desc >> 13) & 4); - xn =3D desc & (1 << 4); - pxn =3D desc & 1; - ns =3D extract32(desc, 19, 1); - } else { - if (cpu_isar_feature(aa32_pxn, cpu)) { - pxn =3D (desc >> 2) & 1; - } - ns =3D extract32(desc, 3, 1); - /* Lookup l2 entry. */ - table =3D (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - desc =3D arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); - if (fi->type !=3D ARMFault_None) { - goto do_fault; - } - ap =3D ((desc >> 4) & 3) | ((desc >> 7) & 4); - switch (desc & 3) { - case 0: /* Page translation fault. */ - fi->type =3D ARMFault_Translation; - goto do_fault; - case 1: /* 64k page. */ - phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); - xn =3D desc & (1 << 15); - *page_size =3D 0x10000; - break; - case 2: case 3: /* 4k page. */ - phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); - xn =3D desc & 1; - *page_size =3D 0x1000; - break; - default: - /* Never happens, but compiler isn't smart enough to tell. */ - g_assert_not_reached(); - } - } - if (domain_prot =3D=3D 3) { - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - } else { - if (pxn && !regime_is_user(env, mmu_idx)) { - xn =3D 1; - } - if (xn && access_type =3D=3D MMU_INST_FETCH) { - fi->type =3D ARMFault_Permission; - goto do_fault; - } - - if (arm_feature(env, ARM_FEATURE_V6K) && - (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { - /* The simplified model uses AP[0] as an access control bit. = */ - if ((ap & 1) =3D=3D 0) { - /* Access flag fault. */ - fi->type =3D ARMFault_AccessFlag; - goto do_fault; - } - *prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); - } else { - *prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); - } - if (*prot && !xn) { - *prot |=3D PAGE_EXEC; - } - if (!(*prot & (1 << access_type))) { - /* Access permission fault. */ - fi->type =3D ARMFault_Permission; - goto do_fault; - } - } - if (ns) { - /* The NS bit will (as required by the architecture) have no effec= t if - * the CPU doesn't support TZ or this is a non-secure translation - * regime, because the attribute will already be non-secure. - */ - attrs->secure =3D false; - } - *phys_ptr =3D phys_addr; - return false; -do_fault: - fi->domain =3D domain; - fi->level =3D level; - return true; -} - /* * check_s2_mmu_setup * @cpu: ARMCPU diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 09c44726287..6a1f4b549d8 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -136,6 +136,159 @@ do_fault: return true; } =20 +static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *pro= t, + target_ulong *page_size, ARMMMUFaultInfo *fi) +{ + CPUState *cs =3D env_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); + int level =3D 1; + uint32_t table; + uint32_t desc; + uint32_t xn; + uint32_t pxn =3D 0; + int type; + int ap; + int domain =3D 0; + int domain_prot; + hwaddr phys_addr; + uint32_t dacr; + bool ns; + + /* Pagetable walk. */ + /* Lookup l1 descriptor. */ + if (!get_level1_table_address(env, mmu_idx, &table, address)) { + /* Section translation fault if page walk is disabled by PD0 or PD= 1 */ + fi->type =3D ARMFault_Translation; + goto do_fault; + } + desc =3D arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + mmu_idx, fi); + if (fi->type !=3D ARMFault_None) { + goto do_fault; + } + type =3D (desc & 3); + if (type =3D=3D 0 || (type =3D=3D 3 && !cpu_isar_feature(aa32_pxn, cpu= ))) { + /* Section translation fault, or attempt to use the encoding + * which is Reserved on implementations without PXN. + */ + fi->type =3D ARMFault_Translation; + goto do_fault; + } + if ((type =3D=3D 1) || !(desc & (1 << 18))) { + /* Page or Section. */ + domain =3D (desc >> 5) & 0x0f; + } + if (regime_el(env, mmu_idx) =3D=3D 1) { + dacr =3D env->cp15.dacr_ns; + } else { + dacr =3D env->cp15.dacr_s; + } + if (type =3D=3D 1) { + level =3D 2; + } + domain_prot =3D (dacr >> (domain * 2)) & 3; + if (domain_prot =3D=3D 0 || domain_prot =3D=3D 2) { + /* Section or Page domain fault */ + fi->type =3D ARMFault_Domain; + goto do_fault; + } + if (type !=3D 1) { + if (desc & (1 << 18)) { + /* Supersection. */ + phys_addr =3D (desc & 0xff000000) | (address & 0x00ffffff); + phys_addr |=3D (uint64_t)extract32(desc, 20, 4) << 32; + phys_addr |=3D (uint64_t)extract32(desc, 5, 4) << 36; + *page_size =3D 0x1000000; + } else { + /* Section. */ + phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); + *page_size =3D 0x100000; + } + ap =3D ((desc >> 10) & 3) | ((desc >> 13) & 4); + xn =3D desc & (1 << 4); + pxn =3D desc & 1; + ns =3D extract32(desc, 19, 1); + } else { + if (cpu_isar_feature(aa32_pxn, cpu)) { + pxn =3D (desc >> 2) & 1; + } + ns =3D extract32(desc, 3, 1); + /* Lookup l2 entry. */ + table =3D (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); + desc =3D arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + mmu_idx, fi); + if (fi->type !=3D ARMFault_None) { + goto do_fault; + } + ap =3D ((desc >> 4) & 3) | ((desc >> 7) & 4); + switch (desc & 3) { + case 0: /* Page translation fault. */ + fi->type =3D ARMFault_Translation; + goto do_fault; + case 1: /* 64k page. */ + phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); + xn =3D desc & (1 << 15); + *page_size =3D 0x10000; + break; + case 2: case 3: /* 4k page. */ + phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); + xn =3D desc & 1; + *page_size =3D 0x1000; + break; + default: + /* Never happens, but compiler isn't smart enough to tell. */ + g_assert_not_reached(); + } + } + if (domain_prot =3D=3D 3) { + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + } else { + if (pxn && !regime_is_user(env, mmu_idx)) { + xn =3D 1; + } + if (xn && access_type =3D=3D MMU_INST_FETCH) { + fi->type =3D ARMFault_Permission; + goto do_fault; + } + + if (arm_feature(env, ARM_FEATURE_V6K) && + (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { + /* The simplified model uses AP[0] as an access control bit. = */ + if ((ap & 1) =3D=3D 0) { + /* Access flag fault. */ + fi->type =3D ARMFault_AccessFlag; + goto do_fault; + } + *prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); + } else { + *prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + } + if (*prot && !xn) { + *prot |=3D PAGE_EXEC; + } + if (!(*prot & (1 << access_type))) { + /* Access permission fault. */ + fi->type =3D ARMFault_Permission; + goto do_fault; + } + } + if (ns) { + /* The NS bit will (as required by the architecture) have no effec= t if + * the CPU doesn't support TZ or this is a non-secure translation + * regime, because the attribute will already be non-secure. + */ + attrs->secure =3D false; + } + *phys_ptr =3D phys_addr; + return false; +do_fault: + fi->domain =3D domain; + fi->level =3D level; + return true; +} + /** * get_phys_addr - get the physical address for this virtual address * --=20 2.25.1