From nobody Mon Feb 9 08:56:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1654700330; cv=none; d=zohomail.com; s=zohoarc; b=ARyOmP0vkYKWphnMCh0ANn3z5g4HpMjhfFKgMg5spfR0KUvDbWcjyvK8WeMltv4iLQnhsaKwgMYhbC02Ny3SmplZmSz2piE3A2aDmESUW61bCV8Q/yze7esJvRSgpBCdDaKrLfSUz0JAwAN0LOFjkqHF9m5W78h4a8UIObO0sOA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654700330; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=7XI4BK6j+x700R6pc1KLFtd+vcBT6/mEj1nyL06qslw=; b=hxPU5vz/sV0W2pzMFslcDQYSRMhs1CkRXe+88HguG0tLtUpRViMffTaY2X72kWA7UQE1mXZBZ0SwksM5p3SvKt2ZhPD7jhdZTRPvuNju5v8TFBoif5pEJdTocpxYKji5FdpTQrParWzzgNjt3XIiEMbjpYa16NX04Cwg+1M03Yk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654700330848245.97480255863059; Wed, 8 Jun 2022 07:58:50 -0700 (PDT) Received: from localhost ([::1]:33408 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyx8y-0002YZ-LF for importer@patchew.org; Wed, 08 Jun 2022 10:58:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35396) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyx5X-0008Hk-Bk for qemu-devel@nongnu.org; Wed, 08 Jun 2022 10:55:15 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]:2611) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyx5Q-0006Im-5Q for qemu-devel@nongnu.org; Wed, 08 Jun 2022 10:55:15 -0400 Received: from fraeml743-chm.china.huawei.com (unknown [172.18.147.207]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4LJ9BL5KKnz67x9D; Wed, 8 Jun 2022 22:50:18 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml743-chm.china.huawei.com (10.206.15.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Wed, 8 Jun 2022 16:55:04 +0200 Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2375.24; Wed, 8 Jun 2022 15:55:03 +0100 To: Paolo Bonzini , , "Michael S . Tsirkin" , Ben Widawsky CC: , , , Marcel Apfelbaum , Igor Mammedov , Markus Armbruster , "Mark Cave-Ayland" , Adam Manzanares , Tong Zhang , "Shameerali Kolothum Thodi" Subject: [PATCH v3 1/8] hw/cxl: Make the CXL fixed memory window setup a machine parameter. Date: Wed, 8 Jun 2022 15:54:33 +0100 Message-ID: <20220608145440.26106-2-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220608145440.26106-1-Jonathan.Cameron@huawei.com> References: <20220608145440.26106-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhreml703-chm.china.huawei.com (10.201.108.52) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Jonathan Cameron From: Jonathan Cameron via X-ZM-MESSAGEID: 1654700333075100001 Content-Type: text/plain; charset="utf-8" Paolo Bonzini requested this change to simplify the ongoing effort to allow machine setup entirely via RPC. Includes shortening the command line form cxl-fixed-memory-window to cxl-fmw as the command lines are extremely long even with this change. The json change is needed to ensure that there is a CXLFixedMemoryWindowOptionsList even though the actual element in the json is never used. Similar to existing SgxEpcProperties. Update qemu-options.hx to reflect that this is now a -machine parameter. The bulk of -M / -machine parameters are documented under machine, so use that in preference to M. Update cxl-test and bios-tables-test to reflect new parameters. Signed-off-by: Jonathan Cameron Reviewed-by: Ben Widawsky Reviewed-by: Davidlohr Bueso --- docs/system/devices/cxl.rst | 4 +- hw/core/machine.c | 22 --------- hw/cxl/cxl-host-stubs.c | 6 +-- hw/cxl/cxl-host.c | 72 ++++++++++++++++++++++++++-- hw/i386/pc.c | 3 ++ hw/pci-bridge/pci_expander_bridge.c | 2 +- include/hw/boards.h | 1 + include/hw/cxl/cxl.h | 7 +-- include/hw/cxl/cxl_host.h | 21 +++++++++ qapi/machine.json | 13 +++++ qemu-options.hx | 73 ++++++++++++++--------------- softmmu/vl.c | 44 ----------------- tests/qtest/bios-tables-test.c | 4 +- tests/qtest/cxl-test.c | 4 +- 14 files changed, 150 insertions(+), 126 deletions(-) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index 9293cbf01a..bcbfe8c490 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -251,7 +251,7 @@ A very simple setup with just one directly attached CXL= Type 3 device:: -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id=3Dcxl.1 \ -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Droot_port13,chassis=3D0,slot=3D= 2 \ -device cxl-type3,bus=3Droot_port13,memdev=3Dcxl-mem1,lsa=3Dcxl-lsa1,id= =3Dcxl-pmem0 \ - -cxl-fixed-memory-window targets.0=3Dcxl.1,size=3D4G + -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G =20 A setup suitable for 4 way interleave. Only one fixed window provided, to = enable 2 way interleave across 2 CXL host bridges. Each host bridge has 2 CXL Root Por= ts, with @@ -277,7 +277,7 @@ the CXL Type3 device directly attached (no switches).:: -device cxl-type3,bus=3Droot_port15,memdev=3Dcxl-mem3,lsa=3Dcxl-lsa3,id= =3Dcxl-pmem2 \ -device cxl-rp,port=3D1,bus=3Dcxl.2,id=3Droot_port16,chassis=3D0,slot=3D= 6 \ -device cxl-type3,bus=3Droot_port16,memdev=3Dcxl-mem4,lsa=3Dcxl-lsa4,id= =3Dcxl-pmem3 \ - -cxl-fixed-memory-window targets.0=3Dcxl.1,targets.1=3Dcxl.2,size=3D4G,i= nterleave-granularity=3D8k + -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.targets.1=3Dcxl.2,cxl-fmw.0.siz= e=3D4G,cxl-fmw.0.interleave-granularity=3D8k =20 Kernel Configuration Options ---------------------------- diff --git a/hw/core/machine.c b/hw/core/machine.c index c53548d0b1..2e589d99e9 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -629,20 +629,6 @@ static void machine_set_nvdimm_persistence(Object *obj= , const char *value, nvdimms_state->persistence_string =3D g_strdup(value); } =20 -static bool machine_get_cxl(Object *obj, Error **errp) -{ - MachineState *ms =3D MACHINE(obj); - - return ms->cxl_devices_state->is_enabled; -} - -static void machine_set_cxl(Object *obj, bool value, Error **errp) -{ - MachineState *ms =3D MACHINE(obj); - - ms->cxl_devices_state->is_enabled =3D value; -} - void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *= type) { QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type)); @@ -929,8 +915,6 @@ static void machine_class_init(ObjectClass *oc, void *d= ata) mc->default_ram_size =3D 128 * MiB; mc->rom_file_has_mr =3D true; =20 - /* Few machines support CXL, so default to off */ - mc->cxl_supported =3D false; /* numa node memory size aligned on 8MB by default. * On Linux, each node's border has to be 8MB aligned */ @@ -1092,13 +1076,7 @@ static void machine_initfn(Object *obj) } =20 if (mc->cxl_supported) { - Object *obj =3D OBJECT(ms); - ms->cxl_devices_state =3D g_new0(CXLState, 1); - object_property_add_bool(obj, "cxl", machine_get_cxl, machine_set_= cxl); - object_property_set_description(obj, "cxl", - "Set on/off to enable/disable " - "CXL instantiation"); } =20 if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { diff --git a/hw/cxl/cxl-host-stubs.c b/hw/cxl/cxl-host-stubs.c index 24465a52ab..de3e8894d5 100644 --- a/hw/cxl/cxl-host-stubs.c +++ b/hw/cxl/cxl-host-stubs.c @@ -6,11 +6,9 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/cxl/cxl.h" - -void cxl_fixed_memory_window_config(MachineState *ms, - CXLFixedMemoryWindowOptions *object, - Error **errp) {}; +#include "hw/cxl/cxl_host.h" =20 void cxl_fixed_memory_window_link_targets(Error **errp) {}; +void cxl_machine_init(Object *obj, CXLState *state) {}; =20 const MemoryRegionOps cfmws_ops; diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c index 469b3c4ced..3a79c32b42 100644 --- a/hw/cxl/cxl-host.c +++ b/hw/cxl/cxl-host.c @@ -15,14 +15,15 @@ =20 #include "qapi/qapi-visit-machine.h" #include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "hw/pci/pci_bus.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_host.h" #include "hw/pci/pcie_port.h" =20 -void cxl_fixed_memory_window_config(MachineState *ms, - CXLFixedMemoryWindowOptions *object, - Error **errp) +static void cxl_fixed_memory_window_config(CXLState *cxl_state, + CXLFixedMemoryWindowOptions *ob= ject, + Error **errp) { CXLFixedWindow *fw =3D g_malloc0(sizeof(*fw)); strList *target; @@ -62,8 +63,7 @@ void cxl_fixed_memory_window_config(MachineState *ms, fw->enc_int_gran =3D 0; } =20 - ms->cxl_devices_state->fixed_windows =3D - g_list_append(ms->cxl_devices_state->fixed_windows, fw); + cxl_state->fixed_windows =3D g_list_append(cxl_state->fixed_windows, f= w); =20 return; } @@ -220,3 +220,65 @@ const MemoryRegionOps cfmws_ops =3D { .unaligned =3D true, }, }; + +static void machine_get_cxl(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + CXLState *cxl_state =3D opaque; + bool value =3D cxl_state->is_enabled; + + visit_type_bool(v, name, &value, errp); +} + +static void machine_set_cxl(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + CXLState *cxl_state =3D opaque; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + cxl_state->is_enabled =3D value; +} + +static void machine_get_cfmw(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + CXLFixedMemoryWindowOptionsList **list =3D opaque; + + visit_type_CXLFixedMemoryWindowOptionsList(v, name, list, errp); +} + +static void machine_set_cfmw(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + CXLState *state =3D opaque; + CXLFixedMemoryWindowOptionsList *cfmw_list =3D NULL; + CXLFixedMemoryWindowOptionsList *it; + + visit_type_CXLFixedMemoryWindowOptionsList(v, name, &cfmw_list, errp); + if (!cfmw_list) { + return; + } + + for (it =3D cfmw_list; it; it =3D it->next) { + cxl_fixed_memory_window_config(state, it->value, errp); + } + state->cfmw_list =3D cfmw_list; +} + +void cxl_machine_init(Object *obj, CXLState *state) +{ + object_property_add(obj, "cxl", "bool", machine_get_cxl, + machine_set_cxl, NULL, state); + object_property_set_description(obj, "cxl", + "Set on/off to enable/disable " + "CXL instantiation"); + + object_property_add(obj, "cxl-fmw", "CXLFixedMemoryWindow", + machine_get_cfmw, machine_set_cfmw, + NULL, state); + object_property_set_description(obj, "cxl-fmw", + "CXL Fixed Memory Windows (array)"); +} diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 7c39c91335..98e63347f2 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -76,6 +76,7 @@ #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" #include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "qapi/error.h" #include "qapi/qapi-visit-common.h" #include "qapi/qapi-visit-machine.h" @@ -1682,6 +1683,7 @@ static void pc_machine_set_max_fw_size(Object *obj, V= isitor *v, static void pc_machine_initfn(Object *obj) { PCMachineState *pcms =3D PC_MACHINE(obj); + MachineState *ms =3D MACHINE(obj); =20 #ifdef CONFIG_VMPORT pcms->vmport =3D ON_OFF_AUTO_AUTO; @@ -1706,6 +1708,7 @@ static void pc_machine_initfn(Object *obj) pcms->pcspk =3D isa_new(TYPE_PC_SPEAKER); object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", OBJECT(pcms->pcspk), "audiodev"); + cxl_machine_init(obj, ms->cxl_devices_state); } =20 static void pc_machine_reset(MachineState *machine) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 69244decdb..02032360f5 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -468,7 +468,7 @@ static void pxb_cxl_dev_realize(PCIDevice *dev, Error *= *errp) error_setg(errp, "pxb-cxl devices cannot reside on a PCI bus"); return; } - if (!ms->cxl_devices_state->is_enabled) { + if (!ms->cxl_devices_state || !ms->cxl_devices_state->is_enabled) { error_setg(errp, "Machine does not have cxl=3Don"); return; } diff --git a/include/hw/boards.h b/include/hw/boards.h index fa57bac4fb..dd9fc56df2 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -362,6 +362,7 @@ struct MachineState { struct NVDIMMState *nvdimms_state; struct CXLState *cxl_devices_state; struct NumaState *numa_state; + CXLFixedMemoryWindowOptionsList *cfmws_list; }; =20 #define DEFINE_MACHINE(namestr, machine_initfn) \ diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h index 21d28ca110..84078a484d 100644 --- a/include/hw/cxl/cxl.h +++ b/include/hw/cxl/cxl.h @@ -12,6 +12,7 @@ =20 =20 #include "qapi/qapi-types-machine.h" +#include "qapi/qapi-visit-machine.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_host.h" #include "cxl_pci.h" @@ -40,6 +41,7 @@ typedef struct CXLState { MemoryRegion host_mr; unsigned int next_mr_idx; GList *fixed_windows; + CXLFixedMemoryWindowOptionsList *cfmw_list; } CXLState; =20 struct CXLHost { @@ -51,11 +53,6 @@ struct CXLHost { #define TYPE_PXB_CXL_HOST "pxb-cxl-host" OBJECT_DECLARE_SIMPLE_TYPE(CXLHost, PXB_CXL_HOST) =20 -void cxl_fixed_memory_window_config(MachineState *ms, - CXLFixedMemoryWindowOptions *object, - Error **errp); void cxl_fixed_memory_window_link_targets(Error **errp); =20 -extern const MemoryRegionOps cfmws_ops; - #endif diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h new file mode 100644 index 0000000000..87a6933de2 --- /dev/null +++ b/include/hw/cxl/cxl_host.h @@ -0,0 +1,21 @@ +/* + * QEMU CXL Host Setup + * + * Copyright (c) 2022 Huawei + * + * This work is licensed under the terms of the GNU GPL, version 2. See the + * COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/cxl/cxl.h" +#include "hw/boards.h" + +#ifndef CXL_HOST_H +#define CXL_HOST_H + +void cxl_machine_init(Object *obj, CXLState *state); + +extern const MemoryRegionOps cfmws_ops; + +#endif diff --git a/qapi/machine.json b/qapi/machine.json index f750a16396..6afd1936b0 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -523,6 +523,19 @@ '*interleave-granularity': 'size', 'targets': ['str'] }} =20 +## +# @CXLFMWProperties: +# +# List of CXL Fixed Memory Windows. +# +# @cxl-fmw: List of CXLFixedMemoryWindowOptions +# +# Since 7.1 +## +{ 'struct' : 'CXLFMWProperties', + 'data': { 'cxl-fmw': ['CXLFixedMemoryWindowOptions'] } +} + ## # @X86CPURegister32: # diff --git a/qemu-options.hx b/qemu-options.hx index 60cf188da4..377d22fbd8 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -36,7 +36,8 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \ " nvdimm=3Don|off controls NVDIMM support (default=3Dof= f)\n" " memory-encryption=3D@var{} memory encryption object t= o use (default=3Dnone)\n" " hmat=3Don|off controls ACPI HMAT support (default=3Do= ff)\n" - " memory-backend=3D'backend-id' specifies explicitly pr= ovided backend for main RAM (default=3Dnone)\n", + " memory-backend=3D'backend-id' specifies explicitly pr= ovided backend for main RAM (default=3Dnone)\n" + " cxl-fmw.0.targets.0=3Dfirsttarget,cxl-fmw.0.targets.1= =3Dsecondtarget,cxl-fmw.0.size=3Dsize[,cxl-fmw.0.interleave-granularity=3Dg= ranularity]\n", QEMU_ARCH_ALL) SRST ``-machine [type=3D]name[,prop=3Dvalue[,...]]`` @@ -124,6 +125,38 @@ SRST -object memory-backend-ram,id=3Dpc.ram,size=3D512M,x-use-canon= ical-path-for-ramblock-id=3Doff -machine memory-backend=3Dpc.ram -m 512M + + ``cxl-fmw.0.targets.0=3Dfirsttarget,cxl-fmw.0.targets.1=3Dsecondtarget= ,cxl-fmw.0.size=3Dsize[,cxl-fmw.0.interleave-granularity=3Dgranularity]`` + Define a CXL Fixed Memory Window (CFMW). + + Described in the CXL 2.0 ECN: CEDT CFMWS & QTG _DSM. + + They are regions of Host Physical Addresses (HPA) on a system which + may be interleaved across one or more CXL host bridges. The system + software will assign particular devices into these windows and + configure the downstream Host-managed Device Memory (HDM) decoders + in root ports, switch ports and devices appropriately to meet the + interleave requirements before enabling the memory devices. + + ``targets.X=3Dtarget`` provides the mapping to CXL host bridges + which may be identified by the id provied in the -device entry. + Multiple entries are needed to specify all the targets when + the fixed memory window represents interleaved memory. X is the + target index from 0. + + ``size=3Dsize`` sets the size of the CFMW. This must be a multiple= of + 256MiB. The region will be aligned to 256MiB but the location is + platform and configuration dependent. + + ``interleave-granularity=3Dgranularity`` sets the granularity of + interleave. Default 256KiB. Only 256KiB, 512KiB, 1024KiB, 2048KiB + 4096KiB, 8192KiB and 16384KiB granularities supported. + + Example: + + :: + + -machine cxl-fmw.0.targets.0=3Dcxl.0,cxl-fmw.0.targets.1=3Dcxl= .1,cxl-fmw.0.size=3D128G,cxl-fmw.0.interleave-granularity=3D512k ERST =20 DEF("M", HAS_ARG, QEMU_OPTION_M, @@ -467,44 +500,6 @@ SRST -numa hmat-cache,node-id=3D1,size=3D10K,level=3D1,associativity=3D= direct,policy=3Dwrite-back,line=3D8 ERST =20 -DEF("cxl-fixed-memory-window", HAS_ARG, QEMU_OPTION_cxl_fixed_memory_windo= w, - "-cxl-fixed-memory-window targets.0=3Dfirsttarget,targets.1=3Dsecondta= rget,size=3Dsize[,interleave-granularity=3Dgranularity]\n", - QEMU_ARCH_ALL) -SRST -``-cxl-fixed-memory-window targets.0=3Dfirsttarget,targets.1=3Dsecondtarge= t,size=3Dsize[,interleave-granularity=3Dgranularity]`` - Define a CXL Fixed Memory Window (CFMW). - - Described in the CXL 2.0 ECN: CEDT CFMWS & QTG _DSM. - - They are regions of Host Physical Addresses (HPA) on a system which - may be interleaved across one or more CXL host bridges. The system - software will assign particular devices into these windows and - configure the downstream Host-managed Device Memory (HDM) decoders - in root ports, switch ports and devices appropriately to meet the - interleave requirements before enabling the memory devices. - - ``targets.X=3Dfirsttarget`` provides the mapping to CXL host bridges - which may be identified by the id provied in the -device entry. - Multiple entries are needed to specify all the targets when - the fixed memory window represents interleaved memory. X is the - target index from 0. - - ``size=3Dsize`` sets the size of the CFMW. This must be a multiple of - 256MiB. The region will be aligned to 256MiB but the location is - platform and configuration dependent. - - ``interleave-granularity=3Dgranularity`` sets the granularity of - interleave. Default 256KiB. Only 256KiB, 512KiB, 1024KiB, 2048KiB - 4096KiB, 8192KiB and 16384KiB granularities supported. - - Example: - - :: - - -cxl-fixed-memory-window targets.0=3Dcxl.0,targets.1=3Dcxl.1,size= =3D128G,interleave-granularity=3D512k - -ERST - DEF("add-fd", HAS_ARG, QEMU_OPTION_add_fd, "-add-fd fd=3Dfd,set=3Dset[,opaque=3Dopaque]\n" " Add 'fd' to fd 'set'\n", QEMU_ARCH_ALL) diff --git a/softmmu/vl.c b/softmmu/vl.c index 4c1e94b00e..ff0ad9ab54 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -147,12 +147,6 @@ typedef struct BlockdevOptionsQueueEntry { =20 typedef QSIMPLEQ_HEAD(, BlockdevOptionsQueueEntry) BlockdevOptionsQueue; =20 -typedef struct CXLFMWOptionQueueEntry { - CXLFixedMemoryWindowOptions *opts; - Location loc; - QSIMPLEQ_ENTRY(CXLFMWOptionQueueEntry) entry; -} CXLFMWOptionQueueEntry; - typedef struct ObjectOption { ObjectOptions *opts; QTAILQ_ENTRY(ObjectOption) next; @@ -179,8 +173,6 @@ static int snapshot; static bool preconfig_requested; static QemuPluginList plugin_list =3D QTAILQ_HEAD_INITIALIZER(plugin_list); static BlockdevOptionsQueue bdo_queue =3D QSIMPLEQ_HEAD_INITIALIZER(bdo_qu= eue); -static QSIMPLEQ_HEAD(, CXLFMWOptionQueueEntry) CXLFMW_opts =3D - QSIMPLEQ_HEAD_INITIALIZER(CXLFMW_opts); static bool nographic =3D false; static int mem_prealloc; /* force preallocation of physical target memory = */ static const char *vga_model =3D NULL; @@ -1072,24 +1064,6 @@ static void parse_display(const char *p) } } =20 -static void parse_cxl_fixed_memory_window(const char *optarg) -{ - CXLFMWOptionQueueEntry *cfmws_entry; - Visitor *v; - - v =3D qobject_input_visitor_new_str(optarg, "cxl-fixed-memory-window", - &error_fatal); - cfmws_entry =3D g_new(CXLFMWOptionQueueEntry, 1); - visit_type_CXLFixedMemoryWindowOptions(v, NULL, &cfmws_entry->opts, - &error_fatal); - if (!cfmws_entry->opts) { - exit(1); - } - visit_free(v); - loc_save(&cfmws_entry->loc); - QSIMPLEQ_INSERT_TAIL(&CXLFMW_opts, cfmws_entry, entry); -} - static inline bool nonempty_str(const char *str) { return str && *str; @@ -1948,20 +1922,6 @@ static void qemu_create_late_backends(void) qemu_semihosting_console_init(); } =20 -static void cxl_set_opts(void) -{ - while (!QSIMPLEQ_EMPTY(&CXLFMW_opts)) { - CXLFMWOptionQueueEntry *cfmws_entry =3D QSIMPLEQ_FIRST(&CXLFMW_opt= s); - - loc_restore(&cfmws_entry->loc); - QSIMPLEQ_REMOVE_HEAD(&CXLFMW_opts, entry); - cxl_fixed_memory_window_config(current_machine, cfmws_entry->opts, - &error_fatal); - qapi_free_CXLFixedMemoryWindowOptions(cfmws_entry->opts); - g_free(cfmws_entry); - } -} - static void qemu_resolve_machine_memdev(void) { if (ram_memdev_id) { @@ -2789,9 +2749,6 @@ void qemu_init(int argc, char **argv, char **envp) exit(1); } break; - case QEMU_OPTION_cxl_fixed_memory_window: - parse_cxl_fixed_memory_window(optarg); - break; case QEMU_OPTION_display: parse_display(optarg); break; @@ -3598,7 +3555,6 @@ void qemu_init(int argc, char **argv, char **envp) =20 qemu_resolve_machine_memdev(); parse_numa_opts(current_machine); - cxl_set_opts(); =20 if (vmstate_dump_file) { /* dump and exit */ diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index a4a46e97f0..8a3a320aea 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1567,8 +1567,8 @@ static void test_acpi_q35_cxl(void) " -device cxl-type3,bus=3Drp3,memdev=3Dcxl-me= m3,lsa=3Dlsa3" " -device cxl-rp,port=3D1,bus=3Dcxl.2,id=3Drp= 4,chassis=3D0,slot=3D6" " -device cxl-type3,bus=3Drp4,memdev=3Dcxl-me= m4,lsa=3Dlsa4" - " -cxl-fixed-memory-window targets.0=3Dcxl.1,= size=3D4G,interleave-granularity=3D8k" - " -cxl-fixed-memory-window targets.0=3Dcxl.1,= targets.1=3Dcxl.2,size=3D4G,interleave-granularity=3D8k", + " -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.si= ze=3D4G,cxl-fmw.0.interleave-granularity=3D8k," + "cxl-fmw.1.targets.0=3Dcxl.1,cxl-fmw.1.target= s.1=3Dcxl.2,cxl-fmw.1.size=3D4G,cxl-fmw.1.interleave-granularity=3D8k", tmp_path, tmp_path, tmp_path, tmp_path, tmp_path, tmp_path, tmp_path, tmp_path); test_acpi_one(params, &data); diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c index 079011af6a..2133e973f4 100644 --- a/tests/qtest/cxl-test.c +++ b/tests/qtest/cxl-test.c @@ -10,12 +10,12 @@ =20 #define QEMU_PXB_CMD "-machine q35,cxl=3Don " \ "-device pxb-cxl,id=3Dcxl.0,bus=3Dpcie.0,bus_nr=3D52 = " \ - "-cxl-fixed-memory-window targets.0=3Dcxl.0,size=3D4G= " + "-M cxl-fmw.0.targets.0=3Dcxl.0,cxl-fmw.0.size=3D4G " =20 #define QEMU_2PXB_CMD "-machine q35,cxl=3Don " \ "-device pxb-cxl,id=3Dcxl.0,bus=3Dpcie.0,bus_nr=3D52= " \ "-device pxb-cxl,id=3Dcxl.1,bus=3Dpcie.0,bus_nr=3D53= " \ - "-cxl-fixed-memory-window targets.0=3Dcxl.0,targets.= 1=3Dcxl.1,size=3D4G " + "-M cxl-fmw.0.targets.0=3Dcxl.0,cxl-fmw.0.targets.1= =3Dcxl.1,cxl-fmw.0.size=3D4G " =20 #define QEMU_RP "-device cxl-rp,id=3Drp0,bus=3Dcxl.0,chassis=3D0,slot=3D0 " =20 --=20 2.32.0