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([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1lEZUH/ogWVZdNv0ca1wSpWH+sIL1KbkILIib8NO3cE=; b=RBURz8yY+JXWmgs5LI0t6iMxs3GV47TihDPYJN2wdFiQBHrOyJHXwnVf4OQrD7LyFB sBCoTOxXypv5reSUS0X/XcFdHYSoSM0gxyTBVg/AZ+mYE7HyFlL0VoPz2YPror4E6x75 +z+bAbNkJplqUBm0NJy/aZ7x0jycUFki6wnZjoKREvP5aFlrFaIQORONB/OyjR0+izkV YoY9jDTQ/YOSOa4WSNuSEVFYbNmAuMVSg5pfziUuj6aIO+N/InUJcl733+s54PJnZLcV 3+g5msB/wFtlBdLn6ECLTAbcclJmBu0oM/5TE/47uZAMymlJ78llbrttUzmT7kgzLX4X 706w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1lEZUH/ogWVZdNv0ca1wSpWH+sIL1KbkILIib8NO3cE=; b=N5WsPdFlPd4VAzN5836vuPbnvcgrHzOIKoEVhfHoYPUnStqLYYdOHNAZWMieF4wLGV M9ldtVn7wt3KNF7USTCiLDPvFEswpzLS9cIBgxX4VIfCXNraDlnTzwM60f6NHJMyhuKK m71IJ+JhJMA05v0e/Eor+kiHTtRnJDYUoNvq9naIUH60eZpnfvpMCD3PhJAY0WeKd/k/ cHvo50VG1HGKJ0D27IYMZXvcLC3pHGkjTRNNwx89J3Giq1cF6li/WYxAyyXfp4PqibAx 6XNjltqpXlfhgLiH5scaccV/NMerfnALRD6C5a9qoWog0Ua6QNg8yXjfiYugxekFKDgE bUaA== X-Gm-Message-State: AOAM5315oSZgkb1U5SzUdx9s4jBKPgGffgqfrsgrUwkRVtE1ZThOkq0f 2Q23BkstgZqtkpwHknghdyMKu5mxullLvw== X-Google-Smtp-Source: ABdhPJwVf7087rlgW2KRUD0GnjDpphfk1BnnrMQtguR+z/Y4FIZOsYOIimNQ06Zlp2ec133hxC+n2Q== X-Received: by 2002:a17:902:ab8c:b0:167:4d5c:3542 with SMTP id f12-20020a170902ab8c00b001674d5c3542mr22520763plr.6.1654633998493; Tue, 07 Jun 2022 13:33:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 12/71] target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el Date: Tue, 7 Jun 2022 13:32:07 -0700 Message-Id: <20220607203306.657998-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654634708712100001 Content-Type: text/plain; charset="utf-8" This will be used for both Normal and Streaming SVE, and the value does not necessarily come from ZCR_ELx. While we're at it, emphasize the units in which the value is returned. Patch produced by git grep -l sve_zcr_len_for_el | \ xargs -n1 sed -i 's/sve_zcr_len_for_el/sve_vqm1_for_el/g' and then adding a function comment. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 11 ++++++++++- target/arm/arch_dump.c | 2 +- target/arm/cpu.c | 2 +- target/arm/gdbstub64.c | 2 +- target/arm/helper.c | 12 ++++++------ 5 files changed, 19 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4ec2daec2a..2cc28f9e59 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1132,7 +1132,16 @@ void aarch64_sync_64_to_32(CPUARMState *env); =20 int fp_exception_el(CPUARMState *env, int cur_el); int sve_exception_el(CPUARMState *env, int cur_el); -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); + +/** + * sve_vqm1_for_el: + * @env: CPUARMState + * @el: exception level + * + * Compute the current SVE vector length for @el, in units of + * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. + */ +uint32_t sve_vqm1_for_el(CPUARMState *env, int el); =20 static inline bool is_a64(CPUARMState *env) { diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 0184845310..b1f040e69f 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -166,7 +166,7 @@ static off_t sve_fpcr_offset(uint32_t vq) =20 static uint32_t sve_current_vq(CPUARMState *env) { - return sve_zcr_len_for_el(env, arm_current_el(env)) + 1; + return sve_vqm1_for_el(env, arm_current_el(env)) + 1; } =20 static size_t sve_size_vq(uint32_t vq) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0621944167..1b5d535788 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -925,7 +925,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *= f, int flags) vfp_get_fpcr(env), vfp_get_fpsr(env)); =20 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) =3D= =3D 0) { - int j, zcr_len =3D sve_zcr_len_for_el(env, el); + int j, zcr_len =3D sve_vqm1_for_el(env, el); =20 for (i =3D 0; i <=3D FFR_PRED_NUM; i++) { bool eol; diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 596878666d..07a6746944 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -152,7 +152,7 @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *bu= f, int reg) * We report in Vector Granules (VG) which is 64bit in a Z reg * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. */ - int vq =3D sve_zcr_len_for_el(env, arm_current_el(env)) + 1; + int vq =3D sve_vqm1_for_el(env, arm_current_el(env)) + 1; return gdb_get_reg64(buf, vq * 2); } default: diff --git a/target/arm/helper.c b/target/arm/helper.c index 7b6f31e9c8..cb44d528c0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6225,7 +6225,7 @@ int sve_exception_el(CPUARMState *env, int el) /* * Given that SVE is enabled, return the vector length for EL. */ -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) +uint32_t sve_vqm1_for_el(CPUARMState *env, int el) { ARMCPU *cpu =3D env_archcpu(env); uint32_t len =3D cpu->sve_max_vq - 1; @@ -6248,7 +6248,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) { int cur_el =3D arm_current_el(env); - int old_len =3D sve_zcr_len_for_el(env, cur_el); + int old_len =3D sve_vqm1_for_el(env, cur_el); int new_len; =20 /* Bits other than [3:0] are RAZ/WI. */ @@ -6259,7 +6259,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, * Because we arrived here, we know both FP and SVE are enabled; * otherwise we would have trapped access to the ZCR_ELn register. */ - new_len =3D sve_zcr_len_for_el(env, cur_el); + new_len =3D sve_vqm1_for_el(env, cur_el); if (new_len < old_len) { aarch64_sve_narrow_vq(env, new_len + 1); } @@ -13683,7 +13683,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState= *env, int el, int fp_el, sve_el =3D 0; } } else if (sve_el =3D=3D 0) { - DP_TBFLAG_A64(flags, VL, sve_zcr_len_for_el(env, el)); + DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el)); } DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); } @@ -14049,10 +14049,10 @@ void aarch64_sve_change_el(CPUARMState *env, int = old_el, */ old_a64 =3D old_el ? arm_el_is_aa64(env, old_el) : el0_a64; old_len =3D (old_a64 && !sve_exception_el(env, old_el) - ? sve_zcr_len_for_el(env, old_el) : 0); + ? sve_vqm1_for_el(env, old_el) : 0); new_a64 =3D new_el ? arm_el_is_aa64(env, new_el) : el0_a64; new_len =3D (new_a64 && !sve_exception_el(env, new_el) - ? sve_zcr_len_for_el(env, new_el) : 0); + ? sve_vqm1_for_el(env, new_el) : 0); =20 /* When changing vector length, clear inaccessible state. */ if (new_len < old_len) { --=20 2.34.1