From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654634091; cv=none; d=zohomail.com; s=zohoarc; b=gccPsrqphxZZMW2I8o/bOU7PFZhpMvqaSgzfS/WCNjgDx1n0muidYXwSBT8fH88HzhyHBKbJXLImz5WUk3ueIbA48DCL5vgSrTSrWMuiSsAexyu5m6G5gLZOLnytXBGjtzcLuRwIw1hWCfEDvm3kE5l+Q9quHf8f1Di/sHMfEeM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654634091; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AP39jqbPiQO8vlhvr3vURJ9OZT2UOimjCnaJk3rF7/M=; b=Lwn/xgx/jWvO6XbW2vyNhiHbiAFeetRQ1Rcgcbrd++QgurLLUIWHx0zZGmk8UZAzuvKITttkIEsniNhDS+pYrph0QeQLZieJcxcgoCPY0rlee3JLiwqZb9Lv9yLR/hgBR1TrhamtXnLlC+A4cCbIRwRHDIxw8BqDy0wHhVBBwDs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654634091258212.41211059788407; Tue, 7 Jun 2022 13:34:51 -0700 (PDT) Received: from localhost ([::1]:44092 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyfua-0001xz-PP for importer@patchew.org; Tue, 07 Jun 2022 16:34:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33240) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyft3-00079g-8m for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:13 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:40865) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyft0-0007Be-9R for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:13 -0400 Received: by mail-pl1-x62d.google.com with SMTP id i1so15790395plg.7 for ; Tue, 07 Jun 2022 13:33:09 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AP39jqbPiQO8vlhvr3vURJ9OZT2UOimjCnaJk3rF7/M=; b=vgpfk3mvjUZkTNqm14QMdfVoDea50YkP5uMEOvtQveYB27Nhy5EZPwMEvKGinwdbtq nxBUiCr3Gn0GHsBcv3o7WK3CwhTsyT8nArc78e3XPYLM3J1+p1YTabdk1VNUSpYT+gma GgR3hVMVszxrDG5rduz049TuYZ9hrzitYoDtgBZFEokFubTk0aR3MBGFL1EVhKcLPaKI AJbYE2Vuc1QPw1wUIM6+rdco7DgmaH0yL15/lT0vpZl+jR0xioEYNV6wWT03PgnDQIdH icvpaWhuUcOCXnNCOniu/8w5OEErQ6WMbJzpZZzFl1aDDJyoPfH68HqPCXKyGkXvtXm9 XFmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AP39jqbPiQO8vlhvr3vURJ9OZT2UOimjCnaJk3rF7/M=; b=BYYhZHKhDqThsXj1spEuXjKBJJpUj2ZzO8S/oZhuhh/HjbqBgDOdoMHzLYKqxzt3JO KaUshkMM/7aXQAOmyy2Ovc1I4TK2Ce09CewiYUzh02FoEBU0hmtrIvCHuwLB0fmWk2nE /RAVJnhuvt8tB/27qVDEAPAtOq+bui53iITpbfasCzp+yLRmgXZHEL6XvhRcZ8P88uwz zUVIQq4D4ao6O9s/oBik5qRPf9uI/pZLJAkprpjaMCGTfB1uArMTtl9V80m8zRz4LoKT nRMzaXOAXuzEtFbj9KPqh+lZJ5vEAr9fZGJRsM06xahUcOskYqKsb/+ABUn0ySHmBo7i ESag== X-Gm-Message-State: AOAM532cW4DM3UkU6sserWOLonBbATOyNmjhzmLtWkPYgo1Q3hlo3KZy abr3MW3BePedLWZXTAH+8xoXZO8/YcR34Q== X-Google-Smtp-Source: ABdhPJy+vNI48R8/zdRdjTVIxUBUfZ8iXa60SBN5W9uhw+zqbAHCwYGwVnDKeI/KbshJp9UUzk7sDA== X-Received: by 2002:a17:90a:4413:b0:1cd:2d00:9d0b with SMTP id s19-20020a17090a441300b001cd2d009d0bmr33784931pjg.81.1654633988849; Tue, 07 Jun 2022 13:33:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 01/71] target/arm: Rename TBFLAG_A64 ZCR_LEN to VL Date: Tue, 7 Jun 2022 13:31:56 -0700 Message-Id: <20220607203306.657998-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654634092688100001 Content-Type: text/plain; charset="utf-8" With SME, the vector length does not only come from ZCR_ELx. Comment that this is either NVL or SVL, like the pseudocode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Renamed from SVE_LEN to VL. --- target/arm/cpu.h | 3 ++- target/arm/translate-a64.h | 2 +- target/arm/translate.h | 2 +- target/arm/helper.c | 2 +- target/arm/translate-a64.c | 2 +- target/arm/translate-sve.c | 2 +- 6 files changed, 7 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c1865ad5da..015ce12fe2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3241,7 +3241,8 @@ FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* No= t cached. */ */ FIELD(TBFLAG_A64, TBII, 0, 2) FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) -FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) +/* The current vector length, either NVL or SVL. */ +FIELD(TBFLAG_A64, VL, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index f2e8ee0ee1..dbc917ee65 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -104,7 +104,7 @@ static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s= , int regno) /* Return the byte size of the "whole" vector register, VL / 8. */ static inline int vec_full_reg_size(DisasContext *s) { - return s->sve_len; + return s->vl; } =20 bool disas_sve(DisasContext *, uint32_t); diff --git a/target/arm/translate.h b/target/arm/translate.h index 9f0bb270c5..f473a21ed4 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -42,7 +42,7 @@ typedef struct DisasContext { bool ns; /* Use non-secure CPREG bank on access */ int fp_excp_el; /* FP exception EL or 0 if enabled */ int sve_excp_el; /* SVE exception EL or 0 if enabled */ - int sve_len; /* SVE vector length in bytes */ + int vl; /* current vector length in bytes */ /* Flag indicating that exceptions from secure mode are routed to EL3.= */ bool secure_routed_to_el3; bool vfp_enabled; /* FP enabled via FPSCR.EN */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 40da63913c..960899022d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13696,7 +13696,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState= *env, int el, int fp_el, zcr_len =3D sve_zcr_len_for_el(env, el); } DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); - DP_TBFLAG_A64(flags, ZCR_LEN, zcr_len); + DP_TBFLAG_A64(flags, VL, zcr_len); } =20 sctlr =3D regime_sctlr(env, stage1); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 935e1929bb..d438fb89e7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14608,7 +14608,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il =3D EX_TBFLAG_ANY(tb_flags, PSTATE__IL); dc->sve_excp_el =3D EX_TBFLAG_A64(tb_flags, SVEEXC_EL); - dc->sve_len =3D (EX_TBFLAG_A64(tb_flags, ZCR_LEN) + 1) * 16; + dc->vl =3D (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; dc->pauth_active =3D EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); dc->bt =3D EX_TBFLAG_A64(tb_flags, BT); dc->btype =3D EX_TBFLAG_A64(tb_flags, BTYPE); diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 836511d719..67761bf2cc 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -111,7 +111,7 @@ static inline int pred_full_reg_offset(DisasContext *s,= int regno) /* Return the byte size of the whole predicate register, VL / 64. */ static inline int pred_full_reg_size(DisasContext *s) { - return s->sve_len >> 3; + return s->vl >> 3; } =20 /* Round up the size of a register to a size allowed by --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654634920; cv=none; d=zohomail.com; s=zohoarc; b=HQFqPPPKg4d0RSEDY+CiMdDpQ7wStr21SXXVDJ2PMgywswexpVBz3mgkKAshEovHoDdjEVWnSwIvQcrWNvgzty2jPEkAQSo/FQomx8WL5Hn1KF5V3xOUpmaLjwbWP2ZzoWPP42uG4WYd4GB5O661RfrzGTx/myf4yD8NO93W34Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654634920; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5Y1P1Y+Ffb//73mSlBoiFZFZX3qfQHSQssa2vHrkCbU=; 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([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5Y1P1Y+Ffb//73mSlBoiFZFZX3qfQHSQssa2vHrkCbU=; b=e7s6XLU3e+TZeIlsfNcOEYyQpDmpnKxIhCX8e/s4WsAluW8iDW6yAtUSkPVrwHokYU xKxJfUQTPrd2So2zNtGkbMTwWmoofM71hlsU2S6mNC8/2VR01BPmxQYDPwDjyNSmCw9j 1Tavx57VU0YoFDHjUCIy+DV9aZ1JyYYoogfJ/wbaF1uAW2KryA7/tE2RSlakiKkK998P I8NW3wSeiMf1uEq0qjv37ywAaXTjbkxJbDc0mA9NwU7PCHCA3opiUrSVTWDHy7hUCGK9 k7gUNWdpiAYUCjx5fS5D3rj3Pf2ZLNc0XbfhBj8FSoG5I4D2SH6O6Q2oCsxeNODRgweU wmrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5Y1P1Y+Ffb//73mSlBoiFZFZX3qfQHSQssa2vHrkCbU=; b=pBO6bMwL5fqeyFJEPM2VnvhoakFCeEBOtpMM+tLZV3edZoHV1wPJza8O+GAiN5fvJO bYkF6uza+vAnwWLtCpV9hyvPwzlzytJSA8Z5eJ2z2X2qaSnKKFtY4fwX9G2umBy8Nq4W dWY94ulNxivMX6OqpNVodkHqlVmb4/4A3kAY5os+1qjQYo3OlJKgB47RYkzT+dDNtQzb S67CxiaWVHYVdg6z84q2grDPmhdg1/ra/CxhjMvlT1kH706pk9bS5uJUDeaHp0TaiAba U9OdL+tvotmNpXTSJf1x9de3ZjFLAwnwx6zK0wNe2VKiHBk2n2+jhmtlE9riOEZJNAhQ 6yWg== X-Gm-Message-State: AOAM530qHpIHvgPc2Ulfew9W5PdCHwfixW+uqSycTWykfvpYAiZSDLc0 w7wp88DP1Y0/411m9T1SO1hvBQ3wqmDrgg== X-Google-Smtp-Source: ABdhPJyNVgSSFSYg2lcXq7+1k94mLNnUutPsXNw7f9jZ0rDK/ijt4m3hckqHQlarKcE9y6jwjMsObg== X-Received: by 2002:a17:90a:bc98:b0:1e8:6895:645e with SMTP id x24-20020a17090abc9800b001e86895645emr17990399pjr.131.1654633989714; Tue, 07 Jun 2022 13:33:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 02/71] linux-user/aarch64: Introduce sve_vq Date: Tue, 7 Jun 2022 13:31:57 -0700 Message-Id: <20220607203306.657998-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654634921900100001 Content-Type: text/plain; charset="utf-8" Add an interface function to extract the digested vector length rather than the raw zcr_el[1] value. This fixes an incorrect return from do_prctl_set_vl where we didn't take into account the set of vector lengths supported by the cpu. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Add sve_vq_cached rather than directly access hflags. v3: Rename to sve_vq. --- linux-user/aarch64/target_prctl.h | 20 +++++++++++++------- target/arm/cpu.h | 11 +++++++++++ linux-user/aarch64/signal.c | 4 ++-- 3 files changed, 26 insertions(+), 9 deletions(-) diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_= prctl.h index 3f5a5d3933..1d440ffbea 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -10,7 +10,7 @@ static abi_long do_prctl_get_vl(CPUArchState *env) { ARMCPU *cpu =3D env_archcpu(env); if (cpu_isar_feature(aa64_sve, cpu)) { - return ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; + return sve_vq(env) * 16; } return -TARGET_EINVAL; } @@ -25,18 +25,24 @@ static abi_long do_prctl_set_vl(CPUArchState *env, abi_= long arg2) */ if (cpu_isar_feature(aa64_sve, env_archcpu(env)) && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { - ARMCPU *cpu =3D env_archcpu(env); uint32_t vq, old_vq; =20 - old_vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; - vq =3D MAX(arg2 / 16, 1); - vq =3D MIN(vq, cpu->sve_max_vq); + old_vq =3D sve_vq(env); =20 + /* + * Bound the value of arg2, so that we know that it fits into + * the 4-bit field in ZCR_EL1. Rely on the hflags rebuild to + * sort out the length supported by the cpu. + */ + vq =3D MAX(arg2 / 16, 1); + vq =3D MIN(vq, ARM_MAX_VQ); + env->vfp.zcr_el[1] =3D vq - 1; + arm_rebuild_hflags(env); + + vq =3D sve_vq(env); if (vq < old_vq) { aarch64_sve_narrow_vq(env, vq); } - env->vfp.zcr_el[1] =3D vq - 1; - arm_rebuild_hflags(env); return vq * 16; } return -TARGET_EINVAL; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 015ce12fe2..6e35e30000 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3286,6 +3286,17 @@ static inline int cpu_mmu_index(CPUARMState *env, bo= ol ifetch) return EX_TBFLAG_ANY(env->hflags, MMUIDX); } =20 +/** + * sve_vq + * @env: the cpu context + * + * Return the VL cached within env->hflags, in units of quadwords. + */ +static inline int sve_vq(CPUARMState *env) +{ + return EX_TBFLAG_A64(env->hflags, VL) + 1; +} + static inline bool bswap_code(bool sctlr_b) { #ifdef CONFIG_USER_ONLY diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 7de4c96eb9..7da0e36c6d 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -315,7 +315,7 @@ static int target_restore_sigframe(CPUARMState *env, =20 case TARGET_SVE_MAGIC: if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { - vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; + vq =3D sve_vq(env); sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq)= , 16); if (!sve && size =3D=3D sve_size) { sve =3D (struct target_sve_context *)ctx; @@ -434,7 +434,7 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, =20 /* SVE state needs saving only if it exists. */ if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { - vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; + vq =3D sve_vq(env); sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); sve_ofs =3D alloc_sigframe_space(sve_size, &layout); } --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654634102; cv=none; d=zohomail.com; s=zohoarc; b=Ke42mZnL240XLTJe6mvRnuTD5Jd7m/Px2bYv3vCQxzD9GVKDVbSRl4cNic3UzWrHXuujl2KSjCSV9aMKgQ6RkILCnV/Bt/LXx/1KNrb1hVakFxT8x8JBQuCsl7MzE+SITo51yFKvdJUxYWbkXZTeLiNHRMXgGRjQsRvwtwuRiyA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654634102; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pLpYyWtmw6OHm0KZCjVI06POe96iERl3wGHLBQYXyAM=; b=e8rDItOW5wIeEsl0lORZNdDSweRT0hJ8TGOr2bI/xBnpxIL3IqL6yk4FpQx3otIScnKG1rGoUf+xdLZJrq72yP8QJMvM5kKTTSt5CxBR3fGbrgrwZ+s4IqEQ0SRp8hceDW+fGmzkGi5OD7knNUVaUyG/OtSpRw9nMuftqdYiQK4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654634102853767.88631038134; Tue, 7 Jun 2022 13:35:02 -0700 (PDT) Received: from localhost ([::1]:45096 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyfun-0002cb-7b for importer@patchew.org; Tue, 07 Jun 2022 16:35:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33328) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyft6-0007E2-0P for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:16 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:46724) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyft2-0007D6-2R for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:15 -0400 Received: by mail-pl1-x633.google.com with SMTP id d13so133192plh.13 for ; Tue, 07 Jun 2022 13:33:11 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pLpYyWtmw6OHm0KZCjVI06POe96iERl3wGHLBQYXyAM=; b=M1VSKjuUvYAaG+gSzge94JduXDpf66YFWnzbHFZhUb6vHNVbIvM1JXkrZRdXDvmMrA JYrFhtdEhiphCgl2bTkuyOO109zBWaF5q6yIBbSVEpCeqE0rH9B6zUURXqUHckAu/CPA y5VDavPWlxcouT47hW5woqMJJ3B1sBuKd0U9VVX+p3MdvdJiWoqdbCJKvQ3aiEHWgF+j TeZXrQfQd0zpE0E/rZY6k8Ykthj1THio84KaiVux18BFpYMonmlqoqJOsYQV+qxRulCy gav7qZHU3qzBLEx/AvkSxuRE1yvfrHfbCkixqpSdL/N2D5qW71KX+IPd9IucDaze/wV3 0kvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pLpYyWtmw6OHm0KZCjVI06POe96iERl3wGHLBQYXyAM=; b=qD/42BC3RGiauyVl/my6nBLngs57ytHqU2yLJNYKMqT4GAxe3quZAlhX3cw/lg2TYl G8GqtJXYfSjsmDuZbfn8ZIcK89lFm3ud6yrEqOxR+52PfuDODQuGx5/QJBVBLjb8XP0Q s+PI1R5hyW+2Pv1YvWwXhNg9k9FsC+XK451fbm8cAq0nNArNoD6WWfckug7lPGgdli6J iPfC1P3dD44fsjyRIWfzsk9IT+bpVDzbW7W+OXXYH1+WnVXQEbd9H8SOCC9zOZ6rKo5Z ygQ1jqVGP8ywYKE2rMUv3iVj9MOIXKZ5X37wVceXcEzV90TS3ZYgB/GJKTWmCckJiu5u 0QCA== X-Gm-Message-State: AOAM532Kn3BrxUtTKjaI+YmsijK7OUbq9zJe/2Z/i6csGaXcmbMYUlH1 jdAl9MydvjO5jXVkXhG7DOS5LSaZkcYZ/g== X-Google-Smtp-Source: ABdhPJw8/h207Bcnk7+Qy61uVFdxTH32CYmlgDCR2Cqs7TGZO5td9dNPIqCsr9oAkEcr12eS5QRyLw== X-Received: by 2002:a17:902:bb90:b0:158:a031:2ff2 with SMTP id m16-20020a170902bb9000b00158a0312ff2mr30624511pls.117.1654633990680; Tue, 07 Jun 2022 13:33:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 03/71] target/arm: Remove route_to_el2 check from sve_exception_el Date: Tue, 7 Jun 2022 13:31:58 -0700 Message-Id: <20220607203306.657998-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654634104691100003 Content-Type: text/plain; charset="utf-8" We handle this routing in raise_exception. Promoting the value early means that we can't directly compare FPEXC_EL and SVEEXC_EL. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 960899022d..8ace3ad533 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6159,8 +6159,7 @@ int sve_exception_el(CPUARMState *env, int el) /* fall through */ case 0: case 2: - /* route_to_el2 */ - return hcr_el2 & HCR_TGE ? 2 : 1; + return 1; } =20 /* Check CPACR.FPEN. */ --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654634314; cv=none; d=zohomail.com; s=zohoarc; b=ktYQqP8T8kr454Uf2gXmspurVSyHcwBjjgsFW9vtdxqnEgZ/DlEghaWM0Mvh4pd06+I2NX3XgFlnOuyK+R0QPwMXBTPc4XQIi3ChdljFJ0nnFSbk4sxoraURaSGOSfS04jS73bdYpr9x+7TzcgYPpFEG1zOaaCCw0frXgik+aqU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654634314; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=e7CiA9DdlCOhWlL8CEoveJRO9oJ9GQCNXOqZts3HTb4=; b=bfTbwPdTO3bcbrx+Q/9OjjcbomjUQnHtEY5pRSZajLMEML16SKNor955Oc/2zlPTX46pmX3MeLE1smr9xT+X1+YHxgdPlF0r77WvmSuo0mb77+SQFPYVkzJ2IlqggeRm0PsIms7Ct3AHraZwh17ud5/AV/GUbg4E6+ox93pvZGA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654634314288900.1477778719241; Tue, 7 Jun 2022 13:38:34 -0700 (PDT) Received: from localhost ([::1]:53928 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyfyD-0000IJ-9Y for importer@patchew.org; Tue, 07 Jun 2022 16:38:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33408) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyft9-0007LB-4B for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:19 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:45954) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyft3-0007DT-TN for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:18 -0400 Received: by mail-pl1-x62b.google.com with SMTP id q18so15770169pln.12 for ; Tue, 07 Jun 2022 13:33:12 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e7CiA9DdlCOhWlL8CEoveJRO9oJ9GQCNXOqZts3HTb4=; b=J5l+3uNyyW6MoPnfGXjWfbVBrdcuRdUBkBrsfu9urswiJraDqWhQr5kv0LIrqDutTR 0nM1Kv9UDP+b+8yFXywOa8r3m4bvV5MYJT1+L0lmnVAWnnUXeXiIfjOpwcBCJVV6hkr5 9zA0eRoncytGMjhIgaE6ivWfessl81U9fo3rqQBCCnkY8871I0eQgdIrtcv4fglIWS1l WP5zt7jo3wCHdbqdqyLxzZCt+JIBA/GB4EVEOjOx+W77BxtxSJeh+uD/3iB6lM40BdUg tJ3vWh7Co4dKSNfZSrzamh3RHs/X4BREesKAojQfunDDRKhRwrTdyPt0hsncA2d7+KJt XPag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e7CiA9DdlCOhWlL8CEoveJRO9oJ9GQCNXOqZts3HTb4=; b=GPYL1kY9gr2Sqw4gY8ZajDqj6MbiYXfd4EUfuAA5rmc8CGnjtfObVi4V8v5HGLT7Au tL5s4t7yO7/rPXz0NXLzfh0PGerF373CcOl8bnXPmlqB/uZjy7UlNCm87uFOtvlT8MTC ff7oReoVbYazD9QS1wzvcUhafzegn70WFoD17703YgIlZAsxPbqqdKmDCkWeExb+fvE3 xM7OuZbFfW47E9OSbPAQagr9M7uyBrLjDtbfzKUr2wD4CQ/L6+X5UArT06Y1SXxedZ99 R85Nko1gu80OXEDUvAT/nfxJTdO2Iax8e94bEKfjTuyN4PMsbdoJ9ge1oai20aDsFdYd lmPg== X-Gm-Message-State: AOAM530RaOB1JIEF+ueiOTgEb8ZikNaWHvvE9YhIVVq40qa+hbHzeE34 cC326kUBb2t/n4GXYRT86Y9dIu9qih6NCA== X-Google-Smtp-Source: ABdhPJy+7NbklkH1e51mGy2lhi+jx4onISpG8XuSCsBg5s9QpWAsFclfqn1u//rmsL3RjzefIuhbRw== X-Received: by 2002:a17:90b:350b:b0:1e8:5177:fe7d with SMTP id ls11-20020a17090b350b00b001e85177fe7dmr22022931pjb.142.1654633991509; Tue, 07 Jun 2022 13:33:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 04/71] target/arm: Remove fp checks from sve_exception_el Date: Tue, 7 Jun 2022 13:31:59 -0700 Message-Id: <20220607203306.657998-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654634315537100003 Content-Type: text/plain; charset="utf-8" Instead of checking these bits in fp_exception_el and also in sve_exception_el, document that we must compare the results. The only place where we have not already checked that FP EL is zero is in rebuild_hflags_a64. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 58 +++++++++++++++------------------------------ 1 file changed, 19 insertions(+), 39 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8ace3ad533..bcf48f1b11 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6139,11 +6139,15 @@ static const ARMCPRegInfo minimal_ras_reginfo[] =3D= { .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.vses= r_el2) }, }; =20 -/* Return the exception level to which exceptions should be taken - * via SVEAccessTrap. If an exception should be routed through - * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should - * take care of raising that exception. - * C.f. the ARM pseudocode function CheckSVEEnabled. +/* + * Return the exception level to which exceptions should be taken + * via SVEAccessTrap. This excludes the check for whether the exception + * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily + * be found by testing 0 < fp_exception_el < sve_exception_el. + * + * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the + * pseudocode does *not* separate out the FP trap checks, but has them + * all in one function. */ int sve_exception_el(CPUARMState *env, int el) { @@ -6161,18 +6165,6 @@ int sve_exception_el(CPUARMState *env, int el) case 2: return 1; } - - /* Check CPACR.FPEN. */ - switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN)) { - case 1: - if (el !=3D 0) { - break; - } - /* fall through */ - case 0: - case 2: - return 0; - } } =20 /* @@ -6190,24 +6182,10 @@ int sve_exception_el(CPUARMState *env, int el) case 2: return 2; } - - switch (FIELD_EX32(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) { - case 1: - if (el =3D=3D 2 || !(hcr_el2 & HCR_TGE)) { - break; - } - /* fall through */ - case 0: - case 2: - return 0; - } } else if (arm_is_el2_enabled(env)) { if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) { return 2; } - if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) { - return 0; - } } } =20 @@ -13683,19 +13661,21 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMSta= te *env, int el, int fp_el, =20 if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { int sve_el =3D sve_exception_el(env, el); - uint32_t zcr_len; =20 /* - * If SVE is disabled, but FP is enabled, - * then the effective len is 0. + * If either FP or SVE are disabled, translator does not need len. + * If SVE EL > FP EL, FP exception has precedence, and translator + * does not need SVE EL. Save potential re-translations by forcing + * the unneeded data to zero. */ - if (sve_el !=3D 0 && fp_el =3D=3D 0) { - zcr_len =3D 0; - } else { - zcr_len =3D sve_zcr_len_for_el(env, el); + if (fp_el !=3D 0) { + if (sve_el > fp_el) { + sve_el =3D 0; + } + } else if (sve_el =3D=3D 0) { + DP_TBFLAG_A64(flags, VL, sve_zcr_len_for_el(env, el)); } DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); - DP_TBFLAG_A64(flags, VL, zcr_len); } =20 sctlr =3D regime_sctlr(env, stage1); --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654634254; cv=none; d=zohomail.com; s=zohoarc; b=EQcamc+ZHQyiUATUx/xjqLVj7ecaEOGD9hcFDM/vNEvFHW3T3nYQZfzcQBSYpdI3VCrPXh/nq/W4aIjg/umGw9ACkKKKRhMutWIL3WXXBxdssouj8l4fPdfD2zlf+R3VjNu27RuzUZYtA3XXksilQGmmaJ3eS4P6Vmh+Uy0xPkk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654634254; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bgSSWj3FWGjqqOHg3NGXEoGoqiXuSmAzBvkeO1FtIzY=; b=aKHtqYWlIJe+7PWcSb2BLqfAgVzp37qm7m9AOKWyivDNId6j9/KkPQyhRHqIyxUs3FozmxU0WkpJLGXmqULBJ0ql5k5shBXt02e6gidMT1eA9e1CEOQPE5hTg/9Ps4x7s8x/c304gc/3oAh8XKWrQmCWaD2jn3xA7LzlNr3IzkA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654634254265233.38086927431561; Tue, 7 Jun 2022 13:37:34 -0700 (PDT) Received: from localhost ([::1]:50730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyfxE-0006RK-Rf for importer@patchew.org; Tue, 07 Jun 2022 16:37:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33372) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyft7-0007HV-7U for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:17 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:53042) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyft3-0007Df-LN for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:16 -0400 Received: by mail-pj1-x1032.google.com with SMTP id gd1so16669569pjb.2 for ; Tue, 07 Jun 2022 13:33:13 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bgSSWj3FWGjqqOHg3NGXEoGoqiXuSmAzBvkeO1FtIzY=; b=WQfeqX1U+IFBpsPRJTcz748nuIuq87IcS6s8MhUOl8rTJ8kk68tIQyEP4guqvNB8dp VUymy3PVaIsPJSUqaBAG1XsWLAVz9WrFu1MIYMxTNw1t0SlZGA6XThZGhIqe8rUsZJoO 3+W7xxRqmmZcxFcawoH+Utc6BhOanbPqSm2O57Zvvu3zHGyy9QmrJZ30D57X7WChu59K c88XOwMrB8es88jk9DKGjT/HDUKTTtroasiEjvx5hQOEh0SxZUz85HoehAjLRNZQ5hMc tGJTPRNxMn9sv8KZ+GRxRO3t4wgmNVzbGakXsLwtTqyRfKiSpMo1Q1ZHrP2iZOxUR/kw vA8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bgSSWj3FWGjqqOHg3NGXEoGoqiXuSmAzBvkeO1FtIzY=; b=uHugxMOgDhLDy7tEJMKZUinAw/w296wvKrA3DVQhPAdpWahimMC7Gg9ZaMXEDyMyPD gIZJCc9Kzag6Dw6Nq18PDp7+lhFd4TGwcSOL+xL6mPGO81/jy+XoNZKlts5SM1zwRO2w yrnlZHQWOFRUy7vOwgc6+ll2PqKutAlg7KX3s3AaxI9/e9h/RYe2kRkxdPngx8V1dyod xhljBL+CpNbruKjfUrXQiPS2LRNTYJgHRSWMlZgTb4OmpAryHcIByRPya8i3vTKjrMow qe0FZ1Y/0EPoksUEd3ARXxbsGaauIKaJP2R+YCRbDSAu+Nu2PlVlbvjogi1FdW114ksY v89w== X-Gm-Message-State: AOAM530RGly2YKG4tmWbibUnC5bjJxAtDD1Vj4nFIYQATCGh/Jpw6wQk mIVuY448iuRrT4oV7S038GWQkDmvf5hS+w== X-Google-Smtp-Source: ABdhPJyI2/kz8fzoIbziI7kmc0mnosqxP+zauB/QzOclprY+79e16MVKTPC39K7TSMmuuAUpXi7JUg== X-Received: by 2002:a17:903:41d0:b0:167:68a7:c2f with SMTP id u16-20020a17090341d000b0016768a70c2fmr17693386ple.148.1654633992263; Tue, 07 Jun 2022 13:33:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 05/71] target/arm: Add el_is_in_host Date: Tue, 7 Jun 2022 13:32:00 -0700 Message-Id: <20220607203306.657998-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654634255145100001 Content-Type: text/plain; charset="utf-8" This (newish) ARM pseudocode function is easier to work with than open-coded tests for HCR_E2H etc. Use of the function will be staged into the code base in parts. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 ++ target/arm/helper.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index b654bee468..a73f2a94c5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1328,6 +1328,8 @@ static inline void define_cortex_a72_a57_a53_cp_regin= fo(ARMCPU *cpu) { } void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); #endif =20 +bool el_is_in_host(CPUARMState *env, int el); + void aa32_max_features(ARMCPU *cpu); =20 #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index bcf48f1b11..839d6401b0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5292,6 +5292,34 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) return ret; } =20 +/* + * Corresponds to ARM pseudocode function ELIsInHost(). + */ +bool el_is_in_host(CPUARMState *env, int el) +{ + uint64_t mask; + + /* + * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff(). + * Perform the simplest bit tests first, and validate EL2 afterward. + */ + if (el & 1) { + return false; /* EL1 or EL3 */ + } + + /* + * Note that hcr_write() checks isar_feature_aa64_vh(), + * aka HaveVirtHostExt(), in allowing HCR_E2H to be set. + */ + mask =3D el ? HCR_E2H : HCR_E2H | HCR_TGE; + if ((env->cp15.hcr_el2 & mask) !=3D mask) { + return false; + } + + /* TGE and/or E2H set: double check those bits are currently legal. */ + return arm_is_el2_enabled(env) && arm_el_is_aa64(env, 2); +} + static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654634448; cv=none; d=zohomail.com; s=zohoarc; b=BAlmClKePYgEJAe9NC7IrzGqBs6GRT1sHrudDqkM6AOcvC5PHKdaJUuLPZuS4GGe56H9aowxdVmcWLHw+GXq3REfs2mCQCRi1Wno/PKJtWrwA85ETdaUF37XskqsXVyJukNhL15IJ3ZMEwR4VGPvNX80u8s6HWgUT+lGc17fqdI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654634448; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gadtRptqMEMWzO7/udpBazlKdbGTM/FsnG+P+qdCdG4=; b=NlbcgLqBMCPMtzYNlDPdB2ZHllwrFQ3/QcYzP/DhE4JYPdyCfanwVeopLUNsA+J2t8BmHIb/Xj42Fdg1g0CF3hwBij7aBtZZrxy7uvUx/qvhOJMbwCZwMr0ifbrJ3HkLJz0MMfcv/wI35Pv87yV3D5dzPKP/mB/fTAjCl1YnKAs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654634448013253.72384380666824; Tue, 7 Jun 2022 13:40:48 -0700 (PDT) Received: from localhost ([::1]:59484 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyg0M-00045n-7y for importer@patchew.org; Tue, 07 Jun 2022 16:40:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33398) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyft8-0007KK-Ff for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:18 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:44794) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyft4-0007E1-B2 for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:18 -0400 Received: by mail-pj1-x1034.google.com with SMTP id gc3-20020a17090b310300b001e33092c737so16421711pjb.3 for ; Tue, 07 Jun 2022 13:33:13 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gadtRptqMEMWzO7/udpBazlKdbGTM/FsnG+P+qdCdG4=; b=G8ki5poRn/nJZL+hfoJ7szwVMJv0HsA41Sf8kg4mIpzhQHc6d81MefRFl1F6jasI3x 7kLczGQ8+oapdRWSEex7wCKhVnOXGpzxOBi/xbC8JCgGlHS2PS9iSNQ37vnisfuM2F0X D49/JGFyPvJ1mvg3ClUmT0lny+2v/jK2/xvTW3+lSuXy/uOVy9kWohBKbGs9pBcn8JSo 3x7OalSaIDzAkFA5B0LzwBEBxztFYLsMsw849V/0PG8Qe0T7mt51YCI05hVW4RIIFh8l tgZHgZAp1T01tVXT5oSGg4qp7wc9PQlYlSE7APkq6QmTL0un7GZebJU/iRJ1JaYApp0O yxew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gadtRptqMEMWzO7/udpBazlKdbGTM/FsnG+P+qdCdG4=; b=DIqkx2qowqz/EDRJdrJvnQ1/YPdPSmdc47jTjLMM3uwby/YMznsVBRyr70A1j4Y/wh nKy8VbeEXF8kyUGLdMZrhaOIeBn8uNRXB9Bl7ChpoOhOZgn5/vIfeBL23tbzl++eyXc0 Xzioc2/rmZW2o6E9yRXl4OrfMiUdruShkaw1eyn2HUTTLTtjGhiF7aCAw+cGxgtAhs3E RlTa+FDRajqV+nZLMn1TydIV5CfRRQ9sgHq4p0GgLBMKQc4/qpeSFg2Kjqxqz/BRy1Ln 900QwfSLVSxja/wMDLivhXXeAKPKzg+5gffa0uVdmYN2Xz5RjHCXVxPnYo4vMIiccWtO ETEg== X-Gm-Message-State: AOAM533OCwHogukUtWGpC3O7I3mXCbHFu/R2EEFM4NSf8+caY9jQQnCk /t9sgSjyV3vNGWxLg8IQMGdevHwa84M8HA== X-Google-Smtp-Source: ABdhPJzh7x8mhBjYQS7HKItPqh697NCApb9w3hYqlBOMVNBI18UMNIul6FmyDLXlGYijEYxEUg3a6A== X-Received: by 2002:a17:902:aa4b:b0:164:11ad:af0f with SMTP id c11-20020a170902aa4b00b0016411adaf0fmr30974938plr.54.1654633993129; Tue, 07 Jun 2022 13:33:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 06/71] target/arm: Use el_is_in_host for sve_zcr_len_for_el Date: Tue, 7 Jun 2022 13:32:01 -0700 Message-Id: <20220607203306.657998-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654634448870100001 Content-Type: text/plain; charset="utf-8" The ARM pseudocode function NVL uses this predicate now, and I think it's a bit clearer. Simplify the pseudocode condition by noting that IsInHost is always false for EL1. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 839d6401b0..135c3e790c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6248,8 +6248,7 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) ARMCPU *cpu =3D env_archcpu(env); uint32_t zcr_len =3D cpu->sve_max_vq - 1; =20 - if (el <=3D 1 && - (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { + if (el <=3D 1 && !el_is_in_host(env, el)) { zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); } if (el <=3D 2 && arm_feature(env, ARM_FEATURE_EL2)) { --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654634312; cv=none; d=zohomail.com; s=zohoarc; b=BICiGJFmqxZF5TKKD3CTsLSt/pXxRkRSvfLIwUqSh/udRP12occHxDRmcQN7DP+DTJU6+N6xYhqbymfOJq9CjKH5/KQxXKHK6PwDPgHyZnKnrNozs6rKbSKSDPrk3XsEHgmMd3GuQo320C/ByJVyNYkmXKcatiKARTRwuMhFJ0o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654634312; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=swxajT381TgS1/Nf3oQ+qlH3g7Wj94ec884EPLSXaF4=; b=IDOK56NarVA7DojHz9ufeoYF0Qd4mNW/cdSWTPnF7ag3pCwlIdxiNXq0IJvBr07ZLt8ejtbS3ppfamFDZ+FgfkvArP3ANN5M7YHTAdTxc9NseJ8XyCKdVH30Av43flOW5gB4aM7v6rMVLDDbwVsO/I+adlYn4NM/g4C/1lvxXPs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654634312237788.0351549565411; Tue, 7 Jun 2022 13:38:32 -0700 (PDT) Received: from localhost ([::1]:53882 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyfyB-0000Ff-6b for importer@patchew.org; Tue, 07 Jun 2022 16:38:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33456) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftB-0007RQ-Dn for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:21 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:46970) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyft6-0007EG-6o for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:21 -0400 Received: by mail-pj1-x102d.google.com with SMTP id k5-20020a17090a404500b001e8875e6242so5675660pjg.5 for ; Tue, 07 Jun 2022 13:33:14 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=swxajT381TgS1/Nf3oQ+qlH3g7Wj94ec884EPLSXaF4=; b=n1DpIQ/LMVvrHA7TxsZMtqrtiALLahHuP9JVkFGEowc7tRrlaYPvxF4UgSRTkYyo4a gWjC+qX4Pl3A0ZXRdO9nHtBA+4Gtmb3ELx8CKd2tWsBdoTYGABfltN7xLfMR4lAJtxf7 H61D3ix54qmq2gVqgaYmogV2ABu6odj0bir6m+yrkq1OcX7V6KhvjJ9wL7k6OZH+Qfmn 5QlpJhDmf38sLEnkIE7lgx/pAvqCY7d4Aek4hUoPcU5bL74RIdwNm5R0H4NAsp6FtNZ3 F9AQCU9H325+VFZGay/wuDOZRVFvjfc+vj29+O3u4CfBwx0MAjhWZg/oUnrsyxzFfxmy BUzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=swxajT381TgS1/Nf3oQ+qlH3g7Wj94ec884EPLSXaF4=; b=Mk9QI3Xc7sM11hFBrzcWz2CundORfe/Lb70HFyjKHW8DpjG3Uu9UiKjwXGvMKJyU+0 2tL2LjUqiLpgEedVVlaNprCEmlUmcg+cicQLes1xIoLkk85cAdUGoqT/z7IBq3ARkgc8 1vE9irCaJfhmfJTPil/wPe0jcPQ1tQoTL0/PAVzzU3TqVIQ4ZpeXQqpqZOn/hGWXjL+4 inDKk1z2vTTAngzr90tuqpbNTpNr3jjl6WtRDL3rtCBqqu62WT7NwPhw/OBsWBBUdCAX rTZLh+r84ADQXPRvMWsTpiNIfQESQfcDV3UMqsrMq+y37fq3WMN3Sg5xepHXtMk97dws l0Rw== X-Gm-Message-State: AOAM530zgXuHZs3I81J3BdhgzZgPC6T1+8QGGSvLnhnRPA4lssuQPH2u FswXeGRigS7oMawsvFIQHXKzWj9ezJhebg== X-Google-Smtp-Source: ABdhPJzRR/9S8z+8KbDNCP4nIho/B5FJvobVAaPDYrQ2adXSo65YXAscO/5h1kRFwq6zVgdALYTzKQ== X-Received: by 2002:a17:90b:1b01:b0:1e3:421c:90f with SMTP id nu1-20020a17090b1b0100b001e3421c090fmr41869910pjb.59.1654633993906; Tue, 07 Jun 2022 13:33:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 07/71] target/arm: Use el_is_in_host for sve_exception_el Date: Tue, 7 Jun 2022 13:32:02 -0700 Message-Id: <20220607203306.657998-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654634313524100001 Content-Type: text/plain; charset="utf-8" The ARM pseudocode function CheckNormalSVEEnabled uses this predicate now, and I think it's a bit clearer. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 135c3e790c..7319c91fc2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6180,9 +6180,7 @@ static const ARMCPRegInfo minimal_ras_reginfo[] =3D { int sve_exception_el(CPUARMState *env, int el) { #ifndef CONFIG_USER_ONLY - uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); - - if (el <=3D 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { + if (el <=3D 1 && !el_is_in_host(env, el)) { switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, ZEN)) { case 1: if (el !=3D 0) { @@ -6199,6 +6197,7 @@ int sve_exception_el(CPUARMState *env, int el) * CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */ if (el <=3D 2) { + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); if (hcr_el2 & HCR_E2H) { switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, ZEN)) { case 1: --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654634429; cv=none; d=zohomail.com; s=zohoarc; b=GduugC4TNyt1e8iaj2k7y01xTdOqCkFbEWYnbKoAHw+Px4MQQ+BjHtfMB6KUQ48YnT+ujf2CrT7oOO792atL58TVqs6Giwve/6FRYBuODpddbjGheYUzJzruay3qrPX/GHcSAKwIE6K2QlPMRblalx+IleJY4Vei5VeJEnTJo3Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654634429; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ReHRR17phjztnIWJ+KLGspDttklUzkMcS8o12wYY8cA=; b=A3Y3lan0m0CpVHzkUQBCDwQBFY+yw5C0xR9is0INAjeAR2xCP0GxRV93pMtCZ6TrJBnHa4JuBgO7ReraYll4lFs3q6z14fgjGdDdwmapvZ6sYSqDQyuqUDKOsF9I8PZZ2FKYLFgdl+z4mBmgsXh5ZoUnNMo1rsM8SHjKeFrUFtk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654634429124841.5966035594038; Tue, 7 Jun 2022 13:40:29 -0700 (PDT) Received: from localhost ([::1]:58250 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyg02-0003Hh-Us for importer@patchew.org; Tue, 07 Jun 2022 16:40:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33570) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftD-0007WL-TS for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:23 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:44594) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyft7-0007ES-AV for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:23 -0400 Received: by mail-pf1-x42c.google.com with SMTP id g205so16481156pfb.11 for ; Tue, 07 Jun 2022 13:33:16 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ReHRR17phjztnIWJ+KLGspDttklUzkMcS8o12wYY8cA=; b=e9BN7/xSLuPtXuL6vRHjV9as0GFq/GnZODWXpriRnrJm3RvSAsqX9AdN8nZTIHxB+C DJ5LfEsRqjkCGIZ29Qoj8GEKwIvVcUbV8Eh9lqbIW4tE1zdpjNnJAbxi3RjN1JwofBft Tz9lZF+IwOIbawWLp88v8Xtc2pC20y+tx3+HfBvVjfm3zWRmmIFvNSGVw+lWI56B4K10 9fWOCzW88C6CumY6yK3MW504OkZT8ffKjbKdVG51lvYRzNDqe6nKa3PHksjZrJVHEnOE actxDmItbH/BF0XO2XMJVi3LQJd4VipkRForI2JcrwwykY1v2+wP/Mmotqu4RL+d/VrL LEbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ReHRR17phjztnIWJ+KLGspDttklUzkMcS8o12wYY8cA=; b=bhZDj/sWcQk2xglF9JQWcX3CUIZ+zhIrbzPFF1q7VB0MaxcwpK4IMUHHldf2DOpq1a meUjU0UroPAwjHk+p00aFL815ALyCwCN6sD+Nv6I2fHJzMeb1/iE2AzlegHCMa+U8N2x xhXSlKJUvPWC+bhtAxJyXzP6GCT7mElDMGZWyykZ4tLXojk1vNiS6TyE2FGJ2GMYwfj4 VrD0/iqw2YTwBDCLw9pf3m5YGtx+zsf9tJhb/vecsPWEf4BpCSHLQ66dY2vE8cl+/pfW zsq4SPU3ukU8Jgzly0FetPbqotXCpSKTPylJzmnr9W9VmPiC0c34GviXr3fQNSS0/OEg Q7bA== X-Gm-Message-State: AOAM5315nW4+vVYMSSanKLsEnEzA/uKrguRFhHIlEJrmJSZdHzQdhtqO K4K+wfkr95xz0rFv4oe3Q35Uwv9cMgvw/w== X-Google-Smtp-Source: ABdhPJxskzb4R4jqRczQOeTeZj4MKxm+IkXKCJjQbcxo5LCEX/WpLiI0oKFuVAu+JPPAkqubGETy9Q== X-Received: by 2002:a63:5607:0:b0:3fc:910a:15e9 with SMTP id k7-20020a635607000000b003fc910a15e9mr26964535pgb.553.1654633994692; Tue, 07 Jun 2022 13:33:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 08/71] target/arm: Hoist arm_is_el2_enabled check in sve_exception_el Date: Tue, 7 Jun 2022 13:32:03 -0700 Message-Id: <20220607203306.657998-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654634430860100001 Content-Type: text/plain; charset="utf-8" This check is buried within arm_hcr_el2_eff(), but since we have to have the explicit check for CPTR_EL2.TZ, we might as well just check it once at the beginning of the block. Once this is done, we can test HCR_EL2.{E2H,TGE} directly, rather than going through arm_hcr_el2_eff(). Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7319c91fc2..dc8f1e44cc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6193,15 +6193,12 @@ int sve_exception_el(CPUARMState *env, int el) } } =20 - /* - * CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). - */ - if (el <=3D 2) { - uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); - if (hcr_el2 & HCR_E2H) { + if (el <=3D 2 && arm_is_el2_enabled(env)) { + /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */ + if (env->cp15.hcr_el2 & HCR_E2H) { switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, ZEN)) { case 1: - if (el !=3D 0 || !(hcr_el2 & HCR_TGE)) { + if (el !=3D 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { break; } /* fall through */ @@ -6209,7 +6206,7 @@ int sve_exception_el(CPUARMState *env, int el) case 2: return 2; } - } else if (arm_is_el2_enabled(env)) { + } else { if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) { return 2; } --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654634482; cv=none; d=zohomail.com; s=zohoarc; b=PX+5fAh7+gk8kJ++bawrzjGNAniqHokMbbg0fsVTVBL/Rk3bZg+13Huk5pX3CdWKXY+huGIErSrzKpBjOoJJKeF2YdS7XUiio92nuXrTU0aKdeRUyEOTn7zGb1KGw5iBF7PmPQAGpSz+JiH0QTYNGbQxt3OkzkdzLGdK8Sz7YZw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654634482; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3ImGeL35V1VptULMhKWxD6rBwxNJOjwQ4O8lIdXg7Ns=; b=YtrHVnh6bgCqox9Nqdhmw+fyYb4Bnc16hmV1MXvj6IdJ1HEy72avl8yU9UMapn+CgNLZZKiU2JigfnNXNyC5fdFpgaPZaOQYHODg5SM057sIrctjs6bJgPw8SBJ4582efxn2ftZiM/AlZcZGva/KcB+U4i06iB/3nN/3T0NPVJ4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165463448287625.116919583490017; Tue, 7 Jun 2022 13:41:22 -0700 (PDT) Received: from localhost ([::1]:34206 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyg0v-0006A4-DN for importer@patchew.org; Tue, 07 Jun 2022 16:41:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33504) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftC-0007Sv-NG for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:22 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:39876) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyft6-0007Er-Sv for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:22 -0400 Received: by mail-pj1-x1029.google.com with SMTP id q12-20020a17090a304c00b001e2d4fb0eb4so21871585pjl.4 for ; Tue, 07 Jun 2022 13:33:16 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3ImGeL35V1VptULMhKWxD6rBwxNJOjwQ4O8lIdXg7Ns=; b=hHsUQU11WBe7700oxpE76yF0K/G5HxsqeHGCcIv/qwNA4vrOltJYMAdqTJaNFnxUpB utbkimkUsAkmRarwyNcEME+3jK/J4p3+4dx4kXXiKOIXYUgOggTGLmiIHL8ou4qLH4yo I+2uXi1r7YDNsZo8UguXcxWwIxTXHg9ZMlK9TrWh1xGH1MxCtxfejHyhd0ZW20g3u9J7 Ts0fyo4cNhSVLWSrq7GxaKI7W3uwS2RS+ECyeOEs5QdFPD+Q1FZjVwjUv895obkRf8M8 iYQDrY7X6C+MPaHIg7FLotSjKKN8jC00b7ygVJiyjHyoW/QofzmSJcuLIrDnukUpOYIB m7qQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3ImGeL35V1VptULMhKWxD6rBwxNJOjwQ4O8lIdXg7Ns=; b=HIXlXR4gREGbocAbc2vinc4IwDLdsRiqFZNdsfzPeDlqXgvyXHWuLER+AtHloMAMUz PhnX1alqNCyxaifUACinkmkhMb8JfSEKNe5SldDpNCIIqnskM2rAghkUA2cAXkVuq0rC 9YuN0IRbfOGKVl1Y6lllTz82bgvK4em2YY7peZ+b35slOo0g83JYPeBrsSPL6UjvB+vQ pUyDycRFq6cgq5UOnS4Uh3pjz2QmCECDnrjMtKwZDPL6q82QX90m5ZXOJOLJEG+ihO3b b0GR2/7GDzLqIvg/0B0/7kTBVxhPd7NMGsPmoHqZaKE+fGfYlLPThUTtXt23wNmkBEit VkAA== X-Gm-Message-State: AOAM532kZUZ7+xWJ5Shc5V/k3f/VnTPA9GHAGk+i1+4Fu25gogHdbcqm ASc/+b3ChAUDL9kygNh3HOQ6/V2jp+8Sog== X-Google-Smtp-Source: ABdhPJxqE0xUJ6udg8jpCx2ncX1eAmr0rJ/7RUNnquYKdPEXM2VHaRBfYzjtb5Ui+3Bp28qUufg2TA== X-Received: by 2002:a17:902:b7c3:b0:167:7ca8:7f24 with SMTP id v3-20020a170902b7c300b001677ca87f24mr12468733plz.51.1654633995537; Tue, 07 Jun 2022 13:33:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 09/71] target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset Date: Tue, 7 Jun 2022 13:32:04 -0700 Message-Id: <20220607203306.657998-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654634485010100001 Content-Type: text/plain; charset="utf-8" We don't need to constrain the value set in zcr_el[1], because it will be done by sve_zcr_len_for_el. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d2bd74c2ed..0621944167 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -208,8 +208,7 @@ static void arm_cpu_reset(DeviceState *dev) CPACR_EL1, ZEN, 3); /* with reasonable vector length */ if (cpu_isar_feature(aa64_sve, cpu)) { - env->vfp.zcr_el[1] =3D - aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1= ); + env->vfp.zcr_el[1] =3D cpu->sve_default_vq - 1; } /* * Enable 48-bit address space (TODO: take reserved_va into accoun= t). --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654634596; cv=none; d=zohomail.com; s=zohoarc; b=eZpaQtRRYqNyCWsNmxBIxnuzc9sOK2ZJ+36QjDPs8H5LGQb/SCoZPA1z86wXsj+oknvz0bYm/dgyLqhDQAjrYSjhe2WTTSoJFgBuvV5GjTAbfsa4ffsY+CF2+shjVdHLgzWA/Wb+z9jMYrcjarFy2CcLt1NAjA3o6eN+YLF2MKE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654634596; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EhwnwnXu9GaRLFDW69ulBLl+dTP5VjSTIg+Z3UagrI0=; b=jSR6HAvXTngel6+y1r62PM9m8LaMjDw/2kOtw0p/IE07JTMdk9y+E2+G+Ldz8/MLIrgYVqNgNsYpbI5RxRbI12AL54g5jIXhn/RzkjFNtefId8egumlprlkNczbToTSV+40xtAwcnYsR4auuuxoHsFnTD/IvAlFtR+L6119Gvco= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654634596080771.6791889346669; Tue, 7 Jun 2022 13:43:16 -0700 (PDT) Received: from localhost ([::1]:39042 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyg2l-0000yj-0Q for importer@patchew.org; Tue, 07 Jun 2022 16:43:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33580) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftE-0007XY-6D for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:24 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:46976) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyft8-0007Bp-AX for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:23 -0400 Received: by mail-pj1-x1034.google.com with SMTP id k5-20020a17090a404500b001e8875e6242so5675467pjg.5 for ; Tue, 07 Jun 2022 13:33:16 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EhwnwnXu9GaRLFDW69ulBLl+dTP5VjSTIg+Z3UagrI0=; b=MAEY0El3J2InYhXJ6z4X6UcWp8e2SvknuCG/v5Y12gGflLdDCfgNnadpTQZVfPxsny SXBz+ejJVrbrEXTOVCmIUurbreh8Q8qD8a7wzqMhR6NCeP88wdjyNLPkdRE7zZJCb0uH +bmWrmt7kU3vrjh7GZqjTEaqGDKXS6xXUFJMExgDWF9n5aVbBCaLC1kg8l/to4hMIMSb DfPVS2OB+EzBku7bdoZKhAL9f6dR1pZm4qqonuMemRsI6kSbVHGXZOM17UnFFfTPsGCZ TwvHWdnodSfPKjlwg1VfydmqlhVhMeSRHsm5p4ns4INXj0NpgaEJnSdC2adED5miT/rT yDSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EhwnwnXu9GaRLFDW69ulBLl+dTP5VjSTIg+Z3UagrI0=; b=cYMzDMuf9zKauZ83BA2ir+R/KlAm5Eqzt/ktT8jl0sjuHOnEir4XXzPsRotVkZpZxN NKkfvK1H8A5/J6BLfSYlYKQRUZhOkRSSE1qyjZ2R0uLO7p7nm7D+0yjKSdZHcc9l0WIV ZXY7mek/p0o03bk++Yj3PPw9KNo4HCh4ML46vkM+uiohGR06SVt9V+0/qsEirzR2gpHS T29R20tS1nww5iXPojZw2/1Gr8Ll7CTviWgGqeVbIK3TnEjZHTuTd8GF0r0ZVuRc6erQ 278Dk637elKvgNO1lFEdxqNo/irgCPMG2O7p0S/wkZlFN0fBD06C1FpGNHW1dpO0s3ov xEmw== X-Gm-Message-State: AOAM533tXqegavr+PJfwTmtIGf55AwILLgSSbjoBS95/GUgQS5r7QBmv +RJ5qzrw0iYQlLMBBcYRmqf/97r5IDkF9g== X-Google-Smtp-Source: ABdhPJx4PHToLzlNoYedpqWjvd0Tzlq35hC3JGnAeckWG7LRQ1FGax//FWB9jjBY3QD/6NVwKMP4Xg== X-Received: by 2002:a17:90b:4c84:b0:1e8:6bea:d278 with SMTP id my4-20020a17090b4c8400b001e86bead278mr16853882pjb.232.1654633996489; Tue, 07 Jun 2022 13:33:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 10/71] target/arm: Merge aarch64_sve_zcr_get_valid_len into caller Date: Tue, 7 Jun 2022 13:32:05 -0700 Message-Id: <20220607203306.657998-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654634597735100003 Content-Type: text/plain; charset="utf-8" This function is used only once, and will need modification for Streaming SVE mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 11 ----------- target/arm/helper.c | 30 +++++++++++------------------- 2 files changed, 11 insertions(+), 30 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a73f2a94c5..4dcdca918b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -189,17 +189,6 @@ void arm_translate_init(void); void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); #endif /* CONFIG_TCG */ =20 -/** - * aarch64_sve_zcr_get_valid_len: - * @cpu: cpu context - * @start_len: maximum len to consider - * - * Return the maximum supported sve vector length <=3D @start_len. - * Note that both @start_len and the return value are in units - * of ZCR_ELx.LEN, so the vector bit length is (x + 1) * 128. - */ -uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len); - enum arm_fprounding { FPROUNDING_TIEEVEN, FPROUNDING_POSINF, diff --git a/target/arm/helper.c b/target/arm/helper.c index dc8f1e44cc..e84d30e5fc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6222,39 +6222,31 @@ int sve_exception_el(CPUARMState *env, int el) return 0; } =20 -uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) -{ - uint32_t end_len; - - start_len =3D MIN(start_len, ARM_MAX_VQ - 1); - end_len =3D start_len; - - if (!test_bit(start_len, cpu->sve_vq_map)) { - end_len =3D find_last_bit(cpu->sve_vq_map, start_len); - assert(end_len < start_len); - } - return end_len; -} - /* * Given that SVE is enabled, return the vector length for EL. */ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) { ARMCPU *cpu =3D env_archcpu(env); - uint32_t zcr_len =3D cpu->sve_max_vq - 1; + uint32_t len =3D cpu->sve_max_vq - 1; + uint32_t end_len; =20 if (el <=3D 1 && !el_is_in_host(env, el)) { - zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); + len =3D MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[1]); } if (el <=3D 2 && arm_feature(env, ARM_FEATURE_EL2)) { - zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); + len =3D MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[2]); } if (arm_feature(env, ARM_FEATURE_EL3)) { - zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); + len =3D MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[3]); } =20 - return aarch64_sve_zcr_get_valid_len(cpu, zcr_len); + end_len =3D len; + if (!test_bit(len, cpu->sve_vq_map)) { + end_len =3D find_last_bit(cpu->sve_vq_map, len); + assert(end_len < len); + } + return end_len; } =20 static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654634818; cv=none; d=zohomail.com; s=zohoarc; b=LxBVdpNuiV7yuDv8Qfd59v89A9QDj0EkHFssGWYZi3SwSymHtibfqHuSltUvFc9u9Y3ewbo/jXFxvR1vy+J0hovzlN9D/q5HvWzrVHtqnERxUuUqYCj0Au9RE9bWXxl0i28CMDAlMw0gxOtEgB7TZFLS4EuJO0sn2caIpc5rcCk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654634818; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=e+EIDfNbUcN+Xaxk1a6EU67mm/0DRFn6xA5ZwUcefR0=; b=IbbkVMU/INfEimfxuHyE9Mu+NsqN5q6bQv86CJfAtC6SReB8jA3wfce4DNMw/l0fNCtsvWYwQOIhbmHlsFdGuRUwhz4PTv1ew5B0n4u/kixOtOpF+ed/s+1s/WX5Pp+kAgVbm0ayBgy3HV+elTjT4T2ds6EmA6S0B8paSFZX224= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654634818909616.8550030270666; Tue, 7 Jun 2022 13:46:58 -0700 (PDT) Received: from localhost ([::1]:47692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyg6L-00073o-Ap for importer@patchew.org; Tue, 07 Jun 2022 16:46:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33696) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftH-0007gP-72 for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:27 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:41596) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftA-0007FU-Eg for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:26 -0400 Received: by mail-pg1-x536.google.com with SMTP id e66so16931125pgc.8 for ; Tue, 07 Jun 2022 13:33:18 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e+EIDfNbUcN+Xaxk1a6EU67mm/0DRFn6xA5ZwUcefR0=; b=vPlICZXgJ+hCScXngliIXn7x1EAhXP/ZxM9qkCBBdpGgO+NgYqN6euR42T/5WlWdu7 VS4dmbjjmhDkt9W/YAVstqHdPpvK0jCPPMAMMHAi7oUon3NLXM0419b/Yf0dTA6F7ju1 Eh9MYpMuM0n4gcboQuRNV/Wwiba6II7gUqPW8ce+Obljjmx3xK/qL1lEHKWQE+LtICBl Ot8rOM+Q88d9iA3XuyaHy5xtOjdGnPpOGwFaSRxfCsEg23Z/hC9ZJGHkHEg0xgJ8FZJ4 s1tBM3mxpOadjxOVTbG6026KjH/7Idw4n/MmTOcZyKEcQkFMiFh6B794ZWurMDNaz/bL oCzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e+EIDfNbUcN+Xaxk1a6EU67mm/0DRFn6xA5ZwUcefR0=; b=Xl/kjp65pC55bP2Ieyv1obsqmOjVybCjGfSZFAJ29MXk64wk8Yk95lbjT8vXr58288 ZEMy0dJ+EA1bYH/mWqPw4t2FoUJjxn+hwWs5T3NpRKEU7sG869eaWXSbsjZLPi7Hc+oa TFJmqlngp0yzWqoLEq9zFii3Oen168hbiT5k30t8w3DWSzjn01MpC1FUEkyikm7H86AI 09cZP+xUBoJTlPL+278wF7KCR0zsHGZJuTfkd7Qx6SCZZQ/1awjzdL7zoDNzvCFdeMKV FKG152biND0v+xJsdGw65q1EpzcH8vki9VfQ57DU//QeBLFxFmiAC/zbpOjQo4MSKJvT s8dA== X-Gm-Message-State: AOAM53399U/0Za+pBL2UmjzseVcq3ZDjPN8+MkdBNaECJeERRl9OkvID XcQZuvvPTQb3YdkiZLBKoj7+SW0PhQby0Q== X-Google-Smtp-Source: ABdhPJzNMN1KEFd3ixMx8OrEdK0b+oT0hWW01fwYnhIGPn0bqnCjyeX1nUkux4QUtEnEg9z3fiQSPg== X-Received: by 2002:a63:f011:0:b0:3fb:c86f:821e with SMTP id k17-20020a63f011000000b003fbc86f821emr27656543pgh.217.1654633997456; Tue, 07 Jun 2022 13:33:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 11/71] target/arm: Use uint32_t instead of bitmap for sve vq's Date: Tue, 7 Jun 2022 13:32:06 -0700 Message-Id: <20220607203306.657998-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654634819341100001 Content-Type: text/plain; charset="utf-8" The bitmap need only hold 15 bits; bitmap is over-complicated. We can simplify operations quite a bit with plain logical ops. The introduction of SVE_VQ_POW2_MAP eliminates the need for looping in order to search for powers of two. Simply perform the logical ops and use count leading or trailing zeros as required to find the result. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 +-- target/arm/internals.h | 5 ++ target/arm/kvm_arm.h | 7 ++- target/arm/cpu64.c | 117 ++++++++++++++++++++--------------------- target/arm/helper.c | 9 +--- target/arm/kvm64.c | 36 +++---------- 6 files changed, 75 insertions(+), 105 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6e35e30000..4ec2daec2a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1041,9 +1041,9 @@ struct ArchCPU { * Bits set in sve_vq_supported represent valid vector lengths for * the CPU type. */ - DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); - DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); - DECLARE_BITMAP(sve_vq_supported, ARM_MAX_VQ); + uint32_t sve_vq_map; + uint32_t sve_vq_init; + uint32_t sve_vq_supported; =20 /* Generic timer counter frequency, in Hz */ uint64_t gt_cntfrq_hz; diff --git a/target/arm/internals.h b/target/arm/internals.h index 4dcdca918b..8bac570475 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1321,4 +1321,9 @@ bool el_is_in_host(CPUARMState *env, int el); =20 void aa32_max_features(ARMCPU *cpu); =20 +/* Powers of 2 for sve_vq_map et al. */ +#define SVE_VQ_POW2_MAP \ + ((1 << (1 - 1)) | (1 << (2 - 1)) | \ + (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1))) + #endif diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index b7f78b5215..99017b635c 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -239,13 +239,12 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures= *ahcf); /** * kvm_arm_sve_get_vls: * @cs: CPUState - * @map: bitmap to fill in * * Get all the SVE vector lengths supported by the KVM host, setting * the bits corresponding to their length in quadwords minus one - * (vq - 1) in @map up to ARM_MAX_VQ. + * (vq - 1) up to ARM_MAX_VQ. Return the resulting map. */ -void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map); +uint32_t kvm_arm_sve_get_vls(CPUState *cs); =20 /** * kvm_arm_set_cpu_features_from_host: @@ -439,7 +438,7 @@ static inline void kvm_arm_steal_time_finalize(ARMCPU *= cpu, Error **errp) g_assert_not_reached(); } =20 -static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) +static inline uint32_t kvm_arm_sve_get_vls(CPUState *cs) { g_assert_not_reached(); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3ff9219ca3..51c5d8d4bc 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -355,8 +355,11 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * any of the above. Finally, if SVE is not disabled, then at least o= ne * vector length must be enabled. */ - DECLARE_BITMAP(tmp, ARM_MAX_VQ); - uint32_t vq, max_vq =3D 0; + uint32_t vq_map =3D cpu->sve_vq_map; + uint32_t vq_init =3D cpu->sve_vq_init; + uint32_t vq_supported; + uint32_t vq_mask =3D 0; + uint32_t tmp, vq, max_vq =3D 0; =20 /* * CPU models specify a set of supported vector lengths which are @@ -364,10 +367,16 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * in the supported bitmap results in an error. When KVM is enabled we * fetch the supported bitmap from the host. */ - if (kvm_enabled() && kvm_arm_sve_supported()) { - kvm_arm_sve_get_vls(CPU(cpu), cpu->sve_vq_supported); - } else if (kvm_enabled()) { - assert(!cpu_isar_feature(aa64_sve, cpu)); + if (kvm_enabled()) { + if (kvm_arm_sve_supported()) { + cpu->sve_vq_supported =3D kvm_arm_sve_get_vls(CPU(cpu)); + vq_supported =3D cpu->sve_vq_supported; + } else { + assert(!cpu_isar_feature(aa64_sve, cpu)); + vq_supported =3D 0; + } + } else { + vq_supported =3D cpu->sve_vq_supported; } =20 /* @@ -375,8 +384,9 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * From the properties, sve_vq_map implies sve_vq_init. * Check first for any sve enabled. */ - if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) { - max_vq =3D find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1; + if (vq_map !=3D 0) { + max_vq =3D 32 - clz32(vq_map); + vq_mask =3D MAKE_64BIT_MASK(0, max_vq); =20 if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { error_setg(errp, "cannot enable sve%d", max_vq * 128); @@ -392,15 +402,10 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * For KVM we have to automatically enable all supported uniti= alized * lengths, even when the smaller lengths are not all powers-o= f-two. */ - bitmap_andnot(tmp, cpu->sve_vq_supported, cpu->sve_vq_init, ma= x_vq); - bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); + vq_map |=3D vq_supported & ~vq_init & vq_mask; } else { /* Propagate enabled bits down through required powers-of-two.= */ - for (vq =3D pow2floor(max_vq); vq >=3D 1; vq >>=3D 1) { - if (!test_bit(vq - 1, cpu->sve_vq_init)) { - set_bit(vq - 1, cpu->sve_vq_map); - } - } + vq_map |=3D SVE_VQ_POW2_MAP & ~vq_init & vq_mask; } } else if (cpu->sve_max_vq =3D=3D 0) { /* @@ -413,25 +418,18 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) =20 if (kvm_enabled()) { /* Disabling a supported length disables all larger lengths. */ - for (vq =3D 1; vq <=3D ARM_MAX_VQ; ++vq) { - if (test_bit(vq - 1, cpu->sve_vq_init) && - test_bit(vq - 1, cpu->sve_vq_supported)) { - break; - } - } + tmp =3D vq_init & vq_supported; } else { /* Disabling a power-of-two disables all larger lengths. */ - for (vq =3D 1; vq <=3D ARM_MAX_VQ; vq <<=3D 1) { - if (test_bit(vq - 1, cpu->sve_vq_init)) { - break; - } - } + tmp =3D vq_init & SVE_VQ_POW2_MAP; } + vq =3D ctz32(tmp) + 1; =20 max_vq =3D vq <=3D ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; - bitmap_andnot(cpu->sve_vq_map, cpu->sve_vq_supported, - cpu->sve_vq_init, max_vq); - if (max_vq =3D=3D 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) { + vq_mask =3D MAKE_64BIT_MASK(0, max_vq); + vq_map =3D vq_supported & ~vq_init & vq_mask; + + if (max_vq =3D=3D 0 || vq_map =3D=3D 0) { error_setg(errp, "cannot disable sve%d", vq * 128); error_append_hint(errp, "Disabling sve%d results in all " "vector lengths being disabled.\n", @@ -441,7 +439,8 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) return; } =20 - max_vq =3D find_last_bit(cpu->sve_vq_map, max_vq) + 1; + max_vq =3D 32 - clz32(vq_map); + vq_mask =3D MAKE_64BIT_MASK(0, max_vq); } =20 /* @@ -451,9 +450,9 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) */ if (cpu->sve_max_vq !=3D 0) { max_vq =3D cpu->sve_max_vq; + vq_mask =3D MAKE_64BIT_MASK(0, max_vq); =20 - if (!test_bit(max_vq - 1, cpu->sve_vq_map) && - test_bit(max_vq - 1, cpu->sve_vq_init)) { + if (vq_init & ~vq_map & (1 << (max_vq - 1))) { error_setg(errp, "cannot disable sve%d", max_vq * 128); error_append_hint(errp, "The maximum vector length must be " "enabled, sve-max-vq=3D%d (%d bits)\n", @@ -462,8 +461,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) } =20 /* Set all bits not explicitly set within sve-max-vq. */ - bitmap_complement(tmp, cpu->sve_vq_init, max_vq); - bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); + vq_map |=3D ~vq_init & vq_mask; } =20 /* @@ -472,13 +470,14 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * are clear, just in case anybody looks. */ assert(max_vq !=3D 0); - bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq); + assert(vq_mask !=3D 0); + vq_map &=3D vq_mask; =20 /* Ensure the set of lengths matches what is supported. */ - bitmap_xor(tmp, cpu->sve_vq_map, cpu->sve_vq_supported, max_vq); - if (!bitmap_empty(tmp, max_vq)) { - vq =3D find_last_bit(tmp, max_vq) + 1; - if (test_bit(vq - 1, cpu->sve_vq_map)) { + tmp =3D vq_map ^ (vq_supported & vq_mask); + if (tmp) { + vq =3D 32 - clz32(tmp); + if (vq_map & (1 << (vq - 1))) { if (cpu->sve_max_vq) { error_setg(errp, "cannot set sve-max-vq=3D%d", cpu->sve_ma= x_vq); error_append_hint(errp, "This CPU does not support " @@ -502,15 +501,15 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) return; } else { /* Ensure all required powers-of-two are enabled. */ - for (vq =3D pow2floor(max_vq); vq >=3D 1; vq >>=3D 1) { - if (!test_bit(vq - 1, cpu->sve_vq_map)) { - error_setg(errp, "cannot disable sve%d", vq * 128); - error_append_hint(errp, "sve%d is required as it " - "is a power-of-two length smalle= r " - "than the maximum, sve%d\n", - vq * 128, max_vq * 128); - return; - } + tmp =3D SVE_VQ_POW2_MAP & vq_mask & ~vq_map; + if (tmp) { + vq =3D 32 - clz32(tmp); + error_setg(errp, "cannot disable sve%d", vq * 128); + error_append_hint(errp, "sve%d is required as it " + "is a power-of-two length smaller " + "than the maximum, sve%d\n", + vq * 128, max_vq * 128); + return; } } } @@ -530,6 +529,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) =20 /* From now on sve_max_vq is the actual maximum supported length. */ cpu->sve_max_vq =3D max_vq; + cpu->sve_vq_map =3D vq_map; } =20 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *na= me, @@ -590,7 +590,7 @@ static void cpu_arm_get_sve_vq(Object *obj, Visitor *v,= const char *name, if (!cpu_isar_feature(aa64_sve, cpu)) { value =3D false; } else { - value =3D test_bit(vq - 1, cpu->sve_vq_map); + value =3D extract32(cpu->sve_vq_map, vq - 1, 1); } visit_type_bool(v, name, &value, errp); } @@ -612,12 +612,8 @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v= , const char *name, return; } =20 - if (value) { - set_bit(vq - 1, cpu->sve_vq_map); - } else { - clear_bit(vq - 1, cpu->sve_vq_map); - } - set_bit(vq - 1, cpu->sve_vq_init); + cpu->sve_vq_map =3D deposit32(cpu->sve_vq_map, vq - 1, 1, value); + cpu->sve_vq_init |=3D 1 << (vq - 1); } =20 static bool cpu_arm_get_sve(Object *obj, Error **errp) @@ -978,7 +974,7 @@ static void aarch64_max_initfn(Object *obj) cpu->dcz_blocksize =3D 7; /* 512 bytes */ #endif =20 - bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ); + cpu->sve_vq_supported =3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); =20 aarch64_add_pauth_properties(obj); aarch64_add_sve_properties(obj); @@ -1025,12 +1021,11 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->gic_vprebits =3D 5; cpu->gic_pribits =3D 5; =20 - /* Suppport of A64FX's vector length are 128,256 and 512bit only */ + /* The A64FX supports only 128, 256 and 512 bit vector lengths */ aarch64_add_sve_properties(obj); - bitmap_zero(cpu->sve_vq_supported, ARM_MAX_VQ); - set_bit(0, cpu->sve_vq_supported); /* 128bit */ - set_bit(1, cpu->sve_vq_supported); /* 256bit */ - set_bit(3, cpu->sve_vq_supported); /* 512bit */ + cpu->sve_vq_supported =3D (1 << 0) /* 128bit */ + | (1 << 1) /* 256bit */ + | (1 << 3); /* 512bit */ =20 cpu->isar.reset_pmcr_el0 =3D 0x46014040; =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index e84d30e5fc..7b6f31e9c8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6229,7 +6229,6 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) { ARMCPU *cpu =3D env_archcpu(env); uint32_t len =3D cpu->sve_max_vq - 1; - uint32_t end_len; =20 if (el <=3D 1 && !el_is_in_host(env, el)) { len =3D MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[1]); @@ -6241,12 +6240,8 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) len =3D MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[3]); } =20 - end_len =3D len; - if (!test_bit(len, cpu->sve_vq_map)) { - end_len =3D find_last_bit(cpu->sve_vq_map, len); - assert(end_len < len); - } - return end_len; + len =3D 31 - clz32(cpu->sve_vq_map & MAKE_64BIT_MASK(0, len + 1)); + return len; } =20 static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 363032da90..b3f635fc95 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -760,15 +760,13 @@ bool kvm_arm_steal_time_supported(void) =20 QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN !=3D 1); =20 -void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) +uint32_t kvm_arm_sve_get_vls(CPUState *cs) { /* Only call this function if kvm_arm_sve_supported() returns true. */ static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; static bool probed; uint32_t vq =3D 0; - int i, j; - - bitmap_zero(map, ARM_MAX_VQ); + int i; =20 /* * KVM ensures all host CPUs support the same set of vector lengths. @@ -809,46 +807,24 @@ void kvm_arm_sve_get_vls(CPUState *cs, unsigned long = *map) if (vq > ARM_MAX_VQ) { warn_report("KVM supports vector lengths larger than " "QEMU can enable"); + vls[0] &=3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); } } =20 - for (i =3D 0; i < KVM_ARM64_SVE_VLS_WORDS; ++i) { - if (!vls[i]) { - continue; - } - for (j =3D 1; j <=3D 64; ++j) { - vq =3D j + i * 64; - if (vq > ARM_MAX_VQ) { - return; - } - if (vls[i] & (1UL << (j - 1))) { - set_bit(vq - 1, map); - } - } - } + return vls[0]; } =20 static int kvm_arm_sve_set_vls(CPUState *cs) { - uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] =3D {0}; + ARMCPU *cpu =3D ARM_CPU(cs); + uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] =3D { cpu->sve_vq_map }; struct kvm_one_reg reg =3D { .id =3D KVM_REG_ARM64_SVE_VLS, .addr =3D (uint64_t)&vls[0], }; - ARMCPU *cpu =3D ARM_CPU(cs); - uint32_t vq; - int i, j; =20 assert(cpu->sve_max_vq <=3D KVM_ARM64_SVE_VQ_MAX); =20 - for (vq =3D 1; vq <=3D cpu->sve_max_vq; ++vq) { - if (test_bit(vq - 1, cpu->sve_vq_map)) { - i =3D (vq - 1) / 64; - j =3D (vq - 1) % 64; - vls[i] |=3D 1UL << j; - } - } - return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); } =20 --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654634707; cv=none; d=zohomail.com; s=zohoarc; b=VPdgtPHhjak4a+8IjcO7d2H6fLhZzPyrMJg/3rRh8hg8oYCTtg9wrxcNqQfBMgFv/tl3duGgjMOUIXWp7EPzXYxvhLINS6Mp+Ec+hWZpEpJvy8NioVn5rTsQkO2li4xNwAGwbYkIaBEKQMUNyX2MnTG1860DxHifCbjUUlt8qjg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654634707; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1lEZUH/ogWVZdNv0ca1wSpWH+sIL1KbkILIib8NO3cE=; b=RBURz8yY+JXWmgs5LI0t6iMxs3GV47TihDPYJN2wdFiQBHrOyJHXwnVf4OQrD7LyFB sBCoTOxXypv5reSUS0X/XcFdHYSoSM0gxyTBVg/AZ+mYE7HyFlL0VoPz2YPror4E6x75 +z+bAbNkJplqUBm0NJy/aZ7x0jycUFki6wnZjoKREvP5aFlrFaIQORONB/OyjR0+izkV YoY9jDTQ/YOSOa4WSNuSEVFYbNmAuMVSg5pfziUuj6aIO+N/InUJcl733+s54PJnZLcV 3+g5msB/wFtlBdLn6ECLTAbcclJmBu0oM/5TE/47uZAMymlJ78llbrttUzmT7kgzLX4X 706w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1lEZUH/ogWVZdNv0ca1wSpWH+sIL1KbkILIib8NO3cE=; b=N5WsPdFlPd4VAzN5836vuPbnvcgrHzOIKoEVhfHoYPUnStqLYYdOHNAZWMieF4wLGV M9ldtVn7wt3KNF7USTCiLDPvFEswpzLS9cIBgxX4VIfCXNraDlnTzwM60f6NHJMyhuKK m71IJ+JhJMA05v0e/Eor+kiHTtRnJDYUoNvq9naIUH60eZpnfvpMCD3PhJAY0WeKd/k/ cHvo50VG1HGKJ0D27IYMZXvcLC3pHGkjTRNNwx89J3Giq1cF6li/WYxAyyXfp4PqibAx 6XNjltqpXlfhgLiH5scaccV/NMerfnALRD6C5a9qoWog0Ua6QNg8yXjfiYugxekFKDgE bUaA== X-Gm-Message-State: AOAM5315oSZgkb1U5SzUdx9s4jBKPgGffgqfrsgrUwkRVtE1ZThOkq0f 2Q23BkstgZqtkpwHknghdyMKu5mxullLvw== X-Google-Smtp-Source: ABdhPJwVf7087rlgW2KRUD0GnjDpphfk1BnnrMQtguR+z/Y4FIZOsYOIimNQ06Zlp2ec133hxC+n2Q== X-Received: by 2002:a17:902:ab8c:b0:167:4d5c:3542 with SMTP id f12-20020a170902ab8c00b001674d5c3542mr22520763plr.6.1654633998493; Tue, 07 Jun 2022 13:33:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 12/71] target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el Date: Tue, 7 Jun 2022 13:32:07 -0700 Message-Id: <20220607203306.657998-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654634708712100001 Content-Type: text/plain; charset="utf-8" This will be used for both Normal and Streaming SVE, and the value does not necessarily come from ZCR_ELx. While we're at it, emphasize the units in which the value is returned. Patch produced by git grep -l sve_zcr_len_for_el | \ xargs -n1 sed -i 's/sve_zcr_len_for_el/sve_vqm1_for_el/g' and then adding a function comment. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 11 ++++++++++- target/arm/arch_dump.c | 2 +- target/arm/cpu.c | 2 +- target/arm/gdbstub64.c | 2 +- target/arm/helper.c | 12 ++++++------ 5 files changed, 19 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4ec2daec2a..2cc28f9e59 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1132,7 +1132,16 @@ void aarch64_sync_64_to_32(CPUARMState *env); =20 int fp_exception_el(CPUARMState *env, int cur_el); int sve_exception_el(CPUARMState *env, int cur_el); -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); + +/** + * sve_vqm1_for_el: + * @env: CPUARMState + * @el: exception level + * + * Compute the current SVE vector length for @el, in units of + * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. + */ +uint32_t sve_vqm1_for_el(CPUARMState *env, int el); =20 static inline bool is_a64(CPUARMState *env) { diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 0184845310..b1f040e69f 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -166,7 +166,7 @@ static off_t sve_fpcr_offset(uint32_t vq) =20 static uint32_t sve_current_vq(CPUARMState *env) { - return sve_zcr_len_for_el(env, arm_current_el(env)) + 1; + return sve_vqm1_for_el(env, arm_current_el(env)) + 1; } =20 static size_t sve_size_vq(uint32_t vq) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0621944167..1b5d535788 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -925,7 +925,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *= f, int flags) vfp_get_fpcr(env), vfp_get_fpsr(env)); =20 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) =3D= =3D 0) { - int j, zcr_len =3D sve_zcr_len_for_el(env, el); + int j, zcr_len =3D sve_vqm1_for_el(env, el); =20 for (i =3D 0; i <=3D FFR_PRED_NUM; i++) { bool eol; diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 596878666d..07a6746944 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -152,7 +152,7 @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *bu= f, int reg) * We report in Vector Granules (VG) which is 64bit in a Z reg * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. */ - int vq =3D sve_zcr_len_for_el(env, arm_current_el(env)) + 1; + int vq =3D sve_vqm1_for_el(env, arm_current_el(env)) + 1; return gdb_get_reg64(buf, vq * 2); } default: diff --git a/target/arm/helper.c b/target/arm/helper.c index 7b6f31e9c8..cb44d528c0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6225,7 +6225,7 @@ int sve_exception_el(CPUARMState *env, int el) /* * Given that SVE is enabled, return the vector length for EL. */ -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) +uint32_t sve_vqm1_for_el(CPUARMState *env, int el) { ARMCPU *cpu =3D env_archcpu(env); uint32_t len =3D cpu->sve_max_vq - 1; @@ -6248,7 +6248,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) { int cur_el =3D arm_current_el(env); - int old_len =3D sve_zcr_len_for_el(env, cur_el); + int old_len =3D sve_vqm1_for_el(env, cur_el); int new_len; =20 /* Bits other than [3:0] are RAZ/WI. */ @@ -6259,7 +6259,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, * Because we arrived here, we know both FP and SVE are enabled; * otherwise we would have trapped access to the ZCR_ELn register. */ - new_len =3D sve_zcr_len_for_el(env, cur_el); + new_len =3D sve_vqm1_for_el(env, cur_el); if (new_len < old_len) { aarch64_sve_narrow_vq(env, new_len + 1); } @@ -13683,7 +13683,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState= *env, int el, int fp_el, sve_el =3D 0; } } else if (sve_el =3D=3D 0) { - DP_TBFLAG_A64(flags, VL, sve_zcr_len_for_el(env, el)); + DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el)); } DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); } @@ -14049,10 +14049,10 @@ void aarch64_sve_change_el(CPUARMState *env, int = old_el, */ old_a64 =3D old_el ? arm_el_is_aa64(env, old_el) : el0_a64; old_len =3D (old_a64 && !sve_exception_el(env, old_el) - ? sve_zcr_len_for_el(env, old_el) : 0); + ? sve_vqm1_for_el(env, old_el) : 0); new_a64 =3D new_el ? arm_el_is_aa64(env, new_el) : el0_a64; new_len =3D (new_a64 && !sve_exception_el(env, new_el) - ? sve_zcr_len_for_el(env, new_el) : 0); + ? sve_vqm1_for_el(env, new_el) : 0); =20 /* When changing vector length, clear inaccessible state. */ if (new_len < old_len) { --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654634580; cv=none; d=zohomail.com; s=zohoarc; b=Xp/JuL7xXEWnCVfTqtZXxb6B2Xm/3pxkiegRfqP3PmiwJY6hzSLSKYOC/4WXNPXatmF9m+YbXsL86wFApkiZzoGIK1OgUSrpLfMNw7XgjJeBV2pirDQwDk3jVlXang7N3+3UFRta27+BJ5JYpJ84orFTdF3kt8hMIJmRsS8Jrkg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654634580; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=F4rHpbD5Ee0Gqq7jh/rhx4dfJgd9LnpoppwR09o1CsY=; b=nFv7lvsjogT/qEmTmfIrCwmk22lBLONcj49ZP1Ngw93JjzgufjsVBQ1ZqIkIuCSmzr7jxnY/hbuqb/wIu8ewFRbrC5HTJS2S8XDHCVeMJ0r5UyLDoLvyaims+/eNEIR6U68TuVlYUNLAOxp7S5/baHVt0hZVfb+9GW2nX4S3iDU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654634580885490.011224776968; Tue, 7 Jun 2022 13:43:00 -0700 (PDT) Received: from localhost ([::1]:37850 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyg2V-00009G-Pf for importer@patchew.org; Tue, 07 Jun 2022 16:42:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33698) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftH-0007gX-7P for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:27 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:33267) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftB-0007Fu-CG for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:26 -0400 Received: by mail-pj1-x1031.google.com with SMTP id hv24-20020a17090ae41800b001e33eebdb5dso14595086pjb.0 for ; Tue, 07 Jun 2022 13:33:20 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F4rHpbD5Ee0Gqq7jh/rhx4dfJgd9LnpoppwR09o1CsY=; b=tdMBZUC2+4GoI7c+aGmgfzgEQf+8lUH9yat8svm0wK6ChLFtKKZLTQwh043JhUNrzI TEfZ2jeQVIUPbVJq7GhJ5PkOSN33XkXiFwsx1SCFvXlA3Shex6aaoA00cJ55TlttIwYB oa9BcRuLTAOkNPt+kyUpIqK3F+n6sqX3HkA2A9ngMsgazNAtCGfeZKHdPiCfKsZLUmj3 WCAOJ9poMcsK/D+jjIvH3Y/7i7kPOt3vozNkEIO0VQtWD2lQ9CwizU6sdE7f6XMvz+z0 JDhjMZ0xdsz9EfUe4ofE8lBEJBQaFMo7y61Q/ldlca8qw7N61bqKPr7bbxhVHb5yDo+P 72cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F4rHpbD5Ee0Gqq7jh/rhx4dfJgd9LnpoppwR09o1CsY=; b=a2T6VXVIf2n1pOCOopbbq+JpKG+VFc6jvXMZYGSaPqb3Rlig33Qmn+tGidfZwdQQ75 f5ryAY8jPocLG7G8x/ODaFa7hmhQkrGgeUJ+dzhY2Wf9mk7Vf0Vz0p/ojDWlC5UuPm45 9t1lnI3uQC3THAU6sLxGs1geJ4dHGQRnd2zLt+ElKqrl4bBG/zLbtti8K8MR6z6se9nV Bi5hPu3M5n1zOHLpaeUaHniVFkrThHcF9u2MspjyvJOq1xP8XuilUmTi04DIwhmK5N8A W0lvBN9Fukac3jKBATtyttaKmx2JEMmE5Tk1qLHMMz38MaX7bJHvSZJlQ1pJWEn9A8hT gn+A== X-Gm-Message-State: AOAM530XHlLo4U2Gw+mAufkfFRAQIP6kL0lOiTszB8s8p9LX3bQZPCzh twPQpz8zm8+aTh9G8/lArXFFenxRfHi4LQ== X-Google-Smtp-Source: ABdhPJxY/FjjnU6bTlKiO/ZoDAuuAjzlCgHa781qIvFPUrvvucunU7mzRtcdOUnarT9u7I9ZGrrIaQ== X-Received: by 2002:a17:903:1c8:b0:167:67ff:323d with SMTP id e8-20020a17090301c800b0016767ff323dmr17055776plh.22.1654633999510; Tue, 07 Jun 2022 13:33:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 13/71] target/arm: Split out load/store primitives to sve_ldst_internal.h Date: Tue, 7 Jun 2022 13:32:08 -0700 Message-Id: <20220607203306.657998-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654634581623100001 Content-Type: text/plain; charset="utf-8" Begin creation of sve_ldst_internal.h by moving the primitives that access host and tlb memory. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve_ldst_internal.h | 127 +++++++++++++++++++++++++++++++++ target/arm/sve_helper.c | 107 +-------------------------- 2 files changed, 128 insertions(+), 106 deletions(-) create mode 100644 target/arm/sve_ldst_internal.h diff --git a/target/arm/sve_ldst_internal.h b/target/arm/sve_ldst_internal.h new file mode 100644 index 0000000000..ef9117e84c --- /dev/null +++ b/target/arm/sve_ldst_internal.h @@ -0,0 +1,127 @@ +/* + * ARM SVE Load/Store Helpers + * + * Copyright (c) 2018-2022 Linaro + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARM_SVE_LDST_INTERNAL_H +#define TARGET_ARM_SVE_LDST_INTERNAL_H + +#include "exec/cpu_ldst.h" + +/* + * Load one element into @vd + @reg_off from @host. + * The controlling predicate is known to be true. + */ +typedef void sve_ldst1_host_fn(void *vd, intptr_t reg_off, void *host); + +/* + * Load one element into @vd + @reg_off from (@env, @vaddr, @ra). + * The controlling predicate is known to be true. + */ +typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off, + target_ulong vaddr, uintptr_t retaddr); + +/* + * Generate the above primitives. + */ + +#define DO_LD_HOST(NAME, H, TYPEE, TYPEM, HOST) = \ +static inline void sve_##NAME##_host(void *vd, intptr_t reg_off, void *hos= t) \ +{ TYPEM val =3D HOST(host); *(TYPEE *)(vd + H(reg_off)) =3D val; } + +#define DO_ST_HOST(NAME, H, TYPEE, TYPEM, HOST) = \ +static inline void sve_##NAME##_host(void *vd, intptr_t reg_off, void *hos= t) \ +{ TYPEM val =3D *(TYPEE *)(vd + H(reg_off)); HOST(host, val); } + +#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) = \ +static inline void sve_##NAME##_tlb(CPUARMState *env, void *vd, = \ + intptr_t reg_off, target_ulong addr, uintptr_t ra)= \ +{ = \ + TYPEM val =3D TLB(env, useronly_clean_ptr(addr), ra); = \ + *(TYPEE *)(vd + H(reg_off)) =3D val; = \ +} + +#define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) = \ +static inline void sve_##NAME##_tlb(CPUARMState *env, void *vd, = \ + intptr_t reg_off, target_ulong addr, uintptr_t ra)= \ +{ = \ + TYPEM val =3D *(TYPEE *)(vd + H(reg_off)); = \ + TLB(env, useronly_clean_ptr(addr), val, ra); = \ +} + +#define DO_LD_PRIM_1(NAME, H, TE, TM) \ + DO_LD_HOST(NAME, H, TE, TM, ldub_p) \ + DO_LD_TLB(NAME, H, TE, TM, cpu_ldub_data_ra) + +DO_LD_PRIM_1(ld1bb, H1, uint8_t, uint8_t) +DO_LD_PRIM_1(ld1bhu, H1_2, uint16_t, uint8_t) +DO_LD_PRIM_1(ld1bhs, H1_2, uint16_t, int8_t) +DO_LD_PRIM_1(ld1bsu, H1_4, uint32_t, uint8_t) +DO_LD_PRIM_1(ld1bss, H1_4, uint32_t, int8_t) +DO_LD_PRIM_1(ld1bdu, H1_8, uint64_t, uint8_t) +DO_LD_PRIM_1(ld1bds, H1_8, uint64_t, int8_t) + +#define DO_ST_PRIM_1(NAME, H, TE, TM) \ + DO_ST_HOST(st1##NAME, H, TE, TM, stb_p) \ + DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra) + +DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t) +DO_ST_PRIM_1(bh, H1_2, uint16_t, uint8_t) +DO_ST_PRIM_1(bs, H1_4, uint32_t, uint8_t) +DO_ST_PRIM_1(bd, H1_8, uint64_t, uint8_t) + +#define DO_LD_PRIM_2(NAME, H, TE, TM, LD) \ + DO_LD_HOST(ld1##NAME##_be, H, TE, TM, LD##_be_p) \ + DO_LD_HOST(ld1##NAME##_le, H, TE, TM, LD##_le_p) \ + DO_LD_TLB(ld1##NAME##_be, H, TE, TM, cpu_##LD##_be_data_ra) \ + DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra) + +#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \ + DO_ST_HOST(st1##NAME##_be, H, TE, TM, ST##_be_p) \ + DO_ST_HOST(st1##NAME##_le, H, TE, TM, ST##_le_p) \ + DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \ + DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra) + +DO_LD_PRIM_2(hh, H1_2, uint16_t, uint16_t, lduw) +DO_LD_PRIM_2(hsu, H1_4, uint32_t, uint16_t, lduw) +DO_LD_PRIM_2(hss, H1_4, uint32_t, int16_t, lduw) +DO_LD_PRIM_2(hdu, H1_8, uint64_t, uint16_t, lduw) +DO_LD_PRIM_2(hds, H1_8, uint64_t, int16_t, lduw) + +DO_ST_PRIM_2(hh, H1_2, uint16_t, uint16_t, stw) +DO_ST_PRIM_2(hs, H1_4, uint32_t, uint16_t, stw) +DO_ST_PRIM_2(hd, H1_8, uint64_t, uint16_t, stw) + +DO_LD_PRIM_2(ss, H1_4, uint32_t, uint32_t, ldl) +DO_LD_PRIM_2(sdu, H1_8, uint64_t, uint32_t, ldl) +DO_LD_PRIM_2(sds, H1_8, uint64_t, int32_t, ldl) + +DO_ST_PRIM_2(ss, H1_4, uint32_t, uint32_t, stl) +DO_ST_PRIM_2(sd, H1_8, uint64_t, uint32_t, stl) + +DO_LD_PRIM_2(dd, H1_8, uint64_t, uint64_t, ldq) +DO_ST_PRIM_2(dd, H1_8, uint64_t, uint64_t, stq) + +#undef DO_LD_TLB +#undef DO_ST_TLB +#undef DO_LD_HOST +#undef DO_LD_PRIM_1 +#undef DO_ST_PRIM_1 +#undef DO_LD_PRIM_2 +#undef DO_ST_PRIM_2 + +#endif /* TARGET_ARM_SVE_LDST_INTERNAL_H */ diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 3bdcd4ce9d..0c6dde00aa 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -21,12 +21,12 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "tcg/tcg.h" #include "vec_internal.h" +#include "sve_ldst_internal.h" =20 =20 /* Return a value for NZCV as per the ARM PredTest pseudofunction. @@ -5301,111 +5301,6 @@ void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, = void *vm, void *va, * Load contiguous data, protected by a governing predicate. */ =20 -/* - * Load one element into @vd + @reg_off from @host. - * The controlling predicate is known to be true. - */ -typedef void sve_ldst1_host_fn(void *vd, intptr_t reg_off, void *host); - -/* - * Load one element into @vd + @reg_off from (@env, @vaddr, @ra). - * The controlling predicate is known to be true. - */ -typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off, - target_ulong vaddr, uintptr_t retaddr); - -/* - * Generate the above primitives. - */ - -#define DO_LD_HOST(NAME, H, TYPEE, TYPEM, HOST) \ -static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \ -{ \ - TYPEM val =3D HOST(host); \ - *(TYPEE *)(vd + H(reg_off)) =3D val; \ -} - -#define DO_ST_HOST(NAME, H, TYPEE, TYPEM, HOST) \ -static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \ -{ HOST(host, (TYPEM)*(TYPEE *)(vd + H(reg_off))); } - -#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \ -static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off,= \ - target_ulong addr, uintptr_t ra) = \ -{ = \ - *(TYPEE *)(vd + H(reg_off)) =3D = \ - (TYPEM)TLB(env, useronly_clean_ptr(addr), ra); = \ -} - -#define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \ -static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off,= \ - target_ulong addr, uintptr_t ra) = \ -{ = \ - TLB(env, useronly_clean_ptr(addr), = \ - (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); = \ -} - -#define DO_LD_PRIM_1(NAME, H, TE, TM) \ - DO_LD_HOST(NAME, H, TE, TM, ldub_p) \ - DO_LD_TLB(NAME, H, TE, TM, cpu_ldub_data_ra) - -DO_LD_PRIM_1(ld1bb, H1, uint8_t, uint8_t) -DO_LD_PRIM_1(ld1bhu, H1_2, uint16_t, uint8_t) -DO_LD_PRIM_1(ld1bhs, H1_2, uint16_t, int8_t) -DO_LD_PRIM_1(ld1bsu, H1_4, uint32_t, uint8_t) -DO_LD_PRIM_1(ld1bss, H1_4, uint32_t, int8_t) -DO_LD_PRIM_1(ld1bdu, H1_8, uint64_t, uint8_t) -DO_LD_PRIM_1(ld1bds, H1_8, uint64_t, int8_t) - -#define DO_ST_PRIM_1(NAME, H, TE, TM) \ - DO_ST_HOST(st1##NAME, H, TE, TM, stb_p) \ - DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra) - -DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t) -DO_ST_PRIM_1(bh, H1_2, uint16_t, uint8_t) -DO_ST_PRIM_1(bs, H1_4, uint32_t, uint8_t) -DO_ST_PRIM_1(bd, H1_8, uint64_t, uint8_t) - -#define DO_LD_PRIM_2(NAME, H, TE, TM, LD) \ - DO_LD_HOST(ld1##NAME##_be, H, TE, TM, LD##_be_p) \ - DO_LD_HOST(ld1##NAME##_le, H, TE, TM, LD##_le_p) \ - DO_LD_TLB(ld1##NAME##_be, H, TE, TM, cpu_##LD##_be_data_ra) \ - DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra) - -#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \ - DO_ST_HOST(st1##NAME##_be, H, TE, TM, ST##_be_p) \ - DO_ST_HOST(st1##NAME##_le, H, TE, TM, ST##_le_p) \ - DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \ - DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra) - -DO_LD_PRIM_2(hh, H1_2, uint16_t, uint16_t, lduw) -DO_LD_PRIM_2(hsu, H1_4, uint32_t, uint16_t, lduw) -DO_LD_PRIM_2(hss, H1_4, uint32_t, int16_t, lduw) -DO_LD_PRIM_2(hdu, H1_8, uint64_t, uint16_t, lduw) -DO_LD_PRIM_2(hds, H1_8, uint64_t, int16_t, lduw) - -DO_ST_PRIM_2(hh, H1_2, uint16_t, uint16_t, stw) -DO_ST_PRIM_2(hs, H1_4, uint32_t, uint16_t, stw) -DO_ST_PRIM_2(hd, H1_8, uint64_t, uint16_t, stw) - -DO_LD_PRIM_2(ss, H1_4, uint32_t, uint32_t, ldl) -DO_LD_PRIM_2(sdu, H1_8, uint64_t, uint32_t, ldl) -DO_LD_PRIM_2(sds, H1_8, uint64_t, int32_t, ldl) - -DO_ST_PRIM_2(ss, H1_4, uint32_t, uint32_t, stl) -DO_ST_PRIM_2(sd, H1_8, uint64_t, uint32_t, stl) - -DO_LD_PRIM_2(dd, H1_8, uint64_t, uint64_t, ldq) -DO_ST_PRIM_2(dd, H1_8, uint64_t, uint64_t, stq) - -#undef DO_LD_TLB -#undef DO_ST_TLB -#undef DO_LD_HOST -#undef DO_LD_PRIM_1 -#undef DO_ST_PRIM_1 -#undef DO_LD_PRIM_2 -#undef DO_ST_PRIM_2 - /* * Skip through a sequence of inactive elements in the guarding predicate = @vg, * beginning at @reg_off bounded by @reg_max. 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([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jaTWEUo9dEcM6jmweyaOFnw3wtRMGNYyznA/W1CTYmM=; b=mgkASMsfiHCqjdCcYtfukBtYmdOfi0ed97QuMWkvpF7oBXVOrexiZekGG7v/06Cw7J 3TOQnfHPNLqrUOtSXg1m5vWH5ikxHdvVCymwySZUp8tXUWuF+NNc2wqIzzYj4GwJP90v 3XwHhx8Fo3rSyJaakwC7AaOyoFDsVLhVZrr77+VxtL7rPf4Y9oSsKffLcfC3Lthl1ykj UUBOYlG0nLHWhHjgnDna94p9PZiQ+NGuu18KBdT1L27B5o9Gc6AV1vcFFDc9k7uxuWWE u3QsWArXYyBvxuH2wb/rLshamaZee6HDezDBJsOvCZV9JbqYo6pOMsPPSG3Pk+bdWIv6 hh0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jaTWEUo9dEcM6jmweyaOFnw3wtRMGNYyznA/W1CTYmM=; b=1f6z2K1LXgDg9mRL1dVUZ29Pv/pO4G/Pj2yexMjFVPE97Jea2B8pehcUKleiw7D1Rm Tb6MIZX+1xWpH0BhgOysWNkQMvowUJqwogVWrUQHklrb0mpOY07PlAhixbpuO+7h5oB8 O1eM8/pHE6odSTKAz8J3WIJYSP0qFbZMJ+KGjZnBWkfBScLSHbuo35k0X+YEibvuyFWW XtGo4trjUugK5bC2tdb6QOATgKsfZglNvMqQNPrBZWxSf038gOg+2wwV8GkUknzM/s7J 5I/KdE08aFoQ7wM6g8HgWqJEandefuBhYu5llJbyVngwPyTzn6rrGLGZAwOrnAORCrY+ 1THw== X-Gm-Message-State: AOAM530wv3dwiCeJ78VH6IOkEuSikt0Qxt/16Euw1CB2Vq/VkPQ0bq+c zYYKQtjfyP/GD5qPIFS28Hlet4vmbBUPuA== X-Google-Smtp-Source: ABdhPJyC5BslkU1osfldgjfB/BxZ593/8Ed9dCTlecqBrcX2rkPEyO144yNk9zoMGhh9sR3gPs1GEA== X-Received: by 2002:a17:902:f68b:b0:163:f358:d4ad with SMTP id l11-20020a170902f68b00b00163f358d4admr31175379plg.23.1654634000395; Tue, 07 Jun 2022 13:33:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 14/71] target/arm: Export sve contiguous ldst support functions Date: Tue, 7 Jun 2022 13:32:09 -0700 Message-Id: <20220607203306.657998-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654634992371100001 Content-Type: text/plain; charset="utf-8" Export all of the support functions for performing bulk fault analysis on a set of elements at contiguous addresses controlled by a predicate. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve_ldst_internal.h | 94 ++++++++++++++++++++++++++++++++++ target/arm/sve_helper.c | 87 ++++++------------------------- 2 files changed, 111 insertions(+), 70 deletions(-) diff --git a/target/arm/sve_ldst_internal.h b/target/arm/sve_ldst_internal.h index ef9117e84c..b5c473fc48 100644 --- a/target/arm/sve_ldst_internal.h +++ b/target/arm/sve_ldst_internal.h @@ -124,4 +124,98 @@ DO_ST_PRIM_2(dd, H1_8, uint64_t, uint64_t, stq) #undef DO_LD_PRIM_2 #undef DO_ST_PRIM_2 =20 +/* + * Resolve the guest virtual address to info->host and info->flags. + * If @nofault, return false if the page is invalid, otherwise + * exit via page fault exception. + */ + +typedef struct { + void *host; + int flags; + MemTxAttrs attrs; +} SVEHostPage; + +bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env, + target_ulong addr, int mem_off, MMUAccessType access_t= ype, + int mmu_idx, uintptr_t retaddr); + +/* + * Analyse contiguous data, protected by a governing predicate. + */ + +typedef enum { + FAULT_NO, + FAULT_FIRST, + FAULT_ALL, +} SVEContFault; + +typedef struct { + /* + * First and last element wholly contained within the two pages. + * mem_off_first[0] and reg_off_first[0] are always set >=3D 0. + * reg_off_last[0] may be < 0 if the first element crosses pages. + * All of mem_off_first[1], reg_off_first[1] and reg_off_last[1] + * are set >=3D 0 only if there are complete elements on a second page. + * + * The reg_off_* offsets are relative to the internal vector register. + * The mem_off_first offset is relative to the memory address; the + * two offsets are different when a load operation extends, a store + * operation truncates, or for multi-register operations. + */ + int16_t mem_off_first[2]; + int16_t reg_off_first[2]; + int16_t reg_off_last[2]; + + /* + * One element that is misaligned and spans both pages, + * or -1 if there is no such active element. + */ + int16_t mem_off_split; + int16_t reg_off_split; + + /* + * The byte offset at which the entire operation crosses a page bounda= ry. + * Set >=3D 0 if and only if the entire operation spans two pages. + */ + int16_t page_split; + + /* TLB data for the two pages. */ + SVEHostPage page[2]; +} SVEContLdSt; + +/* + * Find first active element on each page, and a loose bound for the + * final element on each page. Identify any single element that spans + * the page boundary. Return true if there are any active elements. + */ +bool sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t= *vg, + intptr_t reg_max, int esz, int msize); + +/* + * Resolve the guest virtual addresses to info->page[]. + * Control the generation of page faults with @fault. Return false if + * there is no work to do, which can only happen with @fault =3D=3D FAULT_= NO. + */ +bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, + CPUARMState *env, target_ulong addr, + MMUAccessType access_type, uintptr_t retaddr); + +#ifdef CONFIG_USER_ONLY +static inline void +sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env, uint64_t *v= g, + target_ulong addr, int esize, int msize, + int wp_access, uintptr_t retaddr) +{ } +#else +void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env, + uint64_t *vg, target_ulong addr, + int esize, int msize, int wp_access, + uintptr_t retaddr); +#endif + +void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUARMState *env, uint64_t= *vg, + target_ulong addr, int esize, int msize, + uint32_t mtedesc, uintptr_t ra); + #endif /* TARGET_ARM_SVE_LDST_INTERNAL_H */ diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 0c6dde00aa..8cd371e3e3 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -5341,16 +5341,9 @@ static intptr_t find_next_active(uint64_t *vg, intpt= r_t reg_off, * exit via page fault exception. */ =20 -typedef struct { - void *host; - int flags; - MemTxAttrs attrs; -} SVEHostPage; - -static bool sve_probe_page(SVEHostPage *info, bool nofault, - CPUARMState *env, target_ulong addr, - int mem_off, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env, + target_ulong addr, int mem_off, MMUAccessType access_t= ype, + int mmu_idx, uintptr_t retaddr) { int flags; =20 @@ -5406,59 +5399,13 @@ static bool sve_probe_page(SVEHostPage *info, bool = nofault, return true; } =20 - -/* - * Analyse contiguous data, protected by a governing predicate. - */ - -typedef enum { - FAULT_NO, - FAULT_FIRST, - FAULT_ALL, -} SVEContFault; - -typedef struct { - /* - * First and last element wholly contained within the two pages. - * mem_off_first[0] and reg_off_first[0] are always set >=3D 0. - * reg_off_last[0] may be < 0 if the first element crosses pages. - * All of mem_off_first[1], reg_off_first[1] and reg_off_last[1] - * are set >=3D 0 only if there are complete elements on a second page. - * - * The reg_off_* offsets are relative to the internal vector register. - * The mem_off_first offset is relative to the memory address; the - * two offsets are different when a load operation extends, a store - * operation truncates, or for multi-register operations. - */ - int16_t mem_off_first[2]; - int16_t reg_off_first[2]; - int16_t reg_off_last[2]; - - /* - * One element that is misaligned and spans both pages, - * or -1 if there is no such active element. - */ - int16_t mem_off_split; - int16_t reg_off_split; - - /* - * The byte offset at which the entire operation crosses a page bounda= ry. - * Set >=3D 0 if and only if the entire operation spans two pages. - */ - int16_t page_split; - - /* TLB data for the two pages. */ - SVEHostPage page[2]; -} SVEContLdSt; - /* * Find first active element on each page, and a loose bound for the * final element on each page. Identify any single element that spans * the page boundary. Return true if there are any active elements. */ -static bool sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, - uint64_t *vg, intptr_t reg_max, - int esz, int msize) +bool sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t= *vg, + intptr_t reg_max, int esz, int msize) { const int esize =3D 1 << esz; const uint64_t pg_mask =3D pred_esz_masks[esz]; @@ -5548,9 +5495,9 @@ static bool sve_cont_ldst_elements(SVEContLdSt *info,= target_ulong addr, * Control the generation of page faults with @fault. Return false if * there is no work to do, which can only happen with @fault =3D=3D FAULT_= NO. */ -static bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, - CPUARMState *env, target_ulong addr, - MMUAccessType access_type, uintptr_t retad= dr) +bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, + CPUARMState *env, target_ulong addr, + MMUAccessType access_type, uintptr_t retaddr) { int mmu_idx =3D cpu_mmu_index(env, false); int mem_off =3D info->mem_off_first[0]; @@ -5606,12 +5553,12 @@ static bool sve_cont_ldst_pages(SVEContLdSt *info, = SVEContFault fault, return have_work; } =20 -static void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env, - uint64_t *vg, target_ulong addr, - int esize, int msize, int wp_access, - uintptr_t retaddr) -{ #ifndef CONFIG_USER_ONLY +void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env, + uint64_t *vg, target_ulong addr, + int esize, int msize, int wp_access, + uintptr_t retaddr) +{ intptr_t mem_off, reg_off, reg_last; int flags0 =3D info->page[0].flags; int flags1 =3D info->page[1].flags; @@ -5667,12 +5614,12 @@ static void sve_cont_ldst_watchpoints(SVEContLdSt *= info, CPUARMState *env, } while (reg_off & 63); } while (reg_off <=3D reg_last); } -#endif } +#endif =20 -static void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUARMState *env, - uint64_t *vg, target_ulong addr, int e= size, - int msize, uint32_t mtedesc, uintptr_t= ra) +void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUARMState *env, + uint64_t *vg, target_ulong addr, int esize, + int msize, uint32_t mtedesc, uintptr_t ra) { intptr_t mem_off, reg_off, reg_last; =20 --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654634807; cv=none; d=zohomail.com; s=zohoarc; b=Vb1vtsdu0mDC3SCCVktMvKwR0hNaJBFk2cAEA/dmC+h235rirnjArH7jy102pftiKHsxdA5/WZ958hMa979wOGcOcdb+P7+rx2l3fzojTh9ZYw/XRM7TUz4Jzu/HBE9/x95cmnjCBPvfJzQW6IWguYOSRbTxH1yGSl5Z0usVog0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654634807; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XuOHiX6D0El6nNEd2Jyo7d9eF8KMwz8jltCon2kVgiU=; b=ItwI6MkDUrP4iUOmC6ERv52I0Gn1nJeFphyw3xxRlukMKWpkfbyOOuXf/eXM8XrKT2O7eeroeZj1XycDTZd5ztRsWEs10BAOB4TJnZFn0fmUQCQGeh40ViXA6oh1jxrID38NGa06CsCw6o7jaNLJ56bOglmSCxrMvYXnOqxMBXI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654634807207884.9351403808588; Tue, 7 Jun 2022 13:46:47 -0700 (PDT) Received: from localhost ([::1]:47384 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyg6A-0006pB-7D for importer@patchew.org; Tue, 07 Jun 2022 16:46:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33748) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftI-0007iF-A2 for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:28 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:33344) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftC-0007Gg-LF for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:28 -0400 Received: by mail-pg1-x536.google.com with SMTP id r71so16988908pgr.0 for ; Tue, 07 Jun 2022 13:33:22 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XuOHiX6D0El6nNEd2Jyo7d9eF8KMwz8jltCon2kVgiU=; b=D/XjMCoBvmoi3Y8yz06n6HoI3bvWJu1NyyF0QjauDdgBQR3uwfSMJw/9Ulq0ZdEp1C HpliPg+gkS5FW3+G9Jl88e+uB7Tx3QiLznz2qpMJx0VGj5LHmbWIy9E4w++ZBughogo8 yxtLnkFipApsltpMhw7ztx/P+UH9jXvhp3LCcdkNl0XgNUrHpEFeiMrdjnq4AzYXb+Nq ogKRHX04Howl2n+9JabQvohJ73VECvy4RBt+EBeW71vhHlsHsL4SF7jWPA8JZVvLD8rp FVhFnqNXIs/rd/TCNBF3JcINj60k0zXQ2uPV3vKZ8HEU1oX5vLGWnb+ffl93DPqlZzYs Xy9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XuOHiX6D0El6nNEd2Jyo7d9eF8KMwz8jltCon2kVgiU=; b=6QV8KbcoE1oGaei8lPPtxL9NmXfn7oYU4XEAdgHeQPPMKfLrPMqWj8WPAOfvH/pdz/ 7TJ3OHHg7r5DJopUUb6MV8ramjaIS+e/2ag9u77Xn+iHbY2vNb6DqlFfNfkC5nDCtYe2 mrcaj/SrWjTjIG2GbK9P61wB9FUb9KmEPXvHIoBg6fZaXjtBkTXGJUp4E83p2uuK2pPh AbWN2iCR6EoJDzBwlQtOTfsPa43Dn2yBKrYnVFKOxSTdqLsco2AJi5s5BN3OzUFKaE8Q f/s95F638J4oc5UnUSGtw71VbK05dCwNctSQiN34h/enYQ0+yO+sLhmYyRqMZOgYLUyy rLGA== X-Gm-Message-State: AOAM5319dOHE1MQbGEOO/7rcRNYquTQpIVTedoRgDpbHeE8f10usP9pb PgfbNQg2oqeQ15URHB6sBKmL+guqWVPMCA== X-Google-Smtp-Source: ABdhPJzci2wjVx7Tqh9qJ4vWB/9julWBRqWI44wLyGH/ajpXPCq+F0hlCzq/wpbzQF1JeJFMlUiP3g== X-Received: by 2002:a63:2d82:0:b0:3fd:fb59:d086 with SMTP id t124-20020a632d82000000b003fdfb59d086mr5019975pgt.334.1654634001343; Tue, 07 Jun 2022 13:33:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 15/71] target/arm: Move expand_pred_b to vec_internal.h Date: Tue, 7 Jun 2022 13:32:10 -0700 Message-Id: <20220607203306.657998-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654634809451100001 Content-Type: text/plain; charset="utf-8" Put the inline function near the array declaration. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/vec_internal.h | 8 +++++++- target/arm/sve_helper.c | 9 --------- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h index 1d63402042..d1a1ea4a66 100644 --- a/target/arm/vec_internal.h +++ b/target/arm/vec_internal.h @@ -50,8 +50,14 @@ #define H8(x) (x) #define H1_8(x) (x) =20 -/* Data for expanding active predicate bits to bytes, for byte elements. */ +/* + * Expand active predicate bits to bytes, for byte elements. + */ extern const uint64_t expand_pred_b_data[256]; +static inline uint64_t expand_pred_b(uint8_t byte) +{ + return expand_pred_b_data[byte]; +} =20 static inline void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) { diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 8cd371e3e3..e865c12527 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -103,15 +103,6 @@ uint32_t HELPER(sve_predtest)(void *vd, void *vg, uint= 32_t words) return flags; } =20 -/* - * Expand active predicate bits to bytes, for byte elements. - * (The data table itself is in vec_helper.c as MVE also needs it.) - */ -static inline uint64_t expand_pred_b(uint8_t byte) -{ - return expand_pred_b_data[byte]; -} - /* Similarly for half-word elements. * for (i =3D 0; i < 256; ++i) { * unsigned long m =3D 0; --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654635031; cv=none; d=zohomail.com; s=zohoarc; b=F+onN1UKD4gF6hc1Y8IF9Vg77FdRCffD3i/wpYHixSwB/E4cZz8PGeioqsZlmLcbhg7WXTDZv0Gj3pe9ysEyYhomBHWiMOiDLCYd+zrodlpt4c0B4gWHl/Qu6pYrj6POZ9KTSueUOEA0viqNoEsL9+pB4Qdh1ggUeRJVax93QsI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654635031; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OVdCbtqKJB+BGb16fkMGEP1znoVx5B0GA093B8K9G20=; b=h9HaFHsFcGODLQX0INa3gxXkHFd8pGfCrLhxE/vyHr1VO8Xbh2AyAqwBx0tu6NbGRiy9DBpwKOjtWc3bNEnIyWV+UXs5V9uxItPde/+KRVYOPQhzGHchZZLSVn5UP1ZQ+8zWFDlpPS6tippDaJTBVwNEcTkjkBuOCV8s/7RC9cA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654635031052617.9359453292669; Tue, 7 Jun 2022 13:50:31 -0700 (PDT) Received: from localhost ([::1]:57830 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyg9l-0005gl-UV for importer@patchew.org; Tue, 07 Jun 2022 16:50:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33850) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftK-0007mr-LN for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:30 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:42528) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftD-0007HM-Dy for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:30 -0400 Received: by mail-pl1-x631.google.com with SMTP id d22so15779427plr.9 for ; Tue, 07 Jun 2022 13:33:22 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OVdCbtqKJB+BGb16fkMGEP1znoVx5B0GA093B8K9G20=; b=mu92fmZFW7YpiAu2rsNYFPmj6eW/FkAnDyXoUJQ89YmLNE3BIkOXrLebH1Fc8Bm8C8 2QNSva+iExlPDk2cIbn4ye0e7g57X19c7u1qYqEt8lE2YjKjFlh0PWwBvegY0GJLVx7U 1EvP2wAA6z9i8s2l/uJ3V83ueS2jqqon71TN2F5c6My6B6SNUf4A8TWVJNwuppTE7HiF 3zaZiXh2Db3mPiTcuoZnTQphOAgWD4oyIhPjh0uK7P6nrAEN8l9b3bnWuv80vCe2kFd5 LZmVuxYO+HmXeZlcIl30HlEZkEdBH8Ju6sLM8jyMfcvDeVu4fiOFoglSQu72gQ2ltJFs 6XDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OVdCbtqKJB+BGb16fkMGEP1znoVx5B0GA093B8K9G20=; b=pn+1M429zMU0+v3MOM3ny1auvx7GwidTi85N7aYssDt5S5ZDYRLR7jM2uOm4ScA/TU hFfPUVF2XkJPziqrLtX68k/D89wxIc0vZu8K//cYOZwERRnhDWN2g1WkusYJhk+pwmNZ n6shbL4G2EB/UyRzmJJ0O8zgmsK0qk2ouwfzPqa0vBe4In+CTmdS4/bIvTjkkXkA8Mgs 1/x4HZw4vlH7gbPXXOfXzFVOMQeo2vGitnEN6BMzpLwTsjwqsme4dzj29R/Qf0XXV4LP u4KIyI0HmV5H9ZfYwbF6OEwUg8YjzYXnmmghaZpeRYsiE/lV2MreOgP2XHgtDalYu2mi 8D8w== X-Gm-Message-State: AOAM532/0X+famEmE2HTaylrW5wYGEIkfIiRj+uDUt3inH3Rulkfut3q Dj5/0EvhCTT7iXghZIKEAG34iz4cRkVtGQ== X-Google-Smtp-Source: ABdhPJwzWqiHR/PDkjglhNHDV2sg9WWjsVhLi7GfpMYSK5YB3DNZlSRo09dY4dv7fPZYc4Od4LaX+Q== X-Received: by 2002:a17:902:da8d:b0:165:7c1b:6803 with SMTP id j13-20020a170902da8d00b001657c1b6803mr30618586plx.157.1654634002145; Tue, 07 Jun 2022 13:33:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 16/71] target/arm: Use expand_pred_b in mve_helper.c Date: Tue, 7 Jun 2022 13:32:11 -0700 Message-Id: <20220607203306.657998-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654635032723100002 Content-Type: text/plain; charset="utf-8" Use the function instead of the array directly. Because the function performs its own masking, via the uint8_t parameter, we need to do nothing extra within the users: the bits above the first 2 (_uh) or 4 (_uw) will be discarded by assignment to the local bmask variables, and of course _uq uses the entire uint64_t result. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/mve_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 846962bf4c..403b345ea3 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -726,7 +726,7 @@ static void mergemask_sb(int8_t *d, int8_t r, uint16_t = mask) =20 static void mergemask_uh(uint16_t *d, uint16_t r, uint16_t mask) { - uint16_t bmask =3D expand_pred_b_data[mask & 3]; + uint16_t bmask =3D expand_pred_b(mask); *d =3D (*d & ~bmask) | (r & bmask); } =20 @@ -737,7 +737,7 @@ static void mergemask_sh(int16_t *d, int16_t r, uint16_= t mask) =20 static void mergemask_uw(uint32_t *d, uint32_t r, uint16_t mask) { - uint32_t bmask =3D expand_pred_b_data[mask & 0xf]; + uint32_t bmask =3D expand_pred_b(mask); *d =3D (*d & ~bmask) | (r & bmask); } =20 @@ -748,7 +748,7 @@ static void mergemask_sw(int32_t *d, int32_t r, uint16_= t mask) =20 static void mergemask_uq(uint64_t *d, uint64_t r, uint16_t mask) { - uint64_t bmask =3D expand_pred_b_data[mask & 0xff]; + uint64_t bmask =3D expand_pred_b(mask); *d =3D (*d & ~bmask) | (r & bmask); } =20 --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654635360; cv=none; d=zohomail.com; s=zohoarc; b=hWP6IV1sj53LAIxgqdszkU+D7fwfBW748t+cuLJAGsG9dAlcxV61CqJUM/czCJBpeLENGey2kx4roPHByrfxj41L+UXHhBHQw0V866PiWChZV/Pq/7L2vDF4bZSxTgmYwyCcWWqtVKx90B9QANx8xWPT82kfsoWXclTHi98YJe4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654635360; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lRGebQyqBWSguPRywmTvdJmhpPUXlvnLMmD10I0JmJc=; b=HSgw6RWXftaLuayd4fryHSYB+2Bfn6qOCvDnhURNU5Z47cZFcGVcCwH5Vc7cETPzu7EirChYIq/o3fU/pEkYu+4Z0W3lyE863bFhEA5YgEkhDhdCRvevc3EO6/OFHgM0c7XONgWa8u9CovdG47roR/py3LGuudJCg6hRPE1B/rI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654635360575571.0327477712765; Tue, 7 Jun 2022 13:56:00 -0700 (PDT) Received: from localhost ([::1]:37812 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygF5-0003iK-8y for importer@patchew.org; Tue, 07 Jun 2022 16:55:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33848) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftK-0007mq-KB for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:30 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:44580) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftE-0007Ib-EM for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:30 -0400 Received: by mail-pg1-x52c.google.com with SMTP id c18so8624792pgh.11 for ; Tue, 07 Jun 2022 13:33:23 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lRGebQyqBWSguPRywmTvdJmhpPUXlvnLMmD10I0JmJc=; b=njsjEDYZIdYXaH4KHNwLvVJ4Z/KS7gL8bkgcQrrOlH6KoF9XNgc53hAELH0UbCPLPQ wHpXzzogvzyPvZ3S/E/LMNQYWgPV9xyQP0XB8/WWJoUmqMWiLjukp4neXdlqQHbJsmaB L6TArS7eGpa2pa2pebjebA+QgANpMEF958Or6OZ/U466ihJJ2vTuZ0o81cLXzB/HUr3N eGwcBT/dWXjU2faEX+WudyhnTtWzhmBHRRET5i2w5Nx/LlR5NJtEn+mGUHDi0j5LkX0I 8+OfmEnL6jCajwaxJrkQkaKHKs4z4yrCAYFlgDdLaiL0dDTtHBHpwrLsSlHMmzaZEI/c WUDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lRGebQyqBWSguPRywmTvdJmhpPUXlvnLMmD10I0JmJc=; b=AMleJFXcI5njbZ3bSGBee9CF3nc2O+6oeqZ1OoHH0DrSJfzicsJ5/L5FEnJNkzu1XP R4T0w2urDzDi+SMZbcu7/9wzxQh3XEysPW2+0FFRJNqurCgZSeXR/fSdMRyChtL7Vhs8 LG9pVyR1zLU3LDqjA9c9k2+mYs1FQctz5hSGZoK7Je5ITf7c7QIo5d+NadwjtculsB/9 fmke5I+QJT/Dx/dEmL8Zzu1T6h1hXAqBfez/rVL9I4Max8WEMS/wp4xcROiYvVspZZuA 77tvmmmX4eenmM25YL4Z23jc53o5cVIsEtLh/1LD9WrUoSQ/Wjwcqydtj+xSmyR1ktDn H8jg== X-Gm-Message-State: AOAM533UoMdKUv36pXFTySIy0Jila5PCbCvfW+iTQc1uihnJoVD6kKfe /3YVabPj+T3X0QkwfUNdB2ULAlXqi0u/zw== X-Google-Smtp-Source: ABdhPJwV/RRjhxz7f/PfiuWaeF4boljpvDZyfMHRmILesOBnYVS0A17U6N7Chltxn5Bfz0VR7wZ2CA== X-Received: by 2002:a63:6901:0:b0:3f9:caa5:cffc with SMTP id e1-20020a636901000000b003f9caa5cffcmr27421380pgc.324.1654634003018; Tue, 07 Jun 2022 13:33:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 17/71] target/arm: Move expand_pred_h to vec_internal.h Date: Tue, 7 Jun 2022 13:32:12 -0700 Message-Id: <20220607203306.657998-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654635362832100001 Content-Type: text/plain; charset="utf-8" Move the data to vec_helper.c and the inline to vec_internal.h. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/vec_internal.h | 7 +++++++ target/arm/sve_helper.c | 29 ----------------------------- target/arm/vec_helper.c | 26 ++++++++++++++++++++++++++ 3 files changed, 33 insertions(+), 29 deletions(-) diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h index d1a1ea4a66..1d527fadac 100644 --- a/target/arm/vec_internal.h +++ b/target/arm/vec_internal.h @@ -59,6 +59,13 @@ static inline uint64_t expand_pred_b(uint8_t byte) return expand_pred_b_data[byte]; } =20 +/* Similarly for half-word elements. */ +extern const uint64_t expand_pred_h_data[0x55 + 1]; +static inline uint64_t expand_pred_h(uint8_t byte) +{ + return expand_pred_h_data[byte & 0x55]; +} + static inline void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) { uint64_t *d =3D vd + opr_sz; diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index e865c12527..1654c0bbf9 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -103,35 +103,6 @@ uint32_t HELPER(sve_predtest)(void *vd, void *vg, uint= 32_t words) return flags; } =20 -/* Similarly for half-word elements. - * for (i =3D 0; i < 256; ++i) { - * unsigned long m =3D 0; - * if (i & 0xaa) { - * continue; - * } - * for (j =3D 0; j < 8; j +=3D 2) { - * if ((i >> j) & 1) { - * m |=3D 0xfffful << (j << 3); - * } - * } - * printf("[0x%x] =3D 0x%016lx,\n", i, m); - * } - */ -static inline uint64_t expand_pred_h(uint8_t byte) -{ - static const uint64_t word[] =3D { - [0x01] =3D 0x000000000000ffff, [0x04] =3D 0x00000000ffff0000, - [0x05] =3D 0x00000000ffffffff, [0x10] =3D 0x0000ffff00000000, - [0x11] =3D 0x0000ffff0000ffff, [0x14] =3D 0x0000ffffffff0000, - [0x15] =3D 0x0000ffffffffffff, [0x40] =3D 0xffff000000000000, - [0x41] =3D 0xffff00000000ffff, [0x44] =3D 0xffff0000ffff0000, - [0x45] =3D 0xffff0000ffffffff, [0x50] =3D 0xffffffff00000000, - [0x51] =3D 0xffffffff0000ffff, [0x54] =3D 0xffffffffffff0000, - [0x55] =3D 0xffffffffffffffff, - }; - return word[byte & 0x55]; -} - /* Similarly for single word elements. */ static inline uint64_t expand_pred_s(uint8_t byte) { diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 17fb158362..26c373e522 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -127,6 +127,32 @@ const uint64_t expand_pred_b_data[256] =3D { 0xffffffffffffffff, }; =20 +/* + * Similarly for half-word elements. + * for (i =3D 0; i < 256; ++i) { + * unsigned long m =3D 0; + * if (i & 0xaa) { + * continue; + * } + * for (j =3D 0; j < 8; j +=3D 2) { + * if ((i >> j) & 1) { + * m |=3D 0xfffful << (j << 3); + * } + * } + * printf("[0x%x] =3D 0x%016lx,\n", i, m); + * } + */ +const uint64_t expand_pred_h_data[0x55 + 1] =3D { + [0x01] =3D 0x000000000000ffff, [0x04] =3D 0x00000000ffff0000, + [0x05] =3D 0x00000000ffffffff, [0x10] =3D 0x0000ffff00000000, + [0x11] =3D 0x0000ffff0000ffff, [0x14] =3D 0x0000ffffffff0000, + [0x15] =3D 0x0000ffffffffffff, [0x40] =3D 0xffff000000000000, + [0x41] =3D 0xffff00000000ffff, [0x44] =3D 0xffff0000ffff0000, + [0x45] =3D 0xffff0000ffffffff, [0x50] =3D 0xffffffff00000000, + [0x51] =3D 0xffffffff0000ffff, [0x54] =3D 0xffffffffffff0000, + [0x55] =3D 0xffffffffffffffff, +}; + /* Signed saturating rounding doubling multiply-accumulate high half, 8-bi= t */ int8_t do_sqrdmlah_b(int8_t src1, int8_t src2, int8_t src3, bool neg, bool round) --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gapMUzbWXEa1xXFszg2jbZqJLMbZQGkHBtGV0RlKTO8=; b=ydQEcJ8kR/nWHdKxUHvA1eS0cLEJux68nK0R87iL0PFiG7n7QFk9S9l0itLuX2T1/2 AWMm0ytL0I8Y5KtokC03ywP3To38aHqkgrRA92Rl94cgpiGybaB1WsjwTW1eoQh3R8zf 5Az2plQ5GnFHO8USy3h/zxtM9mzSTT1JeJ5iyz7WwGtZx4xB0HLQCRh38RlEblTRCIQ7 VC51k9yiw5Vy1kD3MovaTsZ6obeuBqhBHh2XmkFOiHqd3WYDrZx1Ayw8tUVtKFmcGJWS GcWTlcB3vHCG/sdLUv00mIc6TDgRGoCfVV60R5F4ICK3ibY29GP3DbYWq0xO5TJEg0th 5PDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gapMUzbWXEa1xXFszg2jbZqJLMbZQGkHBtGV0RlKTO8=; b=EDtKc8lY+/oAG3EOAgfwnq/hqJ9YI21iQwAdmYKHrBy47ZnztwoSe9Skc+vlrcaVSn W3sTyS3YATWETGeusTeOGROnjxZzC+9MAwTyCIqMfN3xXhVB1bhbTcpr4vr33+E6R/oK Wd01j7wzdTt4x69eSiu2MQSUXTCqVtRrTePIhQm72C+vurzvHY2O0elLQ3RTQh74Pudt l+31+U9TYPrZXeItrOgSHot9rQgMGv7VGDlMBvmefROemQOatM7GO1pQM+TQYksk7I4n A/UQDlYWxFqO3W4pGSj6U3kG7jm0BD/PjoGj9NS1ZkS2vCQEuWJSEdWHCBNY2KI6nOHI CwqA== X-Gm-Message-State: AOAM5338rIIOzN/Rg7I6GtYYaP2q5JaRbscmcLM2t9nd2AX6mxItTN5z gG+/WvkSqMj7+DEvEcoSXa9HO1qezJ2cpg== X-Google-Smtp-Source: ABdhPJwGmmd01dUbPx2ynmuFmiy69PW5ZaYT51kNaRkQYf90OWs5myFbBaYU9WYEwTPKvGKdDH0N0g== X-Received: by 2002:a63:6c81:0:b0:3fd:4be3:8ee9 with SMTP id h123-20020a636c81000000b003fd4be38ee9mr17866421pgc.188.1654634003931; Tue, 07 Jun 2022 13:33:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 18/71] target/arm: Export bfdotadd from vec_helper.c Date: Tue, 7 Jun 2022 13:32:13 -0700 Message-Id: <20220607203306.657998-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654635346758100001 Content-Type: text/plain; charset="utf-8" We will need this over in sme_helper.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/vec_internal.h | 13 +++++++++++++ target/arm/vec_helper.c | 2 +- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h index 1d527fadac..1f4ed80ff7 100644 --- a/target/arm/vec_internal.h +++ b/target/arm/vec_internal.h @@ -230,4 +230,17 @@ uint64_t pmull_h(uint64_t op1, uint64_t op2); */ uint64_t pmull_w(uint64_t op1, uint64_t op2); =20 +/** + * bfdotadd: + * @sum: addend + * @e1, @e2: multiplicand vectors + * + * BFloat16 2-way dot product of @e1 & @e2, accumulating with @sum. + * The @e1 and @e2 operands correspond to the 32-bit source vector + * slots and contain two Bfloat16 values each. + * + * Corresponds to the ARM pseudocode function BFDotAdd. + */ +float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2); + #endif /* TARGET_ARM_VEC_INTERNAL_H */ diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 26c373e522..9a9c034e36 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -2557,7 +2557,7 @@ DO_MMLA_B(gvec_usmmla_b, do_usmmla_b) * BFloat16 Dot Product */ =20 -static float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2) +float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2) { /* FPCR is ignored for BFDOT and BFMMLA. */ float_status bf_status =3D { --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654635598; cv=none; d=zohomail.com; s=zohoarc; b=XJVPnd5b26/uXfI/7V7V4Xh15CJW/l5qa9+UqSPA9xOYRUOSNd+9hWQKJjBu/kxpmq0gs7ew6cI4he+A+YfcHIe3jckz8WswDpuvd9hE/9rT2TbBJkvV5pKkrb1Q6UjPjuwQZHJHQKrhFa+ea4w38ZN6HIDbAdgTK53pan/Py40= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654635598; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uCpGQKdd2ynKIQl2a0URRju+a15a7A+73f9CXKIasy0=; b=N0ahglMckySsALIFH/BhRNL3gDZJkaPKz/ba29Y5lgtCKWsV59M6U7hMXrHPXOQXN5Cw61rKrJ4mO0sMjGheyb+OkwFNrSNSFPEICzek+hQqZr8L4ZJNds4EhGvEpckPZ3+z7gcTh1M5Yq3PvWjgtYYvssou3nBgRyM2Fbp2GzA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165463559814592.87237018989856; Tue, 7 Jun 2022 13:59:58 -0700 (PDT) Received: from localhost ([::1]:45978 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygIv-00016Z-4s for importer@patchew.org; Tue, 07 Jun 2022 16:59:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33914) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftL-0007qL-Vg for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:32 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:40865) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftF-0007Be-HW for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:31 -0400 Received: by mail-pl1-x62d.google.com with SMTP id i1so15790395plg.7 for ; Tue, 07 Jun 2022 13:33:25 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uCpGQKdd2ynKIQl2a0URRju+a15a7A+73f9CXKIasy0=; b=ASO0zUIQjhNW22emiswodrWo5M2+wvQ32cU72N+sB0R+EXPSYmf9iyrEZ1j4lO7zrG 7VLCvwaW0R746e4jh0X+/Kuefl2YHH2um8PcyYjIit8pjU4TXm/eYnAk7EqZgkDHC+1i i4Qhe5ibgZVRavhmlLfZXsYCG9FVjreVfGqmsvyTpSMj5vA+n96+xTTNIXQ3104ItWiC x7ZBN0Sjj3y42hqP1y7qNJxHSGsCZa/Lxv1o4ZlGK+O2rPFK7VBjSwSguHR0hHtynoSR uKUBkfwG2o+IXh2oInEoR+81htisDBdMU3637n4OtBAvlFZ4HMfAY+PXuh3tV8Pe4HFn UZGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uCpGQKdd2ynKIQl2a0URRju+a15a7A+73f9CXKIasy0=; b=spiAHgCO4jFmbu4FmbjWAWJfI+Cb8f9on+x89uCXBEphJE6nP8IQ0bIWVF8qjfYo+U KxSsPgqB4fH+u7Npy3TEPV0tugE13ZaWJWKWr7316sqpVMZNDmJFAHtwNo2HJf7qNwUk gQtoHENcbLdskv/T3xV5RcgxXh5H/rRglU1gk8fYxBtyFl+/eGPZSp6QBzHGHbrn+0jH n1ohLCzs4d6/5lW4lDcLnFmRtYLeWNxvjPI3LR2mlvvvSAVJU4n0DC8s1AVyhcmRNoF0 MCCBI1LxcpID4SUsKGEeTCvbsF93pW8vsIB6olZVAFDSjiUnlGfSleptPrRk/dkWR7xO fOnA== X-Gm-Message-State: AOAM531kB/7sPkUdW+gltRa57uJT/SwrnzQBu0wImHuRFp6S1R/DujWj s/wm86s77nj3POuBcGyfW9TuqWdW5MFHLQ== X-Google-Smtp-Source: ABdhPJwLQnm3byrQCNnq/soLfAjbyOWxnGk3m/QLuSxbQq0QahD7+T9i3sT0hIJkdnmTbcNfNKgl8A== X-Received: by 2002:a17:90a:e7d2:b0:1e8:97ac:da0b with SMTP id kb18-20020a17090ae7d200b001e897acda0bmr8213127pjb.242.1654634004747; Tue, 07 Jun 2022 13:33:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 19/71] target/arm: Add isar_feature_aa64_sme Date: Tue, 7 Jun 2022 13:32:14 -0700 Message-Id: <20220607203306.657998-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654635599921100001 Content-Type: text/plain; charset="utf-8" This will be used for implementing FEAT_SME. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2cc28f9e59..ce89ef5dc2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4043,6 +4043,11 @@ static inline bool isar_feature_aa64_mte(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >=3D 2; } =20 +static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) !=3D 0; +} + static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 4 && --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654635372; cv=none; d=zohomail.com; s=zohoarc; b=IEWFWvOWPvyTqX4K2ZGVuU/rvr9Bwpo92CGYziZ9BGL4L+BJ5SIkoeNVxD3VYRrTOv8529sSgVBbpHGOLhwVy4/BKagAyuXQTDdd/DDStSV4FzOUOyyvYXw/o6XKZPLyeYmfHc7fGDvR6UorQpzFfwc4LXfYhs8sekccKW+OKGc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654635372; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HGO//0wOn1sAEsIGZmCJxmY16sqRiuqL/H+xDewX7AQ=; b=KJN70CAUTWfAAkKxjiK/tkBGxscNYxDG1trx865ylcrI6ulqScBG6K1F+qgbmp1HWFsZDupMi1rRJlMTmiXmy44FrDqJX33NCVoe25dOKKaMnF1tr5eNojoq8clg0P8pPZXYeJaeuZDSr0h0U3Ktq/W//S/N1usQcNyajH0upxA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654635372773332.64222250129035; Tue, 7 Jun 2022 13:56:12 -0700 (PDT) Received: from localhost ([::1]:38104 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygFH-0003uF-Kz for importer@patchew.org; Tue, 07 Jun 2022 16:56:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33934) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftM-0007r7-7K for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:32 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:38632) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftH-0007KX-0K for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:31 -0400 Received: by mail-pg1-x535.google.com with SMTP id 123so6587659pgb.5 for ; Tue, 07 Jun 2022 13:33:26 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HGO//0wOn1sAEsIGZmCJxmY16sqRiuqL/H+xDewX7AQ=; b=IpsUlJMNikntsfusICz3pGW/MEPuf2nilsYHSm2oes5TsoVTujVCRy3pmaht1lNw/K xNt0WwazTORCR8dJdWj8a2eRnRCIWrv3CfORv+ibWVFrnBwnm0ifOG8sIvr/pXiy2LWu brZ5nYAxeAFXXH/oUia5pwfQQHaXkntJR4fIOeNJf06T/az9eW6BUG4CXqYOeOi8SDSc sUCr/IetPP5AjCB4CBF9cRJsnM+BePN65ay6PkmR0SOjwgQtp3q8+N/nwFwuQ39TOye6 iAl/f8vZqkRORC7tNVsPD2BzebYwpAeV7QFTJSoVEAvcBRtK2oZAAK56d0/Ljo0Y1oeV MlEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HGO//0wOn1sAEsIGZmCJxmY16sqRiuqL/H+xDewX7AQ=; b=spsS2ZFFOmbHP67TAPULTxeJGzdPfE7QrLylkCLtulWAsI/UylP9d0dtcc5Ph/Ouza Hl3CBfziA1FXcGG3WPtB6nN5VjE42V2qAy1x1EvujAPrqyxzdoOuvMKSFm9yetjlaoWi U42XFgR32fUmkIO8QhypuZegE+pO0zWeRCxKGWiM+M4TE02sWE4FDApdeaIxMWC4++mq CHtG7R/yUEnM9W3ehycdsr68a1xa4uzDOPbBToafO1PQwNd6NwAXjw3dWCExhk29DlIa 1iQxbBNZ5vvc8bOW79PvmJRfg3heDtGVxn0BPedeicc9kB1xIrg3HnhZxEfIML4AGg+Q hBJQ== X-Gm-Message-State: AOAM531gjbdsiEJvPzA0io7lwXlZRTQgpah3v6flSafVqXO3JX6AESen J4iIJeOi14ruFFgRNi7OfWO8i98/0RtKHw== X-Google-Smtp-Source: ABdhPJyiLX/ypvF8tJqQtkAak+ov3NhO3J8yc/nQRPES4Vp3PdKY8k9Y3CSj186vnH7On+MAqle9/Q== X-Received: by 2002:a63:33c5:0:b0:3fc:da19:45aa with SMTP id z188-20020a6333c5000000b003fcda1945aamr26070818pgz.522.1654634005668; Tue, 07 Jun 2022 13:33:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 20/71] target/arm: Add ID_AA64SMFR0_EL1 Date: Tue, 7 Jun 2022 13:32:15 -0700 Message-Id: <20220607203306.657998-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654635374878100001 Content-Type: text/plain; charset="utf-8" This register is allocated from the existing block of id registers, so it is already RES0 for cpus that do not implement SME. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 25 +++++++++++++++++++++++++ target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 11 +++++++---- 3 files changed, 34 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ce89ef5dc2..246371f93b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -966,6 +966,7 @@ struct ArchCPU { uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; uint64_t id_aa64zfr0; + uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; } isar; uint64_t midr; @@ -2190,6 +2191,15 @@ FIELD(ID_AA64ZFR0, I8MM, 44, 4) FIELD(ID_AA64ZFR0, F32MM, 52, 4) FIELD(ID_AA64ZFR0, F64MM, 56, 4) =20 +FIELD(ID_AA64SMFR0, F32F32, 32, 1) +FIELD(ID_AA64SMFR0, B16F32, 34, 1) +FIELD(ID_AA64SMFR0, F16F32, 35, 1) +FIELD(ID_AA64SMFR0, I8I32, 36, 4) +FIELD(ID_AA64SMFR0, F64F64, 48, 1) +FIELD(ID_AA64SMFR0, I16I64, 52, 4) +FIELD(ID_AA64SMFR0, SMEVER, 56, 4) +FIELD(ID_AA64SMFR0, FA64, 63, 1) + FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) FIELD(ID_DFR0, MMAPDBG, 8, 4) @@ -4190,6 +4200,21 @@ static inline bool isar_feature_aa64_sve_f64mm(const= ARMISARegisters *id) return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) !=3D 0; } =20 +static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); +} + +static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) =3D=3D 0xf; +} + +static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/helper.c b/target/arm/helper.c index cb44d528c0..48534db0bd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7732,11 +7732,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, .resetvalue =3D cpu->isar.id_aa64zfr0 }, - { .name =3D "ID_AA64PFR5_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + { .name =3D "ID_AA64SMFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, + .resetvalue =3D cpu->isar.id_aa64smfr0 }, { .name =3D "ID_AA64PFR6_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index b3f635fc95..ff8f65da22 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -574,6 +574,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) } else { err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, ARM64_SYS_REG(3, 0, 0, 4, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, + ARM64_SYS_REG(3, 0, 0, 4, 5)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, ARM64_SYS_REG(3, 0, 0, 5, 0)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, @@ -682,10 +684,11 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures= *ahcf) ahcf->isar.id_aa64pfr0 =3D t; =20 /* - * Before v5.1, KVM did not support SVE and did not expose - * ID_AA64ZFR0_EL1 even as RAZ. After v5.1, KVM still does - * not expose the register to "user" requests like this - * unless the host supports SVE. + * There is a range of kernels between kernel commit 73433762fcae + * and f81cb2c3ad41 which have a bug where the kernel doesn't expo= se + * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabl= ed + * SVE support, so we only read it here, rather than together with= all + * the other ID registers earlier. */ err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, ARM64_SYS_REG(3, 0, 0, 4, 4)); --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654635589; cv=none; d=zohomail.com; s=zohoarc; b=ieHLEpErTwGMpchxweOA7Y33KEdEcJ3ttFIUuzHux6/vtMraEsL0+le5IAkeItGGXdNR7yeKLZpBD0bckYer+9QvmmIj9LEFaui1W6NZkz3qe0KwTgDkbq5ovXB1Jb/CgtXBRkSDgFNKX6lElGuioTIp0hAkLqqfW89/S6Vtpks= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654635589; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZL65kXUjogqHvImAlQL3thwutvuDb7SzFLJksV0LJ4Y=; b=OdD4ew4gw8dMPkgdauIPzRcuAES+dlGgIpXMZYji0+SC2nuKSWRTckdpgrN1hoZXG4TpQeaCnoABlvytjW95vwa6Bpx7efKIIlEABZMAag4OdizEGpdjPMIkBbpA9A7KM/JQcZlirvK3VkjV/z1g1dJvIdeGJvx7I802dZ7uCik= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165463558913227.251340964881024; Tue, 7 Jun 2022 13:59:49 -0700 (PDT) Received: from localhost ([::1]:45430 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygIm-0000iy-01 for importer@patchew.org; Tue, 07 Jun 2022 16:59:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33986) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftN-0007wH-Ck for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:33 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:33637) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftI-0007L9-3V for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:33 -0400 Received: by mail-pf1-x432.google.com with SMTP id w21so16550583pfc.0 for ; Tue, 07 Jun 2022 13:33:27 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZL65kXUjogqHvImAlQL3thwutvuDb7SzFLJksV0LJ4Y=; b=oyZCl3QeNSgnai4eb64j5o0WWhTfPMUEEAoEMEhb8iGHYBycW2wjHMcYPgnX0wZD0g mqIe9TEXte/Lg+oZ/9+WWCIPnvePQ6KafWAID1zMXkb7bX73ikfLRUaM3PyeyMDBcrPc UoPApnh5MzOyul2QCB+D1aPiUMB5iHmhVK8ae3NWm9Lc0R3YS0Lfm/zdgvsJjdwe4nUr t4Ols75QK6zfibyxEetK5Ia7LjY2iT+7oVLxyIl5oM4+US+R+G+JbEBjOyrZ38i2hsjf sBHCjOwyr3K2pxKWQaIw9MD8rvnb9UHnWkrD9LvnITSycfckHTz0CVwJJv2+qeLMrDRp lOfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZL65kXUjogqHvImAlQL3thwutvuDb7SzFLJksV0LJ4Y=; b=GGE2bS2tfphtt4hUwbqFMTHbfm3OEaBIwge7fSHpQ8sFWcMvVnBE0eCRpmEwHVtgn4 K/QZ9vRUwI1dtZ5p8yar3b36TJiur8+10Wg8P5wvTtHxXKvrY41UHiU+sUiEwS2SbPlI OmaIVNI2n4MzZdD/z2OhII62l7hhktGcxIux9RkoVwBnjjk1LpwgT2u/ZrHbAgo5jtJ9 Y0deqO0WrYpgLoMeQD3az8oR4Kb7fLzxc8vQviF57rWukZGKNHzw/PwqihzFhNJAa4h8 KZARA1nOAmGjQo9kwLPbDR29wP0Utow0HJzPkHGrZI3EVOwYMLwRj4ElQry8p2zrrpNq yvaA== X-Gm-Message-State: AOAM53250QM5IMtI8ctmSlNZnRSuWcia8FFSkiYPRy7cHLyhI3195akP CQXx1NAYVaJ/qmYcx43O84ElLEv9tghm2w== X-Google-Smtp-Source: ABdhPJwgyTzgNL/rJi/kSz5i2oJuwDtDf8CHTOkpezn8k6TRauXNQE5mRW4MZE6E7R0A38MJOalY+Q== X-Received: by 2002:a63:4d16:0:b0:3fe:2062:60db with SMTP id a22-20020a634d16000000b003fe206260dbmr2022304pgb.214.1654634006641; Tue, 07 Jun 2022 13:33:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 21/71] target/arm: Implement TPIDR2_EL0 Date: Tue, 7 Jun 2022 13:32:16 -0700 Message-Id: <20220607203306.657998-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654635589853100001 Content-Type: text/plain; charset="utf-8" This register is part of SME, but isn't closely related to the rest of the extension. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/helper.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 246371f93b..31094a9248 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -474,6 +474,7 @@ typedef struct CPUArchState { }; uint64_t tpidr_el[4]; }; + uint64_t tpidr2_el0; /* The secure banks of these registers don't map anywhere */ uint64_t tpidrurw_s; uint64_t tpidrprw_s; diff --git a/target/arm/helper.c b/target/arm/helper.c index 48534db0bd..616ea70c9e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6283,6 +6283,35 @@ static const ARMCPRegInfo zcr_reginfo[] =3D { .writefn =3D zcr_write, .raw_writefn =3D raw_write }, }; =20 +#ifdef TARGET_AARCH64 +static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *= ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 0) { + uint64_t sctlr =3D arm_sctlr(env, el); + if (!(sctlr & SCTLR_EnTP2)) { + return CP_ACCESS_TRAP; + } + } + /* TODO: FEAT_FGT */ + if (el < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_ENTP2)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo sme_reginfo[] =3D { + { .name =3D "TPIDR2_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 13, .crm =3D 0, .opc2 =3D 5, + .access =3D PL0_RW, .accessfn =3D access_tpidr2, + .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr2_el0) }, +}; +#endif /* TARGET_AARCH64 */ + void hw_watchpoint_update(ARMCPU *cpu, int n) { CPUARMState *env =3D &cpu->env; @@ -8444,6 +8473,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 #ifdef TARGET_AARCH64 + if (cpu_isar_feature(aa64_sme, cpu)) { + define_arm_cp_regs(cpu, sme_reginfo); + } if (cpu_isar_feature(aa64_pauth, cpu)) { define_arm_cp_regs(cpu, pauth_reginfo); } --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654635903; cv=none; d=zohomail.com; s=zohoarc; b=Tq9fZ3TJqHM80uwx6t6vMcPzHa4C33ahUNBlX7UOTt9axozkEaJ+MCdOGDbYOnIaWQHsX5ZBLgrGcZNA+gYGzaSb4B8GYq8QxqykUYI9xDnjIhG6OIjKODOgqpEUMgjTEq1Q1G2aGpwbBcn7dSj5O3TDfCo+bv2Waz5KUmwpE8Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654635903; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cwMIrzdINWrV/sQZ3wz6KuPhrAMN58vwUNHGWXs01ZE=; b=MG7hvqCv6joOi63Wmz3OxmmwVgs4zXvlX/a4zgejHIpElZ8JwANvGW9TBM8Dms4ObefyZnFtLg8aWLskslgY256D2ZhIk/VUsbVr9PSYwfYCbKzR1YEfuWnYfDmxfvtEzxCH9HSzEs5kkFujdsrWmuKxTk4VcIAa45eudmE5ih8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654635903861410.55139773753797; Tue, 7 Jun 2022 14:05:03 -0700 (PDT) Received: from localhost ([::1]:56608 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygNp-0000IY-2P for importer@patchew.org; Tue, 07 Jun 2022 17:05:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34062) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftP-00082W-Nd for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:35 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:51858) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftJ-0007Ln-HG for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:35 -0400 Received: by mail-pj1-x1029.google.com with SMTP id cx11so16669744pjb.1 for ; Tue, 07 Jun 2022 13:33:28 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cwMIrzdINWrV/sQZ3wz6KuPhrAMN58vwUNHGWXs01ZE=; b=QKMR5SYLvauIOvMxGqZz5lQx7HyhZIObePwQ7I6a+BLJySLKZV+e9/DqjFJceWdwMC K7BsTTNVazex9j0s+lsd78MZzqGaB4K/vOfylXybePBbiL+rrMKP9mw3m50BQrvSSasD Mu1GnrHjg7kB5yPF6/WOcUt0U3b01+EBoCKz5o7PTgppf80hjMYJ0Zh+vGQtKRKYOzD+ O1d09FC2PZeMK2B2eI9YDihtkJG9+yR65uMKV9247z0eVOl6HL0lfCMtWRd0oDQSF/Ou sm6nCIOdHZR6Y1/8e2ZyFxZfIfWUVKDtmOwwpdM5y4pI6YMe4zoMBdU8PpRwi6JKbfsX zQww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cwMIrzdINWrV/sQZ3wz6KuPhrAMN58vwUNHGWXs01ZE=; b=y01ZnUGFCy8S5NHx6BgM0MTqLKsm52Fm1KXiNP6xhdy+4WrLg96/TYH8HTKAQIMB3Y cUpXdO4jFYOG/VxnaMODbMF1ydFvNMLUBHPef868k9jq24qulM7IenrZ3OUupPRHOov5 oF41YFamMTjH5V71HMrjEp7Wk0t69sSDvrG57AeEkSXsRbwJUCbgZstQnAJJg01mds/h VNmEwl7eXHKcjNwyNDRwJ0y/jcW+VoyaMimFca3x9WmW4OMjC8jJ33HVK7Foh3l/ahHG MSZNO11q0tfv5wkHob0fDAJ5H8IVZKbJ8re91VvJforP2suLs/RGTml9I3dE/3yIZwgL ZzwA== X-Gm-Message-State: AOAM533blOxB+huMjE+jXNZ86qNJhSH3GwF9zNSkYGIv6MYGcC9q5zKM FbP+xlNGWsMUiaJ9j0VRQV7Bh3b3BB9sUw== X-Google-Smtp-Source: ABdhPJwFiZMV8/zlSdA/C5MA9HqJRQCTQ21SW71WsbldD3v7q6Foz78lVFE3H7uhIn3RIL31EpH5EA== X-Received: by 2002:a17:903:4049:b0:167:515b:3efa with SMTP id n9-20020a170903404900b00167515b3efamr21517813pla.41.1654634007677; Tue, 07 Jun 2022 13:33:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 22/71] target/arm: Add SMEEXC_EL to TB flags Date: Tue, 7 Jun 2022 13:32:17 -0700 Message-Id: <20220607203306.657998-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654635904140100001 Content-Type: text/plain; charset="utf-8" This is CheckSMEAccess, which is the basis for a set of related tests for various SME cpregs and instructions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/translate.h | 1 + target/arm/helper.c | 52 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 1 + 4 files changed, 56 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 31094a9248..511c30d7d7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1134,6 +1134,7 @@ void aarch64_sync_64_to_32(CPUARMState *env); =20 int fp_exception_el(CPUARMState *env, int cur_el); int sve_exception_el(CPUARMState *env, int cur_el); +int sme_exception_el(CPUARMState *env, int cur_el); =20 /** * sve_vqm1_for_el: @@ -3272,6 +3273,7 @@ FIELD(TBFLAG_A64, ATA, 15, 1) FIELD(TBFLAG_A64, TCMA, 16, 2) FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) +FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) =20 /* * Helpers for using the above. diff --git a/target/arm/translate.h b/target/arm/translate.h index f473a21ed4..a492e4217b 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -42,6 +42,7 @@ typedef struct DisasContext { bool ns; /* Use non-secure CPREG bank on access */ int fp_excp_el; /* FP exception EL or 0 if enabled */ int sve_excp_el; /* SVE exception EL or 0 if enabled */ + int sme_excp_el; /* SME exception EL or 0 if enabled */ int vl; /* current vector length in bytes */ /* Flag indicating that exceptions from secure mode are routed to EL3.= */ bool secure_routed_to_el3; diff --git a/target/arm/helper.c b/target/arm/helper.c index 616ea70c9e..e0123dce67 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6222,6 +6222,55 @@ int sve_exception_el(CPUARMState *env, int el) return 0; } =20 +/* + * Return the exception level to which exceptions should be taken for SME. + * C.f. the ARM pseudocode function CheckSMEAccess. + */ +int sme_exception_el(CPUARMState *env, int el) +{ +#ifndef CONFIG_USER_ONLY + if (el <=3D 1 && !el_is_in_host(env, el)) { + switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, SMEN)) { + case 1: + if (el !=3D 0) { + break; + } + /* fall through */ + case 0: + case 2: + return 1; + } + } + + if (el <=3D 2 && arm_is_el2_enabled(env)) { + /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */ + if (env->cp15.hcr_el2 & HCR_E2H) { + switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, SMEN)) { + case 1: + if (el !=3D 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { + break; + } + /* fall through */ + case 0: + case 2: + return 2; + } + } else { + if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TSM)) { + return 2; + } + } + } + + /* CPTR_EL3. Since ESM is negative we must check for EL3. */ + if (arm_feature(env, ARM_FEATURE_EL3) + && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { + return 3; + } +#endif + return 0; +} + /* * Given that SVE is enabled, return the vector length for EL. */ @@ -13719,6 +13768,9 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState= *env, int el, int fp_el, } DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); } + if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { + DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el)); + } =20 sctlr =3D regime_sctlr(env, stage1); =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d438fb89e7..8bbd1b7f07 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14608,6 +14608,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->align_mem =3D EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il =3D EX_TBFLAG_ANY(tb_flags, PSTATE__IL); dc->sve_excp_el =3D EX_TBFLAG_A64(tb_flags, SVEEXC_EL); + dc->sme_excp_el =3D EX_TBFLAG_A64(tb_flags, SMEEXC_EL); dc->vl =3D (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; dc->pauth_active =3D EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); dc->bt =3D EX_TBFLAG_A64(tb_flags, BT); --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654635608; cv=none; d=zohomail.com; s=zohoarc; b=gDygVZ6UFfqr22bExuQWmIeiOeIqButE83cDoHn50IY0qT8qQzzRGuohpplKDKtIcA+i0Is12xZ9RKGx7BeQOI/sYDUYtCfeJI1X7X0lE2m6en9DFDTlRP/a+3weKel0bXcnmG7tB0UL5Cjp7Nyp/De4zLrpAHoHjCgXhjdalQg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654635608; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=W/BD6nh7cQl/3oZZqER53B+a4/wNAUufNSOwzZ1BBOk=; b=aT9k7O0TOxbtJ5IL/w37ei0GvRkOEKfJpO9ZSlxRaaQ2L9XtYdDlviRsPZT6h33LgsM9yCx0aP5OZahY8C19mNoZ8bGV2gMo4yjnLfl8U/SKx6nHzuBhqXjLuSvky4PoocwvNxB5xn3ZyewwvbGY3msGVJCfMGy2aBSMrePOz6k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654635608357609.3550799179629; Tue, 7 Jun 2022 14:00:08 -0700 (PDT) Received: from localhost ([::1]:46506 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygJ4-0001WG-Le for importer@patchew.org; Tue, 07 Jun 2022 17:00:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34016) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftO-0007yW-01 for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:34 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:44794) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftJ-0007E1-FO for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:33 -0400 Received: by mail-pj1-x1034.google.com with SMTP id gc3-20020a17090b310300b001e33092c737so16421711pjb.3 for ; Tue, 07 Jun 2022 13:33:29 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W/BD6nh7cQl/3oZZqER53B+a4/wNAUufNSOwzZ1BBOk=; b=Pa6DV5haIlOmJXGAWwl+YZaEm7RnC7QUiCo7kygGgxOnYE3wfYkCoKhrmvtobkw64o coBCUGxH7Gnsy7m5AOW9flYVE9p8Co1qFMBhD1TNTApqktdgqCoMRpbiyVg6ZmAXj+8h kgNu8miUzno8nAG3Tm4lFEtJVjclxyfSKQHvVg4/GPjT19OIHQU8BcJgkdtkKEJVpXzM aMEMy+rU4RDsF2L1O0fz20Ej0H2NqA/KSlYKdyIRqtkIJo1X2UTnskXPo5uPlF7LnJZN hSURKPuubeidn8F9zEusTLAJEbRCdvtEtyVWK4B4H/YQlWnuGBlylT7c02FBhosm1Cgr Zn9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W/BD6nh7cQl/3oZZqER53B+a4/wNAUufNSOwzZ1BBOk=; b=f7owqTCJIpAjeYca0kQA+CIZ4z0d8raVpBgUlfW1fbsNnZnyvO4aavWU8piNGhaYrD A1Fs+V3+CQVHvZmyYk0BZC+0CCfPg9XU9BwuptYz6QADv3mnUBuz5T3Ux5tzd/hMBsXO PAKN3oVxWd5t7CV661MYCzm9falS9VtuE7EKMJRl5PrV9bfc1QS5juOVUbcLimEiDXro e8QfQ+uFtGsZn787et1jreQ5RyV48fv/zNxZBpen4rP7bQ7yOZp9QaxMKi0dO8fKxC7Y wKBt0vfXlBVRPlEaeiuUUZrh4DxIPPYyY6KHR+NnluXk4N16BRZJyOkmhhWYm1YQc5Js xutQ== X-Gm-Message-State: AOAM531yz9sGKCNvmc3k9NfCI7A75ohU1EGyG6Rl9Czn2fpJXvzyOEsY JBziRrBwuMO/PyhvkJxmMMAViNBci6Fs1w== X-Google-Smtp-Source: ABdhPJwJPeZZu9KGJmEXPCcY2ECudao/4kMlT7HM09zyuAyKY96O4sGcQ8/erN1W0tYXoMwrmTYJhQ== X-Received: by 2002:a17:90a:fa16:b0:1e9:805a:bd72 with SMTP id cm22-20020a17090afa1600b001e9805abd72mr3205492pjb.70.1654634008752; Tue, 07 Jun 2022 13:33:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 23/71] target/arm: Add syn_smetrap Date: Tue, 7 Jun 2022 13:32:18 -0700 Message-Id: <20220607203306.657998-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654635610175100003 Content-Type: text/plain; charset="utf-8" This will be used for raising various traps for SME. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/syndrome.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 0cb26dde7d..4002766302 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -48,6 +48,7 @@ enum arm_exception_class { EC_AA64_SMC =3D 0x17, EC_SYSTEMREGISTERTRAP =3D 0x18, EC_SVEACCESSTRAP =3D 0x19, + EC_SMETRAP =3D 0x1d, EC_INSNABORT =3D 0x20, EC_INSNABORT_SAME_EL =3D 0x21, EC_PCALIGNMENT =3D 0x22, @@ -68,6 +69,13 @@ enum arm_exception_class { EC_AA64_BKPT =3D 0x3c, }; =20 +typedef enum { + SME_ET_AccessTrap, + SME_ET_Streaming, + SME_ET_NotStreaming, + SME_ET_InactiveZA, +} SMEExceptionType; + #define ARM_EL_EC_SHIFT 26 #define ARM_EL_IL_SHIFT 25 #define ARM_EL_ISV_SHIFT 24 @@ -206,6 +214,12 @@ static inline uint32_t syn_sve_access_trap(void) return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; } =20 +static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit) +{ + return (EC_SMETRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) | etype; +} + static inline uint32_t syn_pactrap(void) { return EC_PACTRAP << ARM_EL_EC_SHIFT; --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654635962; cv=none; d=zohomail.com; s=zohoarc; b=LPuhTQdB3ykvupqXjXceZfTYa00V3eCTgcoXpakBlST0ztUUXqAZpufOpCjM98TfkbyU5MkrfHYQg+hAB9lmmzEwa92zUcuY5Ha+hrxqMsBHzJvqB4FnO2VejdUEmgRE30WWrcPrKgCpV0UVEWIoEELkKTnWrFlrlQTEI+2KAgw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654635962; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BaEHnyzZVvArILP5rZ7zZnIc67EOdE5VHFcxDg3gfVA=; b=DoxB4yotRjhGxQxOawSpOql8W+1y8UQIDIqqFB4zOdUbNNt+kkY/FPgzjlZN3dBI9WhjeP2wApyHl4Pd+FG7QfunUVApxiWoiY7nPr58jzwyx7+5AuJ6wIIhXcPWgiuoNQbhKsnnqv/vZJ+ooutuzQ0B3kujMn7AsT69f7/A5Ag= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654635962964169.82062634020065; Tue, 7 Jun 2022 14:06:02 -0700 (PDT) Received: from localhost ([::1]:57982 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygOn-0001Eo-Ft for importer@patchew.org; Tue, 07 Jun 2022 17:06:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34042) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftP-00080q-2R for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:35 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:46724) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftK-0007D6-DT for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:34 -0400 Received: by mail-pl1-x633.google.com with SMTP id d13so133192plh.13 for ; Tue, 07 Jun 2022 13:33:29 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BaEHnyzZVvArILP5rZ7zZnIc67EOdE5VHFcxDg3gfVA=; b=TwvKToC7AqOOeBq5uriR71I5v5+RfjB7+1QsFvgZZUx6AvqwPCvYfXEQpCz1a99o9M pDoCBAbqFKzSSniAe0Lv0dvZPF/Rvc9/xm/Cye8x1oAQAd05NLXzW8OzjxBMHu4xEPX3 +Rk/01OJPLlrCYuVxh+8F8++4VOtG5ILcpK2/s+NG0fgYql0lM3s2z433pGcbg4ZYtp4 NgqrwKgDy9Sl7mohs5wxjmsFq+9Mk1SalCXodvQa0gH4dvhl3SwCyTV10yfkn4k0ZZYr ln5qQ1X9/vtRTepcJ1+d39Kv2AfYkwQCx3pDcS1EmXQRxurQ2I4WjKP7eyYprMn/x79h DKVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BaEHnyzZVvArILP5rZ7zZnIc67EOdE5VHFcxDg3gfVA=; b=WZ+K5SiXB5a+pDkhMzJQ83s8KdbUrlt7+PhgOqZaMXiwsRM/4iLGqJr1ElPu3pvpfs g37xGplLcptsEJFhS3xfF5OD27jroYwRB5fGew7Lopj7jpxTTfZePCXLinihPnTL0YGV CNQPhFivXxoWi1e3htXf5iCNrF+IiWBlTH2gn134qzQPAlPBQQLdJF9D5CUiqz+8fw9h wJcySlxRVZznsDmGOmwyyJ2rY/pI6TW9M81zcVHaxtNJKGKmI5g2zRdkFMRsXkLJKl0i FsyEi0i2bikmEnc5AqjryKbqHqtAcKFpOnUiblzdo75BBZycI713bblzulWOROGPga79 Lbng== X-Gm-Message-State: AOAM530gYVo3dclpIX0E8MbH6LMOz4uEKO1Kv6is3xget2gTgPh0AGPM u5e42bSzO8kRgQyBfaXba18adw1q/eZAuQ== X-Google-Smtp-Source: ABdhPJyNDUxnZZcO8pTm5X7v3hW3Dg9bLJ/Bi7akBC/QUYoLQygWIaW5MKwzokjaqyjHq4KYLP0+SA== X-Received: by 2002:a17:90b:4a92:b0:1e8:2c09:d008 with SMTP id lp18-20020a17090b4a9200b001e82c09d008mr27171112pjb.169.1654634009526; Tue, 07 Jun 2022 13:33:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 24/71] target/arm: Add ARM_CP_SME Date: Tue, 7 Jun 2022 13:32:19 -0700 Message-Id: <20220607203306.657998-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654635964519100001 Content-Type: text/plain; charset="utf-8" This will be used for controlling access to SME cpregs. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 5 +++++ target/arm/translate-a64.c | 18 ++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index d9b678c2f1..d30758ee71 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -113,6 +113,11 @@ enum { ARM_CP_EL3_NO_EL2_UNDEF =3D 1 << 16, ARM_CP_EL3_NO_EL2_KEEP =3D 1 << 17, ARM_CP_EL3_NO_EL2_C_NZ =3D 1 << 18, + /* + * Flag: Access check for this sysreg is constrained by the + * ARM pseudocode function CheckSMEAccess(). + */ + ARM_CP_SME =3D 1 << 19, }; =20 /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8bbd1b7f07..f51d80d816 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1186,6 +1186,22 @@ bool sve_access_check(DisasContext *s) return fp_access_check(s); } =20 +/* + * Check that SME access is enabled, raise an exception if not. + * Note that this function corresponds to CheckSMEAccess and is + * only used directly for cpregs. + */ +static bool sme_access_check(DisasContext *s) +{ + if (s->sme_excp_el) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_AccessTrap, false), + s->sme_excp_el); + return false; + } + return true; +} + /* * This utility function is for doing register extension with an * optional shift. You will likely want to pass a temporary for the @@ -1958,6 +1974,8 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, return; } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { return; + } else if ((ri->type & ARM_CP_SME) && !sme_access_check(s)) { + return; } =20 if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO))= { --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654635701; cv=none; d=zohomail.com; s=zohoarc; b=K6TvbzzJpykDj9yHpkuAfDfMhcIvpj92/ZLEvUY1t/+4qCxZImP7kUpbbjMVOI65C5r9A7VZbjka6Vc0L9AIp23xHmjPk+e4vFERHMVuQYmO4zuOMGfnAPbogceMNzQIcimH70k9MxguK8HxPRd/ocsh2YgQpJbmygP0yXdeyyY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654635701; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PXODLC2IHauVSpNYetn9TZRjqsCN3EktuiLVX88MFHQ=; b=HADLdbWA4f8IGxvhz9yAVJV/xKfiwEkzgPJVW7bxE+PgbPdpNNOkpWL689KDOFMWjCARiyqwfUTbvibcjm6OyvkxCuPtHUzBW1kGOCvCryPW0RV5PLbLY18NQefeVHhqzXfV0oFwHspNOeazGShrLJ1QChjGi//SAy1RMm0D0iw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16546357013381017.826206217333; Tue, 7 Jun 2022 14:01:41 -0700 (PDT) Received: from localhost ([::1]:48888 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygKa-0003K7-0q for importer@patchew.org; Tue, 07 Jun 2022 17:01:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34526) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfte-0000Ll-Mc for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:50 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:41879) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftL-0007Bo-6C for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:49 -0400 Received: by mail-pj1-x1035.google.com with SMTP id l20-20020a17090a409400b001dd2a9d555bso16461281pjg.0 for ; Tue, 07 Jun 2022 13:33:30 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PXODLC2IHauVSpNYetn9TZRjqsCN3EktuiLVX88MFHQ=; b=ZfUg08x841UKB/paTcDNbBiIoQDYtJK8r06r26gYcMRXvs3ghdj5X+/aE9guSjIs8k 9Jt5i5F7F+0vi7b4mUylTFrMzJ+uMJ7GgJ4UA8Y6nxG4E9s+uMvd5giVTtHjnCcE41xi l1q9WzKrQPtPzklqdO5KGnl3Mfc5yFvDLApBHwuBifwBInRCe/jWFkMTI77UZbOgM+iu uWBKHNMksgC6W+ldb8/svj4no6bCHPKCwDy+W092UVQO8fuHBH1oUsAtufnwADkx3y0Y 9tzYwdSV+gHWyGFstRYK/9Ul+jQdI8apPcmHs3+lz4dLQ2aZ5qCo7mVZPeE0Unme0exf duNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PXODLC2IHauVSpNYetn9TZRjqsCN3EktuiLVX88MFHQ=; b=6QLMW5kSXvH7sOcmm01GFsF8c/J9njAPsc3FSR+XrVmCRwxwgXvOEgfANeDNjDP/TN 2MzJtci43IPWfAzVOPA5JVWDpHLDmeL0cSTUUFyt6gSsB8I7jJeuY8l3Df8+P5WOZSgD EH16y4YTPhTQ4MxxYEc36lyV+bi5xY+Isqiio+RKKqPi5h4+6Cn5z5uH85Owjxzg0Dji YcaQ/Dh7nbSsIGFy8W8tcF7Q3rkl5Sjti6sFUKeb2w/q0l4aL63MRCzOySLY0cyHvrmF xAq97gOEhJ0ZPruvPbpqUx4bV3UAReWrzUW4LJROI82pJTw+7uYTSg5v5aCBIFe5kSx3 u8tQ== X-Gm-Message-State: AOAM530T0PfyMhgY220Z/nycTXHQJ6VWDM166AZibOkN1Ow+ewvIBSDm lKRuIOsN4SBsDGzWzaIxaOtstD9rvXnuMA== X-Google-Smtp-Source: ABdhPJwFLyyG9yiTt/IHQvsVpm3nEu+/HBmvgk/DoSG/HSJFhVs+Qu4AwHZccgkvaQrSsdqMcH4NEQ== X-Received: by 2002:a17:902:8b8b:b0:167:4e55:2dac with SMTP id ay11-20020a1709028b8b00b001674e552dacmr22523389plb.132.1654634010346; Tue, 07 Jun 2022 13:33:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 25/71] target/arm: Add SVCR Date: Tue, 7 Jun 2022 13:32:20 -0700 Message-Id: <20220607203306.657998-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654635702638100001 Content-Type: text/plain; charset="utf-8" This cpreg is used to access two new bits of PSTATE that are not visible via any other mechanism. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 6 ++++++ target/arm/helper.c | 13 +++++++++++++ 2 files changed, 19 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 511c30d7d7..f1a459af8b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -258,6 +258,7 @@ typedef struct CPUArchState { * nRW (also known as M[4]) is kept, inverted, in env->aarch64 * DAIF (exception masks) are kept in env->daif * BTYPE is kept in env->btype + * SM and ZA are kept in env->svcr * all other bits are stored in their correct places in env->pstate */ uint32_t pstate; @@ -292,6 +293,7 @@ typedef struct CPUArchState { uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ uint32_t btype; /* BTI branch type. spsr[11:10]. */ uint64_t daif; /* exception masks, in the bits they are in PSTATE */ + uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ =20 uint64_t elr_el[4]; /* AArch64 exception link regs */ uint64_t sp_el[4]; /* AArch64 banked stack pointers */ @@ -1428,6 +1430,10 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) #define PSTATE_MODE_EL1t 4 #define PSTATE_MODE_EL0t 0 =20 +/* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ +FIELD(SVCR, SM, 0, 1) +FIELD(SVCR, ZA, 1, 1) + /* Write a new value to v7m.exception, thus transitioning into or out * of Handler mode; this may result in a change of active stack pointer. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index e0123dce67..e2d6d89a5d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6353,11 +6353,24 @@ static CPAccessResult access_tpidr2(CPUARMState *en= v, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D R_SVCR_SM_MASK | R_SVCR_ZA_MASK; + /* TODO: Side effects. */ + env->svcr =3D value; +} + static const ARMCPRegInfo sme_reginfo[] =3D { { .name =3D "TPIDR2_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 13, .crm =3D 0, .opc2 =3D 5, .access =3D PL0_RW, .accessfn =3D access_tpidr2, .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr2_el0) }, + { .name =3D "SVCR", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 2, + .access =3D PL0_RW, .type =3D ARM_CP_SME, + .fieldoffset =3D offsetof(CPUARMState, svcr), + .writefn =3D svcr_write, .raw_writefn =3D raw_write }, }; #endif /* TARGET_AARCH64 */ =20 --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654635886; cv=none; d=zohomail.com; s=zohoarc; b=XV2FeI5Ie2hTC3VVTfU6qr/Nu6nJcz1iWlWlGYao70yz705A19NQL4bqJFnrtP8cPLfvfcNACRk+eRQgjSiIJDEiffXKi0yf8JZ1gK6IWjYfbCWgCFOaejfmiumM5JsCLd0QoiLyNoT+9ggviIJLUoTxCJ5zaySrGwb5+eHRAyQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654635886; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9o/b8H5uwznoVSQFJWAs54gwTyIT2NUPwpnhLmyD5pU=; b=fAsY6xC7pY3iJqN3Wsg9I3F/JofK9oarnSpH3jVFTO4uk7xj7q2NSTdpNeyybXzNYWCrqaQ6ArnO0cLymj25ws9IsyFUgugFJzkuBFsjLov9gNP6B7JqWta6cLpIoFPwini3uy+E7p6/076nrixrMRlQR9WdIntYFu/CbbIcmz8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654635886466121.93150976139793; Tue, 7 Jun 2022 14:04:46 -0700 (PDT) Received: from localhost ([::1]:56208 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygNZ-0008Pr-9B for importer@patchew.org; Tue, 07 Jun 2022 17:04:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34132) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftR-00089B-Oi for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:37 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:46976) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftM-0007Bp-15 for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:37 -0400 Received: by mail-pj1-x1034.google.com with SMTP id k5-20020a17090a404500b001e8875e6242so5675467pjg.5 for ; Tue, 07 Jun 2022 13:33:31 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9o/b8H5uwznoVSQFJWAs54gwTyIT2NUPwpnhLmyD5pU=; b=ITe3JCHLzVhOr+UyrjeRoG1Tsre/E2JO0xH6C8f470B9+V/OX4e3WIo/3rTYzPWD1g Qwa2aOXbLJX+R9EHZh/CkLc7h4KwD9odPVwmrCw1FG7sfHhjS466bZx4h8wiUwtzC8dw ME4cU9k/vW9iCY85yOJJTLTFdrQM0RE105CU8s9O9b/EyFNuWdjxckIZN19z/z/+8EMv o+cp09LHAVO8dpZVUTzhmXy1LcnjMwIjfhRuGgT3NnoKd72UBwUjevbB7WK63oMPkxSW m563E7GO7U/gHi5qCPnJ2/ccJBICBI8g8jlLicYs5eRFdPAn9lNGsG2onkqdBB7lcSDI QnWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9o/b8H5uwznoVSQFJWAs54gwTyIT2NUPwpnhLmyD5pU=; b=Dzjb1nEeUQvWLo/CJHRB2iAM1YxxrLzdehZx5z8evhLZOtG3kN2ghTewN3KqA5gZce CncPp4INn4SzDk7pmWN+TnBYDA7tvARVvNjFnM5gmvYlmP1IUor4BXAU/Wx42ktWolaJ Jm3QDK3+xARJQZJac0LQLcNIa5DmSZxrOZ+UQPELzp6O3BZtnt1pf1CwgqYVpKLqaOr2 8exDd6hGQ7cihF4fXbbzqtX/uIughKJj+nT875PlWhNRRDdpj3Vw6dodInlOHlCBXs+p ppRV8mm+BFqSlmSkTiqYPxe1qYqUqNvNTBB0uFEiSk/nnCor6fzaSXa2Rq5+/MrnwKRA RnXQ== X-Gm-Message-State: AOAM5321qJP8diWpoUWLsDEj3F0K10buDsBL2DDiupuqqaeJ4QsFcLGU EfJu2VaRp85JiX1wxwez0BivxWiPdht5XA== X-Google-Smtp-Source: ABdhPJwOwv+DkTOV4tc9Kb/W3ZTRbQNXRfknGlejDay75lyyK8Z3i44GA9KC6ES6TnhJttgTcQBILg== X-Received: by 2002:a17:902:d504:b0:167:756a:f99d with SMTP id b4-20020a170902d50400b00167756af99dmr13702910plg.6.1654634011200; Tue, 07 Jun 2022 13:33:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 26/71] target/arm: Add SMCR_ELx Date: Tue, 7 Jun 2022 13:32:21 -0700 Message-Id: <20220607203306.657998-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654635888023100001 Content-Type: text/plain; charset="utf-8" These cpregs control the streaming vector length and whether the full a64 instruction set is allowed while in streaming mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 8 ++++++-- target/arm/helper.c | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f1a459af8b..2f43b00843 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -669,8 +669,8 @@ typedef struct CPUArchState { float_status standard_fp_status; float_status standard_fp_status_f16; =20 - /* ZCR_EL[1-3] */ - uint64_t zcr_el[4]; + uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ + uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ } vfp; uint64_t exclusive_addr; uint64_t exclusive_val; @@ -1434,6 +1434,10 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) FIELD(SVCR, SM, 0, 1) FIELD(SVCR, ZA, 1, 1) =20 +/* Fields for SMCR_ELx. */ +FIELD(SMCR, LEN, 0, 4) +FIELD(SMCR, FA64, 31, 1) + /* Write a new value to v7m.exception, thus transitioning into or out * of Handler mode; this may result in a change of active stack pointer. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index e2d6d89a5d..46318515a8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5883,6 +5883,8 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) */ { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, + { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6), + "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme }, =20 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, @@ -6361,6 +6363,30 @@ static void svcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, env->svcr =3D value; } =20 +static void smcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + int cur_el =3D arm_current_el(env); + int old_len =3D sve_vqm1_for_el(env, cur_el); + int new_len; + + QEMU_BUILD_BUG_ON(ARM_MAX_VQ > R_SMCR_LEN_MASK + 1); + value &=3D R_SMCR_LEN_MASK | R_SMCR_FA64_MASK; + raw_write(env, ri, value); + + /* + * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage + * when SVL is widened (old values kept, or zeros). Choose to keep the + * current values for simplicity. But for QEMU internals, we must sti= ll + * apply the narrower SVL to the Zregs and Pregs -- see the comment + * above aarch64_sve_narrow_vq. + */ + new_len =3D sve_vqm1_for_el(env, cur_el); + if (new_len < old_len) { + aarch64_sve_narrow_vq(env, new_len + 1); + } +} + static const ARMCPRegInfo sme_reginfo[] =3D { { .name =3D "TPIDR2_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 13, .crm =3D 0, .opc2 =3D 5, @@ -6371,6 +6397,21 @@ static const ARMCPRegInfo sme_reginfo[] =3D { .access =3D PL0_RW, .type =3D ARM_CP_SME, .fieldoffset =3D offsetof(CPUARMState, svcr), .writefn =3D svcr_write, .raw_writefn =3D raw_write }, + { .name =3D "SMCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 6, + .access =3D PL1_RW, .type =3D ARM_CP_SME, + .fieldoffset =3D offsetof(CPUARMState, vfp.smcr_el[1]), + .writefn =3D smcr_write, .raw_writefn =3D raw_write }, + { .name =3D "SMCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 6, + .access =3D PL2_RW, .type =3D ARM_CP_SME, + .fieldoffset =3D offsetof(CPUARMState, vfp.smcr_el[2]), + .writefn =3D smcr_write, .raw_writefn =3D raw_write }, + { .name =3D "SMCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 6, + .access =3D PL3_RW, .type =3D ARM_CP_SME, + .fieldoffset =3D offsetof(CPUARMState, vfp.smcr_el[3]), + .writefn =3D smcr_write, .raw_writefn =3D raw_write }, }; #endif /* TARGET_AARCH64 */ =20 --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654636171; cv=none; d=zohomail.com; s=zohoarc; b=MD2rTt7w8EykacxeC98SxblI+YDikwVC/rnXeQ5cHwmYqXoknRu6WhNo3+Tv9ZTWzLnF4VTvIkFBb6Ja7xSj+xem0/o2gOCEGyDgkqvo+YfZDt4sgOVDL7UOIW+pHdBICOuAwa8mVzmtTbrFi56yw4ijqvwj0h2Ud3Jz6RHu870= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654636171; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=u3mG8wDmfQDUdFmC25VMT57BuuE4O0ooDRoJ9UT54UY=; b=h8ll/uspnECLB240U78MmqEOUN8J3816OTfnZbaPK/K9oKN/zA965+XmDLnUWPLl26y2/gDcsU5/tqLFcJ5hXNf7Nr6cS8wxowBaSODLSuPS6mUKswgSQV61jHAIOiGEkidAnIqxEtGNmNImj8Hkt0lgsceWhMK8b6dMoiJhJoE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654636170984446.76089303756055; Tue, 7 Jun 2022 14:09:30 -0700 (PDT) Received: from localhost ([::1]:36376 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygS9-0005je-No for importer@patchew.org; Tue, 07 Jun 2022 17:09:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34224) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftU-0008Gw-EU for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:40 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:38909) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftN-0007E5-DO for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:39 -0400 Received: by mail-pl1-x634.google.com with SMTP id n18so15800533plg.5 for ; Tue, 07 Jun 2022 13:33:32 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u3mG8wDmfQDUdFmC25VMT57BuuE4O0ooDRoJ9UT54UY=; b=CTYYilsQNzBZqcdO4ar0ypDz5XZ1HXOYderHcVkiFB0jXBbSWFi4bUoAo7VXRitVVv 61nFUoZ8nqPyekHUfDHZB/F37jEcQ/zP4GChaB7g9iTZRopCIX9Vnr0NzIYi7D6uk/ct K1+DSehphgD8MB5S0GefEEKa80oi9qRPlQpLaj2isJ6j761YqiHZTl9miOAE30yYjzEb zVKwJNeVPj0Z0DfVcE19QIJufcnKlOwljCL/45jjjHiAH3ZEZl9/I3QUwpsoCgZfMJgR oTnYZ2ievOWB2FNlx6ic0dttj32ApYl41HyK0uedVJnJbBIOEkCMEXhGRXVE0x3vaBx+ YObg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u3mG8wDmfQDUdFmC25VMT57BuuE4O0ooDRoJ9UT54UY=; b=d6u6anyqWDwz7QdOVpZgi1yVQW1HhQvb77XujKBFYoRzCL1PprK8FCSzsGjl7K2hxz PvAKMx+bXOtBsbk6XZDMOVy3qcwKXs4TpMshW35JLijZFFUHxRcC7I1SCeAhG/Igjysr oNFhs+GAcbxv8gbBcTHaPgu7nHjulN3G2TydViEGqk0b7lChgfJRJ1geLUYL/nMS2z1O nvy7FkiRfnwkObHkX173/WTfKzBvytN4LTte7yTABAaVctBkrlhy580tAIIQNDoQwIM4 zyb5104Jpby20nCIYVLxd92WBrH+yXtRIelTgjBPnedML50NS3NrJr0u5NXgOcIKfZU1 pspQ== X-Gm-Message-State: AOAM533EvpGXcOdtrH09F5cg42oqZYdhG0GntxbgpIdgQl04byzRzxbU zxozJX5cOe30Btp/kfRXWqy2EjaHdi8rhA== X-Google-Smtp-Source: ABdhPJzyQm4ELXqGBa+cQMXkotdEJuG1oQzp9lxBUSoqDNM/OGCoznXI4Xsg3vJrGl2KwQc9ZHaKKQ== X-Received: by 2002:a17:90a:ce07:b0:1e3:50eb:64d with SMTP id f7-20020a17090ace0700b001e350eb064dmr41160732pju.22.1654634012639; Tue, 07 Jun 2022 13:33:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 27/71] target/arm: Add SMIDR_EL1, SMPRI_EL1, SMPRIMAP_EL2 Date: Tue, 7 Jun 2022 13:32:22 -0700 Message-Id: <20220607203306.657998-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654636172221100001 Content-Type: text/plain; charset="utf-8" Implement the streaming mode identification register, and the two streaming priority registers. For QEMU, they are all RES0. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 46318515a8..e7e94213b1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6355,6 +6355,18 @@ static CPAccessResult access_tpidr2(CPUARMState *env= , const ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +static CPAccessResult access_esm(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + /* TODO: FEAT_FGT for SMPRI_EL1 but not SMPRIMAP_EL2 */ + if (arm_current_el(env) < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -6412,6 +6424,27 @@ static const ARMCPRegInfo sme_reginfo[] =3D { .access =3D PL3_RW, .type =3D ARM_CP_SME, .fieldoffset =3D offsetof(CPUARMState, vfp.smcr_el[3]), .writefn =3D smcr_write, .raw_writefn =3D raw_write }, + { .name =3D "SMIDR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 6, + .access =3D PL1_R, .accessfn =3D access_aa64_tid1, + /* + * IMPLEMENTOR =3D 0 (software) + * REVISION =3D 0 (implementation defined) + * SMPS =3D 0 (no streaming execution priority in QEMU) + * AFFINITY =3D 0 (streaming sve mode not shared with other PEs) + */ + .type =3D ARM_CP_CONST, .resetvalue =3D 0, }, + /* + * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0. + */ + { .name =3D "SMPRI_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 4, + .access =3D PL1_RW, .accessfn =3D access_esm, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "SMPRIMAP_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 5, + .access =3D PL2_RW, .accessfn =3D access_esm, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; #endif /* TARGET_AARCH64 */ =20 --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654634861; cv=none; d=zohomail.com; s=zohoarc; b=Uu9j4XjWpFMLv3KQBlkx7Z4q1s0/q9FNyTQgVdVTLAA5B2QJUcVoZKX3yDAKxVjwg6oZQ/MeYVsZyAodZWH+Oj2ZHdYiqF4GKeECBTFI+GOl+cEEGnW0Vq6lQiCNi+ACwO42oUiK8ewEqvmpKywPCoC0ulMuOG4X3j5OeG3SZKA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654634861; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=M1sbAH5tRNSXz726zBKA/xbfSYLMnAozHgakia7Z6MI=; b=ab/QWl73fXZbiTJobMf5U1Otq/EixKIQ5XFyEI2pdHYmwVOaUZZX7XwPcsN+44Kak0vfWuQW2ZReHxbwPYq4mOtIWUl6drmmU3hj7bV/xzKNNGohtgRN7xG73ydV+OcghnJqizlbwF0kh+JQCxool8AGkANqs2bWpP+8gEiNdgE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654634861379925.675271214464; Tue, 7 Jun 2022 13:47:41 -0700 (PDT) Received: from localhost ([::1]:49484 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyg72-0008P3-C8 for importer@patchew.org; Tue, 07 Jun 2022 16:47:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34264) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftV-0008Ko-OI for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:41 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:44794) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftO-0007E1-Dl for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:41 -0400 Received: by mail-pj1-x1034.google.com with SMTP id gc3-20020a17090b310300b001e33092c737so16421711pjb.3 for ; Tue, 07 Jun 2022 13:33:33 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M1sbAH5tRNSXz726zBKA/xbfSYLMnAozHgakia7Z6MI=; b=AB8uvFJvtBQk/PgO6FfArxUDSyHcqMAjV2jXZqWJO+ZlEQFElFqWO7D000kQXfo+lt GQFpLyIRc67RAZEWROZ8Y9t+9GxkA3kitSEHtsDxJexOKDqwJI2e8QJkOTrQkhhUyRHJ AwDMiS45JyC4Hin+essfF/4LBNkAahGcQf+WAFkE34UisVu2/9NTg4YGNFe8eFFrRpu0 ALbh7Anld1gYZLgayEhiIL+3dWkuR38gHJmqg34Fz6UlsM3rwDIinBZf/MewaUgPqh6y 7N3uJZsfg0YFoylG2VfBd2RoDTuJwTf5WLIi7fHGXbVTSKXUyi9MNt8f0tR2KR1FTPd/ XPCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M1sbAH5tRNSXz726zBKA/xbfSYLMnAozHgakia7Z6MI=; b=iutuImQ7N7FZ9nlhpAFGRGOcmKgRwMy7hqjK8EosjKaVqCQiU6mvZ3Pk9zRye18KlR qxDIrKys0/FFu7iuYxive9df0LOEByrpSXGFFDJP2QAGQDNzg7j4w94t0PytL4CRYo6B yuis4tRFn41Lnj/ewo6xSv7q6DCgJbN4HkOv5rDx5SpK70j3LgxD7A+9x37CM5u+80gM EAJ/WZfF8x+UG19Rut1Qtxuu7lzKEznDUgJm8Gg1p2B/xBbrxBy+5tttuXtqnZ3bGurS Y8uNpldI/0kU4PG4IzpNgZN/ZUYVWPe3TZLAc+TxHKnnnObhGZwYi4b6DGUtzG1pJJr7 QcLg== X-Gm-Message-State: AOAM531VWrWNTPavesZ0hrBCU38mcldbKg+0+lfch0e2r4msBMuXly5r Ecidd+eTETNhF1byRXGy2UJribBYJIGO0Q== X-Google-Smtp-Source: ABdhPJywuT4D3m/4DwAb9DmJCD+Ca+X5DXoYUP3exkE2fLl5+WQ/LH3JBKvbhYcx7aqWOPLYe8FAsQ== X-Received: by 2002:a17:903:283:b0:163:be9d:483a with SMTP id j3-20020a170903028300b00163be9d483amr30124663plr.166.1654634013608; Tue, 07 Jun 2022 13:33:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 28/71] target/arm: Add PSTATE.{SM,ZA} to TB flags Date: Tue, 7 Jun 2022 13:32:23 -0700 Message-Id: <20220607203306.657998-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654634861601100001 Content-Type: text/plain; charset="utf-8" These are required to determine if various insns are allowed to issue. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/translate.h | 4 ++++ target/arm/helper.c | 4 ++++ target/arm/translate-a64.c | 2 ++ 4 files changed, 12 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2f43b00843..b48a80dab7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3284,6 +3284,8 @@ FIELD(TBFLAG_A64, TCMA, 16, 2) FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) +FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) +FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) =20 /* * Helpers for using the above. diff --git a/target/arm/translate.h b/target/arm/translate.h index a492e4217b..fbd6713572 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -101,6 +101,10 @@ typedef struct DisasContext { bool align_mem; /* True if PSTATE.IL is set */ bool pstate_il; + /* True if PSTATE.SM is set. */ + bool pstate_sm; + /* True if PSTATE.ZA is set. */ + bool pstate_za; /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ bool mve_no_pred; /* diff --git a/target/arm/helper.c b/target/arm/helper.c index e7e94213b1..bec7e47b78 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13857,6 +13857,10 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMStat= e *env, int el, int fp_el, } if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el)); + if (FIELD_EX64(env->svcr, SVCR, SM)) { + DP_TBFLAG_A64(flags, PSTATE_SM, 1); + } + DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); } =20 sctlr =3D regime_sctlr(env, stage1); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f51d80d816..fdc035ad9a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14635,6 +14635,8 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->ata =3D EX_TBFLAG_A64(tb_flags, ATA); dc->mte_active[0] =3D EX_TBFLAG_A64(tb_flags, MTE_ACTIVE); dc->mte_active[1] =3D EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE); + dc->pstate_sm =3D EX_TBFLAG_A64(tb_flags, PSTATE_SM); + dc->pstate_za =3D EX_TBFLAG_A64(tb_flags, PSTATE_ZA); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654636525; cv=none; d=zohomail.com; s=zohoarc; b=nA6PVMk1SoQNVIan7c++qim9tDhQZctcd6UfvdfnRq2oyBz/MHauYxEPyYabB9mpIQTHiNWGtTLMP9rvyfNisXJO5QYUqwkrJKyXbRv3IoK5aEvZgSEATKLY8b2uto9FrfQ9+7qaWh+EKl5kGyL6mHrTXJYd6spOTos5amJWR0s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654636525; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EBTWvQZP/RYxFNlEjf8hqWkdSO6h/uW0wx557hiI+xw=; b=jEY4wYccAvTKIbguZWPztj10fan/OexKc3qGtcpVp2FnEx0HPM72owxhdIx+H85aYE465PyyYMxLB8cCF9U3oN64BCqoY/+t14x3S8yGOC3e5G4BWtBCP9EaRvIa5PGfD6QlDnh2R82EfxJdZUya6EDgNlG2wLgXHA2ufp2MmP0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165463652530074.01090581018514; Tue, 7 Jun 2022 14:15:25 -0700 (PDT) Received: from localhost ([::1]:45052 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygXs-0003UJ-9m for importer@patchew.org; Tue, 07 Jun 2022 17:15:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34290) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftW-0008N5-SI for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:42 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:35680) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftP-0007GS-Ln for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:42 -0400 Received: by mail-pj1-x102f.google.com with SMTP id o6-20020a17090a0a0600b001e2c6566046so21930494pjo.0 for ; Tue, 07 Jun 2022 13:33:35 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EBTWvQZP/RYxFNlEjf8hqWkdSO6h/uW0wx557hiI+xw=; b=Mh9AYBq3cU8LhosEfmERJz+m3mYNjuWH9xNqSnyMa4mOxYWNy5rh9iwg1sZ1n+yQCD npzDdeExp0tm+eIgk0q6g35WAaCxBx7kIGsT+5Fu7kfBa8ICFtC9WA0aWUHKismnfurm drt5mBnDKDR+Euo1qDw8aEAvBsnwLF1/4b9a67E8cmsUU1Zq/QqFopj+6RnmKi5FYcJi HOh6cnrhaJ9kIXJE8k4724hhEpTkNxPZPguMIQzxrlB8IGO8hsE2Sm2346P60khJ19uO 86b0t+naqs31TD0CraQQBrRbkRiuxJbFT8U/qEgZluXiXrTkRN/jY8zOIEvk2TNSGJ3Q gOoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EBTWvQZP/RYxFNlEjf8hqWkdSO6h/uW0wx557hiI+xw=; b=mQpf4M6m2AQOexcIKQ1bEYOmJztyVXKx4b/xPA/xzODzPs8AVbeoigfisBYsqF10Ly dJrRFWRipDY6tTANCoxjNX2P8VAEGjA7opYSeyJoM+phMMeySQosF7xfDClbJ7PSLdGz inHqTg/2GaYIQqkV5hwE/bWHA6I+W32XFSGhuAzCR4FhM7Zy24+Rkg93gXA53JuJwSv9 qHli4Im73XxonA2jSvuxHz1BAI08CodjC6IFqZZtuQzbmTO0F3i90Stec8ueqbrmzJpL hwoIQQ57R/4RI/iJF8qu/bu5ZIQi5srT6ZpX7mTX/Sl0Qeg9h1CdPc114NigDGHA0DRz khgg== X-Gm-Message-State: AOAM530zvX+Au/JtSkKFcQbKpTCCNErV2izRAlEePWz1QZ+VQ/XlQ7hy wCJ5o1mcZ8Uhgw6U1oTMlArC9ebGAyLJTQ== X-Google-Smtp-Source: ABdhPJxsflG6Ivhs71/ikQt4sx5BGzKxqrj7eQvWDjnsQoZZ2tRF0V/rUO4V9q1UP1S46JMydlarrQ== X-Received: by 2002:a17:903:2112:b0:166:496a:74b5 with SMTP id o18-20020a170903211200b00166496a74b5mr25958473ple.138.1654634014690; Tue, 07 Jun 2022 13:33:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 29/71] target/arm: Add the SME ZA storage to CPUARMState Date: Tue, 7 Jun 2022 13:32:24 -0700 Message-Id: <20220607203306.657998-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654636526417100001 Content-Type: text/plain; charset="utf-8" Place this late in the resettable section of the structure, to keep the most common element offsets from being > 64k. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 8 ++++++++ target/arm/machine.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b48a80dab7..ef374eefe8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -694,6 +694,14 @@ typedef struct CPUArchState { } keys; =20 uint64_t scxtnum_el[4]; + + /* + * SME ZA storage -- 256 x 256 byte array, with bytes in host word ord= er, + * as we do with vfp.zregs[]. Because this is so large, keep this tow= ard + * the end of the reset area, to keep the offsets into the rest of the + * structure smaller. + */ + ARMVectorReg zarray[ARM_MAX_VQ * 16]; #endif =20 #if defined(CONFIG_USER_ONLY) diff --git a/target/arm/machine.c b/target/arm/machine.c index 285e387d2c..54c5c62433 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -167,6 +167,39 @@ static const VMStateDescription vmstate_sve =3D { VMSTATE_END_OF_LIST() } }; + +static const VMStateDescription vmstate_vreg =3D { + .name =3D "vreg", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64_ARRAY(d, ARMVectorReg, ARM_MAX_VQ * 2), + VMSTATE_END_OF_LIST() + } +}; + +static bool za_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + /* + * When ZA storage is disabled, its contents are discarded. + * It will be zeroed when ZA storage is re-enabled. + */ + return FIELD_EX64(cpu->env.svcr, SVCR, ZA); +} + +static const VMStateDescription vmstate_za =3D { + .name =3D "cpu/sme", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D za_needed, + .fields =3D (VMStateField[]) { + VMSTATE_STRUCT_ARRAY(env.zarray, ARMCPU, ARM_MAX_VQ * 16, 0, + vmstate_vreg, ARMVectorReg), + VMSTATE_END_OF_LIST() + } +}; #endif /* AARCH64 */ =20 static bool serror_needed(void *opaque) @@ -884,6 +917,7 @@ const VMStateDescription vmstate_arm_cpu =3D { &vmstate_m_security, #ifdef TARGET_AARCH64 &vmstate_sve, + &vmstate_za, #endif &vmstate_serror, &vmstate_irq_line_state, --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654636336; cv=none; d=zohomail.com; s=zohoarc; b=N797gLeiwuPyQXTEr4NKV5CiL2u7XhrDeKbprXAL/ZNVWZG2l1n85uOr9oPQ/l7fNUhTCwVksxZ7LbtWITFR+lUAHQ9ZNfyTtCvyMFf5EgeWrbe5P39xMnVq3o9eE40JPVAHpAY2xmqkZmcvoQ5NPTljYRqot13Duw+Q0jKNzyQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654636336; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=03rd4A4qLn1D1mjrmymRetC77V7qJ8iA+zPBzz1Ln/A=; b=ECwAB+2MSMc+I1Lep7nj0oGpuQ+/XndKSNUsy6d1/Her32oLpPpgOOxqmZgkaHVJiUm1w648iXjmJKiut9EaI6jXIxTzb+mJ/6pNwh1RrQfrFpgbumplYHB8JLA4o5xUhlSJg2ObXDXMH5aFLHAcSosnz/8GNj5Q+p503jzSQfs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654636336013394.181816012656; Tue, 7 Jun 2022 14:12:16 -0700 (PDT) Received: from localhost ([::1]:38542 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygUo-0007IK-NE for importer@patchew.org; Tue, 07 Jun 2022 17:12:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34350) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftY-0008Tt-Lm for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:44 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:34720) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftQ-0007BX-Nw for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:44 -0400 Received: by mail-pf1-x433.google.com with SMTP id c196so16521128pfb.1 for ; Tue, 07 Jun 2022 13:33:36 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=03rd4A4qLn1D1mjrmymRetC77V7qJ8iA+zPBzz1Ln/A=; b=AFPsI8EMP2OouL7V8nW2DcLpV/7xF6hbSsvSGZZNfAPCl3ifNKm0u1kXZoIhBOl9sD GT7/aX+zj4EKWBC9yLZo1eBvcbkfRVXtj5ak3AyKkhZO4nyqqI2/Rd3jZnnxT7eQtk0u rjGyq7ymexCL8VUMq2CuaktTag6XshuckvdkRZrmIxDCqnKZVEJCfxAY2UWopiv9MoVr 3+WKWjzqfvjM07deFGCC05FlpPj/GoJKvWQ6Im/JBUlqmU6wTrYOkdoRLeTLzVH35HTY GjfbIxzZ2y3zL2DnfBxnBVbq1mXURPGZxjmEbsufuosY5AZvFEiMa7h199kAZJoqJfZb mFwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=03rd4A4qLn1D1mjrmymRetC77V7qJ8iA+zPBzz1Ln/A=; b=ZDGAyqjQQXtgIvcK5h36psyCd7h1GS2GtZGu1ir6a29YajFI//36GVwIM1G7GBYGIF 9Vh85sJna059bCE8wbtA0rG0YakuEV4/tDK4bI7p/AMhZ7fh6XqteX2AtshWSCDDQaWs ZOXmt0eEoIupiaGKCaacq1US5icGvi2G5Vc3vf9UTNmHotPQEkiUheDPZBM9gkVzLV54 IdkHg70R8npgcXZqJC7j20sDA6xIoEO3Z51sYZEt+mx4W/Vl5QDlJ5KjiTlZOUp+BIYO KUvS3toIEGGK2n+ZZk41pQtSJbzfdK9UbZsohfo5cdUDEC0tFm9zcyX7DCxQNx/u5Bbc RKaQ== X-Gm-Message-State: AOAM533zffubVerZJkvjb/AWIib6/ar9Gve/BIJ3lu/7rn9RKhQE79GY uFPYu9brl76kLIgdNOroc7bwCFGzihDxdA== X-Google-Smtp-Source: ABdhPJzH7C2m+/ehkey7RFhgJ3hWgAmP/uDe9ThphYNsK6NVoPreLW9VbBeIvDIlZMy8jVp/OZby2A== X-Received: by 2002:a63:2b8b:0:b0:3fc:c510:7941 with SMTP id r133-20020a632b8b000000b003fcc5107941mr27669275pgr.47.1654634015606; Tue, 07 Jun 2022 13:33:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 30/71] target/arm: Implement SMSTART, SMSTOP Date: Tue, 7 Jun 2022 13:32:25 -0700 Message-Id: <20220607203306.657998-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654636337317100001 Content-Type: text/plain; charset="utf-8" These two instructions are aliases of MSR (immediate). Use the two helpers to properly implement svcr_write. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/helper-sme.h | 21 +++++++++++++ target/arm/helper.h | 1 + target/arm/helper.c | 6 ++-- target/arm/sme_helper.c | 61 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 24 +++++++++++++++ target/arm/meson.build | 1 + 7 files changed, 112 insertions(+), 3 deletions(-) create mode 100644 target/arm/helper-sme.h create mode 100644 target/arm/sme_helper.c diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ef374eefe8..e7ec03a8a7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1106,6 +1106,7 @@ void aarch64_sve_change_el(CPUARMState *env, int old_= el, int new_el, bool el0_a64); void aarch64_add_sve_properties(Object *obj); void aarch64_add_pauth_properties(Object *obj); +void arm_reset_sve_state(CPUARMState *env); =20 /* * SVE registers are encoded in KVM's memory in an endianness-invariant fo= rmat. diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h new file mode 100644 index 0000000000..3bd48c235f --- /dev/null +++ b/target/arm/helper-sme.h @@ -0,0 +1,21 @@ +/* + * AArch64 SME specific helper definitions + * + * Copyright (c) 2022 Linaro, Ltd + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32) +DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32) diff --git a/target/arm/helper.h b/target/arm/helper.h index b1334e0c42..5bca7255f1 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1020,6 +1020,7 @@ DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG, #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" +#include "helper-sme.h" #endif =20 #include "helper-mve.h" diff --git a/target/arm/helper.c b/target/arm/helper.c index bec7e47b78..e065a1deb8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6370,9 +6370,9 @@ static CPAccessResult access_esm(CPUARMState *env, co= nst ARMCPRegInfo *ri, static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - value &=3D R_SVCR_SM_MASK | R_SVCR_ZA_MASK; - /* TODO: Side effects. */ - env->svcr =3D value; + helper_set_pstate_sm(env, FIELD_EX64(value, SVCR, SM)); + helper_set_pstate_za(env, FIELD_EX64(value, SVCR, ZA)); + arm_rebuild_hflags(env); } =20 static void smcr_write(CPUARMState *env, const ARMCPRegInfo *ri, diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c new file mode 100644 index 0000000000..b215725594 --- /dev/null +++ b/target/arm/sme_helper.c @@ -0,0 +1,61 @@ +/* + * ARM SME Operations + * + * Copyright (c) 2022 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/helper-proto.h" + +/* ResetSVEState */ +void arm_reset_sve_state(CPUARMState *env) +{ + memset(env->vfp.zregs, 0, sizeof(env->vfp.zregs)); + /* Recall that FFR is stored as pregs[16]. */ + memset(env->vfp.pregs, 0, sizeof(env->vfp.pregs)); + vfp_set_fpcr(env, 0x0800009f); +} + +void helper_set_pstate_sm(CPUARMState *env, uint32_t i) +{ + if (i =3D=3D FIELD_EX64(env->svcr, SVCR, SM)) { + return; + } + env->svcr ^=3D R_SVCR_SM_MASK; + arm_reset_sve_state(env); +} + +void helper_set_pstate_za(CPUARMState *env, uint32_t i) +{ + if (i =3D=3D FIELD_EX64(env->svcr, SVCR, ZA)) { + return; + } + env->svcr ^=3D R_SVCR_ZA_MASK; + + /* + * ResetSMEState. + * + * SetPSTATE_ZA zeros on enable and disable. We can zero this only + * on enable: while disabled, the storage is inaccessible and the + * value does not matter. We're not saving the storage in vmstate + * when disabled either. + */ + if (i) { + memset(env->zarray, 0, sizeof(env->zarray)); + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fdc035ad9a..40f2e53983 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1761,6 +1761,30 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, } break; =20 + case 0x1b: /* SVCR* */ + if (!dc_isar_feature(aa64_sme, s) || crm < 2 || crm > 7) { + goto do_unallocated; + } + if (sme_access_check(s)) { + bool i =3D crm & 1; + bool changed =3D false; + + if ((crm & 2) && i !=3D s->pstate_sm) { + gen_helper_set_pstate_sm(cpu_env, tcg_constant_i32(i)); + changed =3D true; + } + if ((crm & 4) && i !=3D s->pstate_za) { + gen_helper_set_pstate_za(cpu_env, tcg_constant_i32(i)); + changed =3D true; + } + if (changed) { + gen_rebuild_hflags(s); + } else { + s->base.is_jmp =3D DISAS_NEXT; + } + } + break; + default: do_unallocated: unallocated_encoding(s); diff --git a/target/arm/meson.build b/target/arm/meson.build index 50f152214a..02c91f72bb 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -47,6 +47,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'mte_helper.c', 'pauth_helper.c', 'sve_helper.c', + 'sme_helper.c', 'translate-a64.c', 'translate-sve.c', )) --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654635031; cv=none; d=zohomail.com; s=zohoarc; b=WXC8LlujSVEEtREZv+0R1rlGuH9lIyfg3ar2hwgNKPmnS0ADOlpsadbXtflIGN8ckHkQUDxk9aptXIZuy0YCwFRjP8mU+mmaBxSkqCgjmOd+MzuupAy97bD2LYXms+RktutnqS5YDo6+KiWV7PsNVCAIbtP5xmY9+tpDCW9lKeg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654635031; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iCOG6DsXO7r1GwfN6wKfqvV2SzATr8uc1yKAbhFIADk=; b=MPBhwN6Z+uDNd0RYY48jNoevdkO1TZgHqLAcqnS0T1u9EA11kEX7W54KNkx93qGTjV0nxQsYVp5mKtdhyi3VQiD1ZO4SeKbhdA1HIBoXgWuV46eRV0pFicPyt/jq6FpSXs56seqbmivwHvouVkcVmXUzjAuHTmwPLSMsgvfUClY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654635031435454.64347066498715; Tue, 7 Jun 2022 13:50:31 -0700 (PDT) Received: from localhost ([::1]:57904 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyg9l-0005im-SV for importer@patchew.org; Tue, 07 Jun 2022 16:50:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34404) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfta-00008E-97 for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:46 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:36462) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftR-0007RF-LZ for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:46 -0400 Received: by mail-pg1-x532.google.com with SMTP id y187so16974753pgd.3 for ; Tue, 07 Jun 2022 13:33:37 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iCOG6DsXO7r1GwfN6wKfqvV2SzATr8uc1yKAbhFIADk=; b=aMuz+txlVjvsgBhdIn3WNxv49jdideVw0erSeJ1vj7cRgTP+1FfyvABHXoITRywRwa S2xUcVxylTDWq6oLBMn1XpvV1IO6VHfWsgFMUtKSyMskV7IQcLujlIiyk8oETNieDsns BC/crXwVy+HDsU8ZLOHMp9E1Qk2cQSic3hWh1ad6tu4T/3DTXI/0EQmwcbQbpjseW63z TOmX4ccboArq6DQujcCuMEMmbT7gWezeU7oNEGQ1KHLJ4En68d97UCx1tlnJjsLX1sMm lA3YT5OANU2tEXgq5438IeZz7f7dKQ2Uqx3MueNqpT2873hcMyPuZyFBgl0B0OAS57ex ff4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iCOG6DsXO7r1GwfN6wKfqvV2SzATr8uc1yKAbhFIADk=; b=Gi6KjXb4kED871/EWMtK9LBOz6a9V1vKKqkY0oZFb2XAVeq/DnXrnH/VrBQKdlkbYe w2+Cp3rV/r7+pUqt2xHSrRLHljPxrFAd2669Z8aZKNd6+ic9hshfgN11QVO8mDbQXOpz yyXmeVCR6pkxVsMJuf8nb3+9letLFtYaMav63PHTGh84alCXtZ7BFitcGv5L8A8xNKuw iMj+Ssv55E5qUcjbrWe9LIG2nmunIx0ADIhxMw1kZ0jUd2YEpQ1iGmzx/pQU5vM8R1t8 oEjX/yhblv6kedrk/LMz3gyJcVlwh4vaptsmkpI6RJixPZwcxYvJ/LY9GUQ0yqCDHAzE uhkw== X-Gm-Message-State: AOAM533/7kclixQGvYZUsehVWbOtPWSn7xYlrOlPo4EyKywYjknM/MQ8 G+CF703bws/fkPmCtN0WMb1f9cJLOH4srg== X-Google-Smtp-Source: ABdhPJxaalStAAxpYpXZVhfuHTu5xQRIcEjdFWRez0S3u1OLqQ9d+g+QjEv+X3m434DNIrSbxpWXpw== X-Received: by 2002:a63:1152:0:b0:3fd:b58f:5be7 with SMTP id 18-20020a631152000000b003fdb58f5be7mr11273838pgr.164.1654634016424; Tue, 07 Jun 2022 13:33:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 31/71] target/arm: Move error for sve%d property to arm_cpu_sve_finalize Date: Tue, 7 Jun 2022 13:32:26 -0700 Message-Id: <20220607203306.657998-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654635032723100001 Content-Type: text/plain; charset="utf-8" Keep all of the error messages together. This does mean that when setting many sve length properties we'll only generate one error, but we only really need one. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu64.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 51c5d8d4bc..e18f585fa7 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -487,8 +487,13 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) "using only sve properties.\n"); } else { error_setg(errp, "cannot enable sve%d", vq * 128); - error_append_hint(errp, "This CPU does not support " - "the vector length %d-bits.\n", vq * 128= ); + if (vq_supported) { + error_append_hint(errp, "This CPU does not support " + "the vector length %d-bits.\n", vq *= 128); + } else { + error_append_hint(errp, "SVE not supported by KVM " + "on this host\n"); + } } return; } else { @@ -606,12 +611,6 @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v= , const char *name, return; } =20 - if (value && kvm_enabled() && !kvm_arm_sve_supported()) { - error_setg(errp, "cannot enable %s", name); - error_append_hint(errp, "SVE not supported by KVM on this host\n"); - return; - } - cpu->sve_vq_map =3D deposit32(cpu->sve_vq_map, vq - 1, 1, value); cpu->sve_vq_init |=3D 1 << (vq - 1); } --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654636563; cv=none; d=zohomail.com; s=zohoarc; b=l/eGdksHxQhcWRGQpjLJiNnReQi7wRdiKxswPE6EqFSgJK3qJ7ieLVEi0GNjl+cgGUM98DxFMBSXDGRDNaC0gAD+FJ8NXs6HXGwNNHt91ROyED/6ijZL3aDRtxIPZ4AmI9KdMyj+977YlUVEmDLGtTmvvlo6n/KB11/71AFBY7A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654636563; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1+sOff0+QrylHPJptcCOIS0ShDDTD4Sb4O393k+bbFc=; b=RkXUgd9HLyYqTJMYOQa6x+nTrm/VeMaBCZ7H9P21FEpIAbHr3c83vaMLLvaadusMFwupsuvaBjrDmXnVpleiip4cQcOKMneyEKBJFyq5KMee+Or93fp3XPWCCkUVmwomanZ6XyJbXwp4fjo38Ab+VR5N0dERzuhYyddhSjtDt/U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654636563705722.1796406233948; Tue, 7 Jun 2022 14:16:03 -0700 (PDT) Received: from localhost ([::1]:46694 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygYT-0004lV-LS for importer@patchew.org; Tue, 07 Jun 2022 17:16:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34462) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftc-0000Dy-1X for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:48 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:44789) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftS-0007Ra-Lw for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:47 -0400 Received: by mail-pj1-x102c.google.com with SMTP id gc3-20020a17090b310300b001e33092c737so16422673pjb.3 for ; Tue, 07 Jun 2022 13:33:38 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1+sOff0+QrylHPJptcCOIS0ShDDTD4Sb4O393k+bbFc=; b=Sh1z2Z8dy75CpmxSz/Cm2fbWdPPDzFPOTSXp0hu6LbszyPtiEIxPvkvZClnI/1d4Ul s/VrsIhL0y4kmJDiKgeglJs8HfLSSl13Mv7ScB0B0XHuSy5Ij2XPcE9G66jM3MEIDcCn F/rkb1EqsbamZQIxmZMUBiEtMdkZkYt0bcyMy4MwNj5HYmGzQdgEq7oSfHGw8ya2ZKaD s8+X3I3Xos1qGVMvFnnoe9UeI2tqnQVKoaU7lmdqoPS6hAXf6+U75z0WLFCRm7SjsBI/ k7XP+MrTXZe6YYpnNosq0LtXEHDR1PpqKlDiRzeyjYHbO5K0+jZSqnVnL+IpyIrSM8lo +a+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1+sOff0+QrylHPJptcCOIS0ShDDTD4Sb4O393k+bbFc=; b=rcQ4e6b+iESB9WIQKC0nDXP75FDFcei9UfHqnsZXEymlM8JJE135Yr5R3W0l/TTEuk ZwQkXjmLPdqb818X7NZC6ATjkmVLON8q2ADEx3q7+CUq58DQ3NmOeWDTokALtjOqs/Uy 8dzM+0VBHM0njeR+iI6XAEW/qSHd8HWJc4Payykzw6OnHB6abIKU219eNaJhs5wOwmxM cWkCnT7lfixqQwctTD8K9Ms03neO3X3qdiKTHABByryTjRWApvri3BYRI0b+GTWfV/ko HhZkZOdoEZZsD1dvGF1TF+R89MLtSIor9ZlGRj6Avme2edLoVcHd1q5SYueVyJi+yRk7 sy1Q== X-Gm-Message-State: AOAM533dACTTEHKGq8rP8cvhp83KkvTsjMiOTGCDFS6v8WhLSYnHodix rroJKYBZSjJH2iyHnzhV3xk6CkrAqPcVYg== X-Google-Smtp-Source: ABdhPJw6cbSynsiSaX/nQFB8/iyrhAzBMcSuQGkA4zZ8SzvyyGSVXbAyAXhY5PNuXKDFoKa0ZdtYpw== X-Received: by 2002:a17:902:e886:b0:163:f3e5:b3b9 with SMTP id w6-20020a170902e88600b00163f3e5b3b9mr30442727plg.80.1654634017274; Tue, 07 Jun 2022 13:33:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 32/71] target/arm: Create ARMVQMap Date: Tue, 7 Jun 2022 13:32:27 -0700 Message-Id: <20220607203306.657998-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654636564531100001 Content-Type: text/plain; charset="utf-8" Pull the three sve_vq_* values into a structure. This will be reused for SME. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 29 ++++++++++++++--------------- target/arm/cpu64.c | 22 +++++++++++----------- target/arm/helper.c | 2 +- target/arm/kvm64.c | 2 +- 4 files changed, 27 insertions(+), 28 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e7ec03a8a7..4e86d143c8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -793,6 +793,19 @@ typedef enum ARMPSCIState { =20 typedef struct ARMISARegisters ARMISARegisters; =20 +/* + * In map, each set bit is a supported vector length of (bit-number + 1) *= 16 + * bytes, i.e. each bit number + 1 is the vector length in quadwords. + * + * While processing properties during initialization, corresponding init b= its + * are set for bits in sve_vq_map that have been set by properties. + * + * Bits set in supported represent valid vector lengths for the CPU type. + */ +typedef struct { + uint32_t map, init, supported; +} ARMVQMap; + /** * ARMCPU: * @env: #CPUARMState @@ -1041,21 +1054,7 @@ struct ArchCPU { uint32_t sve_default_vq; #endif =20 - /* - * In sve_vq_map each set bit is a supported vector length of - * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector - * length in quadwords. - * - * While processing properties during initialization, corresponding - * sve_vq_init bits are set for bits in sve_vq_map that have been - * set by properties. - * - * Bits set in sve_vq_supported represent valid vector lengths for - * the CPU type. - */ - uint32_t sve_vq_map; - uint32_t sve_vq_init; - uint32_t sve_vq_supported; + ARMVQMap sve_vq; =20 /* Generic timer counter frequency, in Hz */ uint64_t gt_cntfrq_hz; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e18f585fa7..0a2f4f3170 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -355,8 +355,8 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * any of the above. Finally, if SVE is not disabled, then at least o= ne * vector length must be enabled. */ - uint32_t vq_map =3D cpu->sve_vq_map; - uint32_t vq_init =3D cpu->sve_vq_init; + uint32_t vq_map =3D cpu->sve_vq.map; + uint32_t vq_init =3D cpu->sve_vq.init; uint32_t vq_supported; uint32_t vq_mask =3D 0; uint32_t tmp, vq, max_vq =3D 0; @@ -369,14 +369,14 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) */ if (kvm_enabled()) { if (kvm_arm_sve_supported()) { - cpu->sve_vq_supported =3D kvm_arm_sve_get_vls(CPU(cpu)); - vq_supported =3D cpu->sve_vq_supported; + cpu->sve_vq.supported =3D kvm_arm_sve_get_vls(CPU(cpu)); + vq_supported =3D cpu->sve_vq.supported; } else { assert(!cpu_isar_feature(aa64_sve, cpu)); vq_supported =3D 0; } } else { - vq_supported =3D cpu->sve_vq_supported; + vq_supported =3D cpu->sve_vq.supported; } =20 /* @@ -534,7 +534,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) =20 /* From now on sve_max_vq is the actual maximum supported length. */ cpu->sve_max_vq =3D max_vq; - cpu->sve_vq_map =3D vq_map; + cpu->sve_vq.map =3D vq_map; } =20 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *na= me, @@ -595,7 +595,7 @@ static void cpu_arm_get_sve_vq(Object *obj, Visitor *v,= const char *name, if (!cpu_isar_feature(aa64_sve, cpu)) { value =3D false; } else { - value =3D extract32(cpu->sve_vq_map, vq - 1, 1); + value =3D extract32(cpu->sve_vq.map, vq - 1, 1); } visit_type_bool(v, name, &value, errp); } @@ -611,8 +611,8 @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v,= const char *name, return; } =20 - cpu->sve_vq_map =3D deposit32(cpu->sve_vq_map, vq - 1, 1, value); - cpu->sve_vq_init |=3D 1 << (vq - 1); + cpu->sve_vq.map =3D deposit32(cpu->sve_vq.map, vq - 1, 1, value); + cpu->sve_vq.init |=3D 1 << (vq - 1); } =20 static bool cpu_arm_get_sve(Object *obj, Error **errp) @@ -973,7 +973,7 @@ static void aarch64_max_initfn(Object *obj) cpu->dcz_blocksize =3D 7; /* 512 bytes */ #endif =20 - cpu->sve_vq_supported =3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); + cpu->sve_vq.supported =3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); =20 aarch64_add_pauth_properties(obj); aarch64_add_sve_properties(obj); @@ -1022,7 +1022,7 @@ static void aarch64_a64fx_initfn(Object *obj) =20 /* The A64FX supports only 128, 256 and 512 bit vector lengths */ aarch64_add_sve_properties(obj); - cpu->sve_vq_supported =3D (1 << 0) /* 128bit */ + cpu->sve_vq.supported =3D (1 << 0) /* 128bit */ | (1 << 1) /* 256bit */ | (1 << 3); /* 512bit */ =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index e065a1deb8..e3f3e4dfc2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6291,7 +6291,7 @@ uint32_t sve_vqm1_for_el(CPUARMState *env, int el) len =3D MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[3]); } =20 - len =3D 31 - clz32(cpu->sve_vq_map & MAKE_64BIT_MASK(0, len + 1)); + len =3D 31 - clz32(cpu->sve_vq.map & MAKE_64BIT_MASK(0, len + 1)); return len; } =20 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index ff8f65da22..d16d4ea250 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -820,7 +820,7 @@ uint32_t kvm_arm_sve_get_vls(CPUState *cs) static int kvm_arm_sve_set_vls(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); - uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] =3D { cpu->sve_vq_map }; + uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] =3D { cpu->sve_vq.map }; struct kvm_one_reg reg =3D { .id =3D KVM_REG_ARM64_SVE_VLS, .addr =3D (uint64_t)&vls[0], --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654635375; cv=none; d=zohomail.com; s=zohoarc; b=kYTkVf+fR4NAESHwUJACcqzxe+5umng2bTCYwuT/UpByar7WDQgIMp8pkWiepmugLxNOa4GUgTqQyyXQsk8LTVTMid3MdVW9T8AGI98Cu9XSpBfNt/mobLob5yLX6BMB2j0fRcVUHLG5viNB/GA0LjDJYKCCdev4aHYK7nOf1ao= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654635375; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fwPtvhYNG8jCnQ1cI9YW7usJn3JNHfnrq4zhCHsHE5Y=; b=MxzIYGceoED1CJ08IWUi6OjSG25mVg4ylwRQhErbf9lLok8srKuaPxpeep2mrZdbIr NrI7c9+IH5VpWUm0JhAYtT3lEE0SaUhwYUalsivPofNKAjr8m/VueWx+uRjt+P1jJ/yW BL7oZ6JuMWy8qvUXdRSUib/taHgPQ4cTHtoqO+XIF0VI4yh0JCs1aFVhpNGl0qyMCXdY kFxMir93dEooyb2fIUEIvST+x4QbtSwYJywO/Bi0/767uRksw9SLMta9hfWTct7tQJBD /cb+BKaO+WY7U+p6DVNEkW3Wr3fAGy8t1veCwPibG2dsPURqmGmhoqUQN8bpPCRDNIoO x1Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fwPtvhYNG8jCnQ1cI9YW7usJn3JNHfnrq4zhCHsHE5Y=; b=msklAAKdEOcIfJryGzKj8XenwxeOwJGB6Ok7/RmNww7pqDbvVHSXijGJ0uSJPNO2s7 FRsSQrN5VYSZaEywrXi9c9Zx+rS3b+EzmR1xCyi3OdVBeCeB6Mnh+nQVr/jU0cj5rEpP 2Mns+petXHerO4vDex8f84TXC/XFlh1CVnlhHLxQFnGE04R+o+zU9hhM3r6BhxbdAW7C voLabpN7UorvCkZc8PA8JZL9XG8VD+bisRA1Lh61IhCHdP/dkSLe3unT0UYC4KznaFp5 +X1iLKDMqZgMul/sU9yFHDwq9XylSZgyevmxPcH/cI2u3IQPX873hSKBYCnbAGdLxC1C fN7Q== X-Gm-Message-State: AOAM532XE4KRRK+PBbFOJ7yHGMmPReiSRqQq/NbHSUU0T1OnHq5gJTHL xI1VLBLEJFs3Sg5ooT5wxGkoYOWQ9gTSBg== X-Google-Smtp-Source: ABdhPJwQrlRRBNjA1xMMMZy+KMUj0jNQCr4IKubTZo4dhwsrHMxEJUing+MafXPvksYFglEHgUbnLA== X-Received: by 2002:a17:902:efcc:b0:163:f35b:2a99 with SMTP id ja12-20020a170902efcc00b00163f35b2a99mr29975966plb.42.1654634018260; Tue, 07 Jun 2022 13:33:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 33/71] target/arm: Generalize cpu_arm_{get,set}_vq Date: Tue, 7 Jun 2022 13:32:28 -0700 Message-Id: <20220607203306.657998-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654635376876100003 Content-Type: text/plain; charset="utf-8" Rename from cpu_arm_{get,set}_sve_vq, and take the ARMVQMap as the opaque parameter. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu64.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0a2f4f3170..dcec0a6559 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -579,15 +579,15 @@ static void cpu_max_set_sve_max_vq(Object *obj, Visit= or *v, const char *name, } =20 /* - * Note that cpu_arm_get/set_sve_vq cannot use the simpler - * object_property_add_bool interface because they make use - * of the contents of "name" to determine which bit on which - * to operate. + * Note that cpu_arm_{get,set}_vq cannot use the simpler + * object_property_add_bool interface because they make use of the + * contents of "name" to determine which bit on which to operate. */ -static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) +static void cpu_arm_get_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMVQMap *vq_map =3D opaque; uint32_t vq =3D atoi(&name[3]) / 128; bool value; =20 @@ -595,15 +595,15 @@ static void cpu_arm_get_sve_vq(Object *obj, Visitor *= v, const char *name, if (!cpu_isar_feature(aa64_sve, cpu)) { value =3D false; } else { - value =3D extract32(cpu->sve_vq.map, vq - 1, 1); + value =3D extract32(vq_map->map, vq - 1, 1); } visit_type_bool(v, name, &value, errp); } =20 -static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) +static void cpu_arm_set_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) { - ARMCPU *cpu =3D ARM_CPU(obj); + ARMVQMap *vq_map =3D opaque; uint32_t vq =3D atoi(&name[3]) / 128; bool value; =20 @@ -611,8 +611,8 @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v,= const char *name, return; } =20 - cpu->sve_vq.map =3D deposit32(cpu->sve_vq.map, vq - 1, 1, value); - cpu->sve_vq.init |=3D 1 << (vq - 1); + vq_map->map =3D deposit32(vq_map->map, vq - 1, 1, value); + vq_map->init |=3D 1 << (vq - 1); } =20 static bool cpu_arm_get_sve(Object *obj, Error **errp) @@ -691,6 +691,7 @@ static void cpu_arm_get_sve_default_vec_len(Object *obj= , Visitor *v, =20 void aarch64_add_sve_properties(Object *obj) { + ARMCPU *cpu =3D ARM_CPU(obj); uint32_t vq; =20 object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); @@ -698,8 +699,8 @@ void aarch64_add_sve_properties(Object *obj) for (vq =3D 1; vq <=3D ARM_MAX_VQ; ++vq) { char name[8]; sprintf(name, "sve%d", vq * 128); - object_property_add(obj, name, "bool", cpu_arm_get_sve_vq, - cpu_arm_set_sve_vq, NULL, NULL); + object_property_add(obj, name, "bool", cpu_arm_get_vq, + cpu_arm_set_vq, NULL, &cpu->sve_vq); } =20 #ifdef CONFIG_USER_ONLY --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654636610015309.813975193076; Tue, 7 Jun 2022 14:16:50 -0700 (PDT) Received: from localhost ([::1]:48790 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygZE-0006E0-V1 for importer@patchew.org; Tue, 07 Jun 2022 17:16:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34464) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftc-0000E9-3o for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:48 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:40825) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftU-0007Gf-0X for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:47 -0400 Received: by mail-pg1-x52d.google.com with SMTP id f65so6752127pgc.7 for ; Tue, 07 Jun 2022 13:33:39 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7xdazpoc98KTxU+Hkap6hV74hgs0EjjQuCmdWfoKk1g=; b=uHv8x/Nf/neIA93S+wbDDYJYsPsV/MqtVTAQmTlIjXJiapyq7dFbfboMwxhIW827Y4 zQrm8DKH+1VqIjniD92OQjvoUddABJrw7B0rOC5bne6gsrwvPrALbPETZhDKBUoDeYgc T77DDXDUWI5ebZlsUPT4xrWrahIX6BgEYaqkPQ+9OExvG4MARHI3TKr99BhlijmBdsFH b6oOelGO/QptVsLP2zlPKPKvcsZrIX0ZhV90LbFaJJkb6nIUQ91tXeVQGOR1fRGJ90w/ oletdaoLZeMQmxlHyMbEJEKUiQPl9XjKXGeSSt1OhAJDp14niW24dP6NYcv4Cr9wqyxx Mi+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7xdazpoc98KTxU+Hkap6hV74hgs0EjjQuCmdWfoKk1g=; b=6IHTh22HWPrl9LbURcxEFLEkQ5j2ORwc7JxMCNDi1x6856UN0ONgemNizePIRZJ2vG H6AJLl+oQdujmoYJwcx3Gv0/CxMZk8Wct8S7en2FJ7AtgwF+82YBAdaVyKCBViBDdEjZ MAiliKEgWcAl78CsJcGQFI74bweaGzwnwd9KrSesxi45TPoSipAqFVOUCoVXcuOSU3jY 8zVKt/xJ/FWgcBrCEv5QS3P7JJxdPbpU6/RkkTz2g62LN/hTi+b7pomZx3k6qCQ4aLJ1 gaGKStww8KREasf6nvxdqdPEiUxHHEJ7B5ifE0w0cXjcMsjYR3ACdFILR6N8TgcxbnzC J8FQ== X-Gm-Message-State: AOAM533d7a+szqVoAni4Ge0f05U1mPrsm5PhKsAfrtxHs7hj0M3j3uYA MyKkQBLhUbcVx7kY0Fn6qpVWhRle0m0pxQ== X-Google-Smtp-Source: ABdhPJw9SlGCccT/591rCxQn/fjxDfdwg5CPPElfsbHOkT/UgDXxAPjzCPEMtGo8sKY6wQpccXsenA== X-Received: by 2002:a63:b55:0:b0:3fd:a384:bd10 with SMTP id a21-20020a630b55000000b003fda384bd10mr12291615pgl.534.1654634019154; Tue, 07 Jun 2022 13:33:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 34/71] target/arm: Generalize cpu_arm_{get, set}_default_vec_len Date: Tue, 7 Jun 2022 13:32:29 -0700 Message-Id: <20220607203306.657998-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1654636611726100001 Content-Type: text/plain; charset="utf-8" Rename from cpu_arm_{get,set}_sve_default_vec_len, and take the pointer to default_vq from opaque. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu64.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index dcec0a6559..c5bfc3d082 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -638,11 +638,11 @@ static void cpu_arm_set_sve(Object *obj, bool value, = Error **errp) =20 #ifdef CONFIG_USER_ONLY /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ -static void cpu_arm_set_sve_default_vec_len(Object *obj, Visitor *v, - const char *name, void *opaque, - Error **errp) +static void cpu_arm_set_default_vec_len(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) { - ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t *ptr_default_vq =3D opaque; int32_t default_len, default_vq, remainder; =20 if (!visit_type_int32(v, name, &default_len, errp)) { @@ -651,7 +651,7 @@ static void cpu_arm_set_sve_default_vec_len(Object *obj= , Visitor *v, =20 /* Undocumented, but the kernel allows -1 to indicate "maximum". */ if (default_len =3D=3D -1) { - cpu->sve_default_vq =3D ARM_MAX_VQ; + *ptr_default_vq =3D ARM_MAX_VQ; return; } =20 @@ -675,15 +675,15 @@ static void cpu_arm_set_sve_default_vec_len(Object *o= bj, Visitor *v, return; } =20 - cpu->sve_default_vq =3D default_vq; + *ptr_default_vq =3D default_vq; } =20 -static void cpu_arm_get_sve_default_vec_len(Object *obj, Visitor *v, - const char *name, void *opaque, - Error **errp) +static void cpu_arm_get_default_vec_len(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) { - ARMCPU *cpu =3D ARM_CPU(obj); - int32_t value =3D cpu->sve_default_vq * 16; + uint32_t *ptr_default_vq =3D opaque; + int32_t value =3D *ptr_default_vq * 16; =20 visit_type_int32(v, name, &value, errp); } @@ -706,8 +706,9 @@ void aarch64_add_sve_properties(Object *obj) #ifdef CONFIG_USER_ONLY /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ object_property_add(obj, "sve-default-vector-length", "int32", - cpu_arm_get_sve_default_vec_len, - cpu_arm_set_sve_default_vec_len, NULL, NULL); + cpu_arm_get_default_vec_len, + cpu_arm_set_default_vec_len, NULL, + &cpu->sve_default_vq); #endif } =20 --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654636808; cv=none; d=zohomail.com; s=zohoarc; b=gofPZnbsUMo+HWrS80P+CaPBDuVcuc63EGuHdCQKeTi+EuwK2jFv3+xICMRvKJZXiZ2VtH77q2U+DrEXX0wdIEeotoCK6zGLZnIv8FMZPDa+Tbwe2NQU26Ez3iFIrCEwkueBs1e/+uhahplg37MqQARQwhGadKBF9lEDch3DjFE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654636808; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Im5u11D8yrAC4qQJy1JnWa+rWzoOJ65BBH7IOoUdIyQ=; b=LAsrB1ZFZfvNyZEFT/TFPx22/2XGgb10TUECfuven3OSGpZg/k1Fru15qcdgZd/eNZDQyg/T58E5NEUHPttrq53K8W8RJSrg61UZvulraqMr7AvVV3xQ8UwmEmaoMFkLurgT9Bq465+sS53+esM1+l5ABhI7yVYf4n2PGQV+lm4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654636808503105.29286215152274; Tue, 7 Jun 2022 14:20:08 -0700 (PDT) Received: from localhost ([::1]:57216 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygcR-0003dx-AO for importer@patchew.org; Tue, 07 Jun 2022 17:20:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34510) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftd-0000Kb-Du for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:49 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:34699) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftU-0007L8-RQ for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:49 -0400 Received: by mail-pg1-x52d.google.com with SMTP id g186so8075803pgc.1 for ; Tue, 07 Jun 2022 13:33:40 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Im5u11D8yrAC4qQJy1JnWa+rWzoOJ65BBH7IOoUdIyQ=; b=J7y0v9iGUlDOPRh03zbC+4A23pTa9EYfociFC23p5YJ2Us9UuFs90ppQkFkKc9NXGJ USavmNA6PahvKQ6So04V1eHIUv6RT0yqWqbkzlG9o6Lus7PpienJh9MNj231macFiVyC hAzXIb3IHxgYSTzJ/8BTcthPfuAX5apARy4k9NcQRtWD5TD96OpLyLqh3+SXZzRi5d4d g4+JrSrenyecs087twarVewtPduCgVb0/73iLLAAYUa7t+akuUMXTr02dlvCiepmiQUG 66lViN87wmMx2Y0OopVSipGO24er1RaujcJ2h+jss683ZgeNPQf63wRLmXQAgGgWFWUF /REA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Im5u11D8yrAC4qQJy1JnWa+rWzoOJ65BBH7IOoUdIyQ=; b=1Jueo+yLfyVG6FERdW02VEg1uAwbwGI9CENE9nBWw1UM4uE8O9baEi5Dt3l3em0YCm AAMI0c/mlIg7BDmF3teCIwDSWQhf/mnZU+ea3m2m6gcrjs+eBRSy1JYEC8HgNODvSRjh eiH/oeDj1m6R5jmYCLtW9vZMaqqikghOIjA6di8m4Q4M1PFXg9oG9Jmg3fTBJrTyVNpL tdc5C1IfKEmT+4AU4TnVMtJ9Qjx4/wczSACkGsFRFarwVKNmgwrK7Uh80rUr5+dLdQ8k 3OZ4ihD77jPBR09kOdCzrQNMoeknUtYyyKIS7BfAprwcgQJXK/Oa1xxOVOLg1PyajRsj bgtQ== X-Gm-Message-State: AOAM532cUvZie8pfcpRQCrCeeQZx7hc4DPHDjck7iGtEegI8XATEfYL/ 61m7qg/O7+Q/TNdxRf2Nnep6Su9RBYCKXA== X-Google-Smtp-Source: ABdhPJztOTWuxigdF6S82pW04d73OUGOO+/htgbPeJ2571ErGkqzHGkr3CQII9XXiGt8yB1XQMyiDg== X-Received: by 2002:a05:6a00:1a87:b0:51c:29f1:13a0 with SMTP id e7-20020a056a001a8700b0051c29f113a0mr9000697pfv.13.1654634019983; Tue, 07 Jun 2022 13:33:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 35/71] target/arm: Move arm_cpu_*_finalize to internals.h Date: Tue, 7 Jun 2022 13:32:30 -0700 Message-Id: <20220607203306.657998-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654636808891100001 Content-Type: text/plain; charset="utf-8" Drop the aa32-only inline fallbacks, and just use a couple of ifdefs. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 6 ------ target/arm/internals.h | 3 +++ target/arm/cpu.c | 2 ++ 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4e86d143c8..25a77ec676 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -205,14 +205,8 @@ typedef struct { =20 #ifdef TARGET_AARCH64 # define ARM_MAX_VQ 16 -void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); -void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); #else # define ARM_MAX_VQ 1 -static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } -static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } -static inline void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { } #endif =20 typedef struct ARMVectorReg { diff --git a/target/arm/internals.h b/target/arm/internals.h index 8bac570475..756301b536 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1309,6 +1309,9 @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *= buf, int reg); int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); +void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); +void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); +void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); #endif =20 #ifdef CONFIG_USER_ONLY diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1b5d535788..b5276fa944 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1421,6 +1421,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **e= rrp) { Error *local_err =3D NULL; =20 +#ifdef TARGET_AARCH64 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { arm_cpu_sve_finalize(cpu, &local_err); if (local_err !=3D NULL) { @@ -1440,6 +1441,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **e= rrp) return; } } +#endif =20 if (kvm_enabled()) { kvm_arm_steal_time_finalize(cpu, &local_err); --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654637103; cv=none; d=zohomail.com; s=zohoarc; b=Ob3LriE2VqR1eHXXkR0uJMpmZWaEUEiuO0XtvkhJSwWcTX1h7cy9haWg0gCFW0huLKU8yU2n+Aa6ozndf6Ui/rxO68R474tskp02oqPitZY4F0D3zH6UPoJMazVZSRhYGHgnQbfCPo5uFAVMWUAOFYPS4XL6Tf0bb6V1Zace2FE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654637103; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lr8nU07ATHOfF6fXY/tNxkqqDhGq3qxiduBu16rymxM=; b=OxseJ4fxVHEBQZJ7rqyFxWqSPp/6qvpyzjBTvIIQT/zlCHZ0aogOyUbC8c6RsFz6nSrUlP6hPNIrLeK/MxYgKXgLy+kj8Wl5D79FlRBnamlpqLasct5T4ltiGL8q5WSIrCxtKDNXU95gLM3BiFcSVslQQhyGPh32NWG+/lHU+qU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165463710384446.06375306841221; Tue, 7 Jun 2022 14:25:03 -0700 (PDT) Received: from localhost ([::1]:37308 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyghC-00016j-Ay for importer@patchew.org; Tue, 07 Jun 2022 17:25:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34552) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfte-0000Nm-KG for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:50 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:34697) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftW-0007TZ-K8 for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:50 -0400 Received: by mail-pg1-x529.google.com with SMTP id g186so8076296pgc.1 for ; Tue, 07 Jun 2022 13:33:41 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lr8nU07ATHOfF6fXY/tNxkqqDhGq3qxiduBu16rymxM=; b=NV6/dE+rxePGYSNNSPx0QSoT9PYlQKsOvAAYE9It/RcORdGiNZiKJf+YvBNdykBatE kjeTFKW1aTTZf6Z0fLwcdnQPtkBNJTuYOhezoM4xbk4leZxZwIjAmieboJgT0vlYZTJs mj/WQWCRKzZeTXJkNgPlCz05aTXCPNOdlHZGRfYu9rQPA+DYNndOZFq5PDK+fIy1OMiK /jcEHDAqe5W7G3RhbmMmxvKATbNjkTFqiR3/G3945A7RvIuHDD9S2txCpjOR141X5NUv FKzH3dlWp17FdAe6T1JS7Ps/mkJcIKbvu5gRURsukvkinJzH6Y+M2uSzuNloUoVTs+R2 9hTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lr8nU07ATHOfF6fXY/tNxkqqDhGq3qxiduBu16rymxM=; b=l0ULRnZ+7mbZ1fPSXovyGdueTpCxgtWbJRughM//2vg+LQcZRayOO3W2Fq2VwZbSK4 YBcPSwgcgEYukDxihgD5DQTLPejWufGy97HDNK3brm5R3iZyFWxDwluPJx/FZqaakZ/m HJIpgZQs1feokhF+se1lNWJJfZJ5GOZ4Z6BcgknMqt89zaBe6h6/vDgJpNvLyqL+1+l5 XXDqgb5p0Yf6s7rIbMRrTSFKv/ezVyGIVmcyFZKyMfAlK8yB8qiwiW6PHA4oYWvMQ9qb ownjyjXx3AklTOYeEc7MzCTNIDYYFRWhrwLMx1mt5nWrLskH7ntTsJsntZMJNi7N+Zqy 4K8Q== X-Gm-Message-State: AOAM533wTonuNWO1JkATvdatdFgN5LuOAawRXw/AHF9UpOaI9pY1AnGw OO+rMeUiPuY3gbyibL4y+e5chaVRhMqbig== X-Google-Smtp-Source: ABdhPJy+1ZjyMMzUyYRTZu+11oq9JszN1lp0fgReFYZxgmBikQYtXiBQe6xuGYFixKkFky3s7fTV1w== X-Received: by 2002:a63:480c:0:b0:3fa:7277:bf34 with SMTP id v12-20020a63480c000000b003fa7277bf34mr27186216pga.35.1654634020767; Tue, 07 Jun 2022 13:33:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 36/71] target/arm: Unexport aarch64_add_*_properties Date: Tue, 7 Jun 2022 13:32:31 -0700 Message-Id: <20220607203306.657998-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654637106060100001 Content-Type: text/plain; charset="utf-8" These functions are not used outside cpu64.c, so make them static. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 3 --- target/arm/cpu64.c | 4 ++-- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 25a77ec676..8a89548cb9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1097,8 +1097,6 @@ int aarch64_cpu_gdb_write_register(CPUState *cpu, uin= t8_t *buf, int reg); void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el, bool el0_a64); -void aarch64_add_sve_properties(Object *obj); -void aarch64_add_pauth_properties(Object *obj); void arm_reset_sve_state(CPUARMState *env); =20 /* @@ -1130,7 +1128,6 @@ static inline void aarch64_sve_narrow_vq(CPUARMState = *env, unsigned vq) { } static inline void aarch64_sve_change_el(CPUARMState *env, int o, int n, bool a) { } -static inline void aarch64_add_sve_properties(Object *obj) { } #endif =20 void aarch64_sync_32_to_64(CPUARMState *env); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c5bfc3d082..9ae9be6698 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -689,7 +689,7 @@ static void cpu_arm_get_default_vec_len(Object *obj, Vi= sitor *v, } #endif =20 -void aarch64_add_sve_properties(Object *obj) +static void aarch64_add_sve_properties(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); uint32_t vq; @@ -752,7 +752,7 @@ static Property arm_cpu_pauth_property =3D static Property arm_cpu_pauth_impdef_property =3D DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); =20 -void aarch64_add_pauth_properties(Object *obj) +static void aarch64_add_pauth_properties(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); =20 --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654637497; cv=none; d=zohomail.com; s=zohoarc; b=O0ho3mRcSMmehErOLSbSuWfcqTqlPcSjx/NXbWkmJBn/0mETs0CGZjIUGZ2lRGsMRi6sDJKboERq9cPoY8tnCCJr49G41VI5L8NUgBA8W0YrjRUwhtGy4KKDToKsejiXIl9Kv8cOQ/rlwlM57gE5+JrDLA67KAG9gDzn541bmcc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654637497; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=d0wqTPEvX0ysSyrnbJpTcraL6n1BQisJ52WpRbhHsec=; b=H14RnTT1T+0jSzssRRjgudPgbk2+D70J8v1e0ammvpYhpmRfdi+JZ6J7mw1RuT5zXIVETDjMB0IBK9u7BzIsB7km06FwMC3G2TKBK5Fuglq0v5/+b4qLfUlBhnHelrp2IEqKWIVDM2ozKwq0CbLZjuVamvASZFmzkze8+i+taFQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165463749747242.2316299642938; Tue, 7 Jun 2022 14:31:37 -0700 (PDT) Received: from localhost ([::1]:47100 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygnX-00084H-UM for importer@patchew.org; Tue, 07 Jun 2022 17:31:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34588) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftf-0000T0-Vc for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:52 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:40832) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftY-0007U0-3Z for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:51 -0400 Received: by mail-pg1-x533.google.com with SMTP id f65so6752832pgc.7 for ; Tue, 07 Jun 2022 13:33:43 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d0wqTPEvX0ysSyrnbJpTcraL6n1BQisJ52WpRbhHsec=; b=B40VK5bkqr0Ay1CTdRdtLLnTlao52fVejvRaP+WLvEiDJynNUSijrt4pCd+MbuYUdz o/FgjUYKpcCe9iHhLEG/FsddP3AxgQ9RYrNv8rOrpbT1iZtyZWbiY//bw3AZd1GR44Dw 6XeQbQnz8KYkL/WyQ2+WKsbyVxn6uiFEf8SgtP2vxj9VH1IEDfNKI4bh9zU6m2joPC9y AtW96K8/AA/8RPvzB7SPjxxiLuZKzGjAuE2vO5FOkdUy4tdrcb+wSHMOToP6pRcXh0HG ygqKkdD9A16Kszo6og7XNvB0QuntSBryvzYSAi31NePvi5PoIXCxXMmpVZV9i9ui2zIA SwRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d0wqTPEvX0ysSyrnbJpTcraL6n1BQisJ52WpRbhHsec=; b=rbGv6d5pXmEf0xUJ/MkfrskjLFPbUTw3V+IuWDDX254gZw5JOyBEw+qBLleZ8E8Hzb k05r9rBJ6NcfaFQcTnumUfXiSpCDO14eO9lF2OrCpQ+OFfZ2tPT8PQ1CVijVVkTGECXw Kt09JLqJcNUUDzkmMUAsU8pvlj6BR2OLnVC2nkzMhPNhvlabHRlbu8aDJTuo72pAKpBI ZegWk/uQduAaACkOSDA50sQnfwytysfcBacZyRLBBV7mrTY1mDo7b3i66CXG3JKBj8/T lsugl1vdmHHy/vE8l7LdPoxESc0c94t4CqL6qBHVGfMxERW4Z4EUMbcRhA4isdz2aGOe gQ1g== X-Gm-Message-State: AOAM533U5eCmk/bksPD419qjsjeE0ffH4omK7A051XgjkAcgsgvnVCJY CHiq7Js7xyAHyOGDDKLmxyiM7JdU70ed4Q== X-Google-Smtp-Source: ABdhPJwWA4IbF0bvoacI79bjYYhY+2nm9TKgBrfCc4KuDh+NymrSjkYNADoCHYEAf7jNtih2fOXoxg== X-Received: by 2002:a05:6a00:164c:b0:50a:472a:6b0a with SMTP id m12-20020a056a00164c00b0050a472a6b0amr31234667pfc.77.1654634021655; Tue, 07 Jun 2022 13:33:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 37/71] target/arm: Add cpu properties for SME Date: Tue, 7 Jun 2022 13:32:32 -0700 Message-Id: <20220607203306.657998-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654637498394100001 Content-Type: text/plain; charset="utf-8" Mirror the properties for SVE. The main difference is that any arbitrary set of powers of 2 may be supported, and not the stricter constraints that apply to SVE. Include a property to control FEAT_SME_FA64, as failing to restrict the runtime to the proper subset of insns could be a major point for bugs. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 + target/arm/internals.h | 1 + target/arm/cpu.c | 14 +++-- target/arm/cpu64.c | 114 +++++++++++++++++++++++++++++++++++++++-- 4 files changed, 124 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8a89548cb9..d81d1bedf9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1046,9 +1046,11 @@ struct ArchCPU { #ifdef CONFIG_USER_ONLY /* Used to set the default vector length at process start. */ uint32_t sve_default_vq; + uint32_t sme_default_vq; #endif =20 ARMVQMap sve_vq; + ARMVQMap sme_vq; =20 /* Generic timer counter frequency, in Hz */ uint64_t gt_cntfrq_hz; diff --git a/target/arm/internals.h b/target/arm/internals.h index 756301b536..7e160d1349 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1310,6 +1310,7 @@ int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf= , int reg); int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); +void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b5276fa944..75295a14a3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1122,11 +1122,13 @@ static void arm_cpu_initfn(Object *obj) #ifdef CONFIG_USER_ONLY # ifdef TARGET_AARCH64 /* - * The linux kernel defaults to 512-bit vectors, when sve is supported. - * See documentation for /proc/sys/abi/sve_default_vector_length, and - * our corresponding sve-default-vector-length cpu property. + * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. + * These values were chosen to fit within the default signal frame. + * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, + * and our corresponding cpu property. */ cpu->sve_default_vq =3D 4; + cpu->sme_default_vq =3D 2; # endif #else /* Our inbound IRQ and FIQ lines */ @@ -1429,6 +1431,12 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **= errp) return; } =20 + arm_cpu_sme_finalize(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + arm_cpu_pauth_finalize(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9ae9be6698..aaf2c243d6 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -589,10 +589,13 @@ static void cpu_arm_get_vq(Object *obj, Visitor *v, c= onst char *name, ARMCPU *cpu =3D ARM_CPU(obj); ARMVQMap *vq_map =3D opaque; uint32_t vq =3D atoi(&name[3]) / 128; + bool sve =3D vq_map =3D=3D &cpu->sve_vq; bool value; =20 - /* All vector lengths are disabled when SVE is off. */ - if (!cpu_isar_feature(aa64_sve, cpu)) { + /* All vector lengths are disabled when feature is off. */ + if (sve + ? !cpu_isar_feature(aa64_sve, cpu) + : !cpu_isar_feature(aa64_sme, cpu)) { value =3D false; } else { value =3D extract32(vq_map->map, vq - 1, 1); @@ -636,8 +639,80 @@ static void cpu_arm_set_sve(Object *obj, bool value, E= rror **errp) cpu->isar.id_aa64pfr0 =3D t; } =20 +void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) +{ + uint32_t vq_map =3D cpu->sme_vq.map; + uint32_t vq_init =3D cpu->sme_vq.init; + uint32_t vq_supported =3D cpu->sme_vq.supported; + uint32_t vq; + + if (vq_map =3D=3D 0) { + if (!cpu_isar_feature(aa64_sme, cpu)) { + cpu->isar.id_aa64smfr0 =3D 0; + return; + } + + /* TODO: KVM will require limitations via SMCR_EL2. */ + vq_map =3D vq_supported & ~vq_init; + + if (vq_map =3D=3D 0) { + vq =3D ctz32(vq_supported) + 1; + error_setg(errp, "cannot disable sme%d", vq * 128); + error_append_hint(errp, "All SME vector lengths are disabled.\= n"); + error_append_hint(errp, "With SME enabled, at least one " + "vector length must be enabled.\n"); + return; + } + } else { + if (!cpu_isar_feature(aa64_sme, cpu)) { + vq =3D 32 - clz32(vq_map); + error_setg(errp, "cannot enable sme%d", vq * 128); + error_append_hint(errp, "SME must be enabled to enable " + "vector lengths.\n"); + error_append_hint(errp, "Add sme=3Don to the CPU property list= .\n"); + return; + } + /* TODO: KVM will require limitations via SMCR_EL2. */ + } + + cpu->sme_vq.map =3D vq_map; +} + +static bool cpu_arm_get_sme(Object *obj, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + return cpu_isar_feature(aa64_sme, cpu); +} + +static void cpu_arm_set_sme(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + uint64_t t; + + t =3D cpu->isar.id_aa64pfr1; + t =3D FIELD_DP64(t, ID_AA64PFR1, SME, value); + cpu->isar.id_aa64pfr1 =3D t; +} + +static bool cpu_arm_get_sme_fa64(Object *obj, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + return cpu_isar_feature(aa64_sme, cpu) && + cpu_isar_feature(aa64_sme_fa64, cpu); +} + +static void cpu_arm_set_sme_fa64(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + uint64_t t; + + t =3D cpu->isar.id_aa64smfr0; + t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, value); + cpu->isar.id_aa64smfr0 =3D t; +} + #ifdef CONFIG_USER_ONLY -/* Mirror linux /proc/sys/abi/sve_default_vector_length. */ +/* Mirror linux /proc/sys/abi/{sve,sme}_default_vector_length. */ static void cpu_arm_set_default_vec_len(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) @@ -663,7 +738,11 @@ static void cpu_arm_set_default_vec_len(Object *obj, V= isitor *v, * and is the maximum architectural width of ZCR_ELx.LEN. */ if (remainder || default_vq < 1 || default_vq > 512) { - error_setg(errp, "cannot set sve-default-vector-length"); + ARMCPU *cpu =3D ARM_CPU(obj); + const char *which =3D + (ptr_default_vq =3D=3D &cpu->sve_default_vq ? "sve" : "sme"); + + error_setg(errp, "cannot set %s-default-vector-length", which); if (remainder) { error_append_hint(errp, "Vector length not a multiple of 16\n"= ); } else if (default_vq < 1) { @@ -712,6 +791,31 @@ static void aarch64_add_sve_properties(Object *obj) #endif } =20 +static void aarch64_add_sme_properties(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t vq; + + object_property_add_bool(obj, "sme", cpu_arm_get_sme, cpu_arm_set_sme); + object_property_add_bool(obj, "sme_fa64", cpu_arm_get_sme_fa64, + cpu_arm_set_sme_fa64); + + for (vq =3D 1; vq <=3D ARM_MAX_VQ; vq <<=3D 1) { + char name[8]; + sprintf(name, "sme%d", vq * 128); + object_property_add(obj, name, "bool", cpu_arm_get_vq, + cpu_arm_set_vq, NULL, &cpu->sme_vq); + } + +#ifdef CONFIG_USER_ONLY + /* Mirror linux /proc/sys/abi/sme_default_vector_length. */ + object_property_add(obj, "sme-default-vector-length", "int32", + cpu_arm_get_default_vec_len, + cpu_arm_set_default_vec_len, NULL, + &cpu->sme_default_vq); +#endif +} + void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { int arch_val =3D 0, impdef_val =3D 0; @@ -976,9 +1080,11 @@ static void aarch64_max_initfn(Object *obj) #endif =20 cpu->sve_vq.supported =3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); + cpu->sme_vq.supported =3D SVE_VQ_POW2_MAP; =20 aarch64_add_pauth_properties(obj); aarch64_add_sve_properties(obj); + aarch64_add_sme_properties(obj); object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_v= q, cpu_max_set_sve_max_vq, NULL, NULL); qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654636726; cv=none; d=zohomail.com; s=zohoarc; b=kUvEjWuHU9Jf2L3UT9SKNdQXEQU1ei/bUCvMUT9cJHWUYcp36yJF/0MG1r/isLC6B47eTG/AbideHgh3n5HlbH3zO1BxKgkPChc6kiKPkUwGZ8fzKb3EKh8+MpaD9SMFyg4oy+Kyr286MQbZLMf7zHHEismPnB5n3Xd/8OLsZPA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654636726; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WYa9Ij7DGXX4UaDE3YZGCzVfYSAzgGKdab54muYOC2Q=; b=i9U6BiGLjOmddRkVpKBAsE19ZeKGTKuc4T8vU3+65JHGBA1nHp5a6BoYLnr9O4lVBVC+NGPC+FN5YUNwAHI+BcOXk6xfBK41geuk5JfGrPvI1m38QFnCfSMlwLpHEivdhNeM2ybN7GK64WN+QeTMonlhwfVPh3ZM22I/duVMpKs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654636726874245.40251156353497; Tue, 7 Jun 2022 14:18:46 -0700 (PDT) Received: from localhost ([::1]:55548 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygb7-0002Rq-Gj for importer@patchew.org; Tue, 07 Jun 2022 17:18:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34628) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfti-0000d0-HZ for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:54 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:44585) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftX-0007U9-Uj for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:54 -0400 Received: by mail-pg1-x52f.google.com with SMTP id c18so8625520pgh.11 for ; Tue, 07 Jun 2022 13:33:43 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WYa9Ij7DGXX4UaDE3YZGCzVfYSAzgGKdab54muYOC2Q=; b=P/SdpQ+7mvHVs1z6glcl6s4SaN7KF6induAAqWnrxC6C4PW667b4UZQvzF+7k5KnhP 0/uwtjEGTjfFwPk6gK8+ag4f6bPnGYRs1k+acE/63SuK4fWd2B9cf571nUqYc3rvZgAT 5W0hAmRmQDah6CO4dO19uah+puT0l3JDnlqpbmSoLWRav1gqHPTXLmAHxywuH4dJvQVj pV+0wOBs0/zJ9XU0u5sEbc39tZATL3AIwqVanrcPTmjneQoxWYRBigmjmPYs3BRBxi8+ uI63sPaeqK24CkrBI9xKBJj9906wunMRtReLitB/HexZY2GP4q4MhW46NesVVfjUb2Nt Q60w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WYa9Ij7DGXX4UaDE3YZGCzVfYSAzgGKdab54muYOC2Q=; b=nHJRienV+rMMVydgW0N6dXUxLq2Ctkt45AFORhuUm1w71obeD8Jg3k1+UHLiTVUBW0 cdBsYZa9G30mgufXMEkPGmp8Wi/d8fUDEMjauAtmZE+cWpNm3BBmhgZ8kfKjxLS/Myoq ZElDtS5agPGbsD0JZ0BceKtgIKRQPVrA+N0s/AYqB5MTFGEEEmOHDfacYxqZvzdeMW6h GPJtUh5rXEQLdQw5GEZJvb6oetvF0rT6iGxqsXgXAEQkS9A4A3h9dnHIPfPY0YIvjBcW 6vEofsv7ROKBEcPgUmUYKh5FZU6SrVe/cQ1Lv/Elrzuulu0e4VXX0xv114XvCjMFtoRE 1OCg== X-Gm-Message-State: AOAM530ANdRCIkYTHGeFucKe8BauuLodMGX6m0aXuSNFGUeqhlKFpmi/ IopiPKvLrZnIfBFLMdtoJCzwOgBEye4ECw== X-Google-Smtp-Source: ABdhPJyjHBd2YlPpmyqSt4kq3X5sN1Mj1rhvfjpQdX5m9302FIauPj9H2i1nKnyJPvAu+VyGa6IHag== X-Received: by 2002:a63:8241:0:b0:3fe:2e64:95f0 with SMTP id w62-20020a638241000000b003fe2e6495f0mr133653pgd.190.1654634022703; Tue, 07 Jun 2022 13:33:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 38/71] target/arm: Introduce sve_vqm1_for_el_sm Date: Tue, 7 Jun 2022 13:32:33 -0700 Message-Id: <20220607203306.657998-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654636728501100001 Content-Type: text/plain; charset="utf-8" When Streaming SVE mode is enabled, the size is taken from SMCR_ELx instead of ZCR_ELx. The format is shared, but the set of vector lengths is not. Further, Streaming SVE does not require any particular length to be supported. Adjust sve_vqm1_for_el to pass the current value of PSTATE.SM to the new function. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 9 +++++++-- target/arm/helper.c | 32 +++++++++++++++++++++++++------- 2 files changed, 32 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d81d1bedf9..d7d364abbb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1140,13 +1140,18 @@ int sve_exception_el(CPUARMState *env, int cur_el); int sme_exception_el(CPUARMState *env, int cur_el); =20 /** - * sve_vqm1_for_el: + * sve_vqm1_for_el_sm: * @env: CPUARMState * @el: exception level + * @sm: streaming mode * - * Compute the current SVE vector length for @el, in units of + * Compute the current vector length for @el & @sm, in units of * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. + * If @sm, compute for SVL, otherwise NVL. */ +uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); + +/* Likewise, but using @sm =3D PSTATE.SM. */ uint32_t sve_vqm1_for_el(CPUARMState *env, int el); =20 static inline bool is_a64(CPUARMState *env) diff --git a/target/arm/helper.c b/target/arm/helper.c index e3f3e4dfc2..b1ca819597 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6276,23 +6276,41 @@ int sme_exception_el(CPUARMState *env, int el) /* * Given that SVE is enabled, return the vector length for EL. */ -uint32_t sve_vqm1_for_el(CPUARMState *env, int el) +uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm) { ARMCPU *cpu =3D env_archcpu(env); - uint32_t len =3D cpu->sve_max_vq - 1; + uint64_t *cr =3D env->vfp.zcr_el; + uint32_t map =3D cpu->sve_vq.map; + uint32_t len =3D ARM_MAX_VQ - 1; + + if (sm) { + cr =3D env->vfp.smcr_el; + map =3D cpu->sme_vq.map; + } =20 if (el <=3D 1 && !el_is_in_host(env, el)) { - len =3D MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[1]); + len =3D MIN(len, 0xf & (uint32_t)cr[1]); } if (el <=3D 2 && arm_feature(env, ARM_FEATURE_EL2)) { - len =3D MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[2]); + len =3D MIN(len, 0xf & (uint32_t)cr[2]); } if (arm_feature(env, ARM_FEATURE_EL3)) { - len =3D MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[3]); + len =3D MIN(len, 0xf & (uint32_t)cr[3]); } =20 - len =3D 31 - clz32(cpu->sve_vq.map & MAKE_64BIT_MASK(0, len + 1)); - return len; + map &=3D MAKE_64BIT_MASK(0, len + 1); + if (map !=3D 0) { + return 31 - clz32(map); + } + + /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */ + assert(sm); + return ctz32(cpu->sme_vq.map); +} + +uint32_t sve_vqm1_for_el(CPUARMState *env, int el) +{ + return sve_vqm1_for_el_sm(env, el, FIELD_EX64(env->svcr, SVCR, SM)); } =20 static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654635970; cv=none; d=zohomail.com; s=zohoarc; b=VH1ONfMGBT/sAag7f5aMeRwlzhmNYdWzZSkma0gWvfGkY2hpxdVKdatya+KI8UyRHVy4bt2GKW0oL5yFfEh4ZOCqgnZPRUuuze5fJnT+gCcX8uVOqVaxSBs78imn1GyV8vfuZmcljoG0uPpF7y4ecFruKujBn0DTi0cR2WQw9bc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654635970; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/BExpvNtfeOaLygKWpS4gykSxDaWFRszDLVZHG0ddOs=; b=iObxhW+Qzx2XJXwcXPdAhkbqHE4egKtb+hgu4H8HOjeg+8SQ0SzKzNwYTYM1w9Wg78RHWWtljnAEzrX9TMWupQcCMbtgqtfS6eBBSZeMgsy0WTRxUUXtKyxyrauYLZqwJb22FSdZ3vV60Qs/lwyFv+Qsa0b5nUU4bvWjo/Q+Jes= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654635970586811.7773491268402; Tue, 7 Jun 2022 14:06:10 -0700 (PDT) Received: from localhost ([::1]:58372 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygOv-0001Ve-Ef for importer@patchew.org; Tue, 07 Jun 2022 17:06:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34594) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyftg-0000TN-2j for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:52 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:33553) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyftY-0007UU-Rn for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:33:51 -0400 Received: by mail-pl1-x62f.google.com with SMTP id f9so5339584plg.0 for ; Tue, 07 Jun 2022 13:33:44 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s22-20020a17090aba1600b001d9780b7779sm4227856pjr.15.2022.06.07.13.33.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:33:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/BExpvNtfeOaLygKWpS4gykSxDaWFRszDLVZHG0ddOs=; b=rJGZ3JN4OKBU1KQw89iQN+g+iPge1iOVfJsVnWT21IFxVLebZ/EGUO/fOD6Q1Snl1v d1LqkT9atDKjvLT65sQQB7qObN1hGyFKGvzA69t6DOCemPan1SkgQQxdnWs9AF30NFUu QF0vU0W06M3z2nuyu0dWzqzwMS3y4ruTV+fYbtB1tbhvDLEYr3cKVpaVOfJs15Re1ISW WhC53+BKUvgbD6+biN91cI0odEHYH510pB4s5GDdzrA4vhMD7xx2BhwT+pdEbBc/HYS+ iOgyqZt0btkbXwNHfcZVBvzFxwbn3bFPfQzAE7/jd63A51JD++2rH2jSoJ7SNRVOEfU1 mFlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/BExpvNtfeOaLygKWpS4gykSxDaWFRszDLVZHG0ddOs=; b=AhL/613ZUy2PoclmeI1q6a8tuG6w7uaV+OOdn7jQqrtEu2cVw3+wg5ic5jXhowAlu2 Jv6cuBPnQ4YjHh6l5VxJRmVekKMOJwmxt+mZn91GrOmfmQWt9jqZiUz9vaBWD+01k+KS jwo+iYUZSElrWuMMSLs7XiUz1EhFzjeIQQLGik45rwMnk6yxs7rHZG/IGbqsC9xBEMQ6 D6SMZro4nJ1kntInTeI42HWfwj0srGcDdeai3sJ7djQM7DjK2nrIujTm0nJg/Ykovw9R 0g4FnHZv2W1/yp9Zdz8P0giUy+6jug5TvZGTCJoq2IE2kDVkdpk5ByaUu7MdFAO5J1J0 uVjg== X-Gm-Message-State: AOAM533YbrwvYzcw5IsWWLWr0FrKzifjkUnZH3381gSGeTflJyV+vrPA TZYdk2E0fSQ8BJ+xYeajI0NMA2Ytpw3eAw== X-Google-Smtp-Source: ABdhPJzKQACKGA3zPxfMzfjEMNmp1PMQh/aNXH2PcoP2g3MipoPuOQBuFf6mx5bY7JNh+GENsFpsjA== X-Received: by 2002:a17:90a:df16:b0:1e3:1cd:6c6f with SMTP id gp22-20020a17090adf1600b001e301cd6c6fmr50299220pjb.10.1654634023471; Tue, 07 Jun 2022 13:33:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 39/71] target/arm: Add SVL to TB flags Date: Tue, 7 Jun 2022 13:32:34 -0700 Message-Id: <20220607203306.657998-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654635972540100001 Content-Type: text/plain; charset="utf-8" We need SVL separate from VL for RDSVL at al, as well as ZA storage loads and stores, which do not require PSTATE.SM. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 12 ++++++++++++ target/arm/translate.h | 1 + target/arm/helper.c | 8 +++++++- target/arm/translate-a64.c | 1 + 4 files changed, 21 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d7d364abbb..23d46c7d7d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3292,6 +3292,7 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) +FIELD(TBFLAG_A64, SVL, 24, 4) =20 /* * Helpers for using the above. @@ -3337,6 +3338,17 @@ static inline int sve_vq(CPUARMState *env) return EX_TBFLAG_A64(env->hflags, VL) + 1; } =20 +/** + * sme_vq + * @env: the cpu context + * + * Return the SVL cached within env->hflags, in units of quadwords. + */ +static inline int sme_vq(CPUARMState *env) +{ + return EX_TBFLAG_A64(env->hflags, SVL) + 1; +} + static inline bool bswap_code(bool sctlr_b) { #ifdef CONFIG_USER_ONLY diff --git a/target/arm/translate.h b/target/arm/translate.h index fbd6713572..1330281f8b 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -44,6 +44,7 @@ typedef struct DisasContext { int sve_excp_el; /* SVE exception EL or 0 if enabled */ int sme_excp_el; /* SME exception EL or 0 if enabled */ int vl; /* current vector length in bytes */ + int svl; /* current streaming vector length in bytes */ /* Flag indicating that exceptions from secure mode are routed to EL3.= */ bool secure_routed_to_el3; bool vfp_enabled; /* FP enabled via FPSCR.EN */ diff --git a/target/arm/helper.c b/target/arm/helper.c index b1ca819597..2b38e82c22 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13874,7 +13874,13 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMStat= e *env, int el, int fp_el, DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); } if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { - DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el)); + int sme_el =3D sme_exception_el(env, el); + + DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el); + if (sme_el =3D=3D 0) { + /* Similarly, do not compute SVL if SME is disabled. */ + DP_TBFLAG_A64(flags, SVL, sve_vqm1_for_el_sm(env, el, true)); + } if (FIELD_EX64(env->svcr, SVCR, SM)) { DP_TBFLAG_A64(flags, PSTATE_SM, 1); } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 40f2e53983..b1d2840819 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14652,6 +14652,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->sve_excp_el =3D EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sme_excp_el =3D EX_TBFLAG_A64(tb_flags, SMEEXC_EL); dc->vl =3D (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; + dc->svl =3D (EX_TBFLAG_A64(tb_flags, SVL) + 1) * 16; dc->pauth_active =3D EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); dc->bt =3D EX_TBFLAG_A64(tb_flags, BT); dc->btype =3D EX_TBFLAG_A64(tb_flags, BTYPE); --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654637395709312.38141752878164; Tue, 7 Jun 2022 14:29:55 -0700 (PDT) Received: from localhost ([::1]:44846 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyglu-0006Xk-Hm for importer@patchew.org; Tue, 07 Jun 2022 17:29:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35600) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfwb-0006O1-UG for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:36:54 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:35697) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfwU-0008DH-5b for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:36:53 -0400 Received: by mail-pj1-x102f.google.com with SMTP id o6-20020a17090a0a0600b001e2c6566046so21938892pjo.0 for ; Tue, 07 Jun 2022 13:36:45 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.36.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:36:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nRiBuDw8xOiappiLJwDebAsj0dPMzIOBq+w1XQpJT0Q=; b=QLDWXpE8up/O5B4CSnNCMsB3GaGriyBjzSU1f6JAX9+dwTlN0N4NRfotk3OZhZYM4I WY1dECOkMy0TgaiCagsKQ6aJoF8mqlm+nfe+pfpJV1/yxcRKu1VJEtdA3YgReXesMbzL Wd0thSlToEiJWbVJOwboxqiDL4gwvZiCXZ0DIQUKR7YhJ3Ub3NxjVVZ/alf50rgRx2dK Y62lc9DZtkxGaHl8x6i5hMfnGwvBGQyjQIyLsHkUHEvhBnAIY+zZTDVtPgJQhvcwRmSd 8cV/O4tvceXzA2dnc7UDPvJynsBJ3hvunqM1gQwXWA1aI5Mr2R/Q71xM7zaEMiv44RhJ PMqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nRiBuDw8xOiappiLJwDebAsj0dPMzIOBq+w1XQpJT0Q=; b=EP+FsVEJ9nNNiTcKGHa0gAPQuIRyv7FjzlJsh9ib7Lm7e+PJ37rPVlOwcFRkEATUFS 2Uy/b4Rb7UP7sYEuSc+kNcZrvK3AiPPTTLMh4/dZtTPW5ttmSmKj7T5bHYTTgCU581wQ rSRU4i6Wjoxv+bBDjUR8CELPUKFrFQxtnudJjJQlRGx/7afZSgIp8H3H5Q+6qLl/CEdH xj8FcaOsB++sauZz7t5v+a3FoqNQjPC2AvCeYdkvKOMFZ4c65SeHJq5dJkdOEJ3S0LN/ GzbP3/DOLzfz800VJYHEp7hapB7w9oNhunfSlCBiMMYmYjydewBezUxcXkKAX9x9ZWSW Jaow== X-Gm-Message-State: AOAM533pey4FILRpv8kv3DLJAmHOvKt+WaiKj+IzVzxo6SbNUZCCXTqA kQ0MQJJ90QYtbOkWZN/rHn8DPXOR5H7OiQ== X-Google-Smtp-Source: ABdhPJyozaHS2c5RVDkClduirJi6YzlQ2vXBcvYqiWdsY8d4Lg2JhOrqJBXHQ1RvgSzvsZFuTVZGyA== X-Received: by 2002:a17:90b:1d0a:b0:1e8:7f14:8db with SMTP id on10-20020a17090b1d0a00b001e87f1408dbmr13665038pjb.218.1654634204738; Tue, 07 Jun 2022 13:36:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 40/71] target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.h Date: Tue, 7 Jun 2022 13:32:35 -0700 Message-Id: <20220607203306.657998-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1654637397816100001 Content-Type: text/plain; charset="utf-8" We will need these functions in translate-sme.c. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.h | 38 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 36 ------------------------------------ 2 files changed, 38 insertions(+), 36 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index dbc917ee65..f0970c6b8c 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -107,6 +107,44 @@ static inline int vec_full_reg_size(DisasContext *s) return s->vl; } =20 +/* + * Return the offset info CPUARMState of the predicate vector register Pn. + * Note for this purpose, FFR is P16. + */ +static inline int pred_full_reg_offset(DisasContext *s, int regno) +{ + return offsetof(CPUARMState, vfp.pregs[regno]); +} + +/* Return the byte size of the whole predicate register, VL / 64. */ +static inline int pred_full_reg_size(DisasContext *s) +{ + return s->vl >> 3; +} + +/* + * Round up the size of a register to a size allowed by + * the tcg vector infrastructure. Any operation which uses this + * size may assume that the bits above pred_full_reg_size are zero, + * and must leave them the same way. + * + * Note that this is not needed for the vector registers as they + * are always properly sized for tcg vectors. + */ +static inline int size_for_gvec(int size) +{ + if (size <=3D 8) { + return 8; + } else { + return QEMU_ALIGN_UP(size, 16); + } +} + +static inline int pred_gvec_reg_size(DisasContext *s) +{ + return size_for_gvec(pred_full_reg_size(s)); +} + bool disas_sve(DisasContext *, uint32_t); =20 void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 67761bf2cc..62b5f3040c 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -100,42 +100,6 @@ static inline int msz_dtype(DisasContext *s, int msz) * Implement all of the translator functions referenced by the decoder. */ =20 -/* Return the offset info CPUARMState of the predicate vector register Pn. - * Note for this purpose, FFR is P16. - */ -static inline int pred_full_reg_offset(DisasContext *s, int regno) -{ - return offsetof(CPUARMState, vfp.pregs[regno]); -} - -/* Return the byte size of the whole predicate register, VL / 64. */ -static inline int pred_full_reg_size(DisasContext *s) -{ - return s->vl >> 3; -} - -/* Round up the size of a register to a size allowed by - * the tcg vector infrastructure. Any operation which uses this - * size may assume that the bits above pred_full_reg_size are zero, - * and must leave them the same way. - * - * Note that this is not needed for the vector registers as they - * are always properly sized for tcg vectors. - */ -static int size_for_gvec(int size) -{ - if (size <=3D 8) { - return 8; - } else { - return QEMU_ALIGN_UP(size, 16); - } -} - -static int pred_gvec_reg_size(DisasContext *s) -{ - return size_for_gvec(pred_full_reg_size(s)); -} - /* Invoke an out-of-line helper on 2 Zregs. */ static bool gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn, int rd, int rn, int data) --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654637084; cv=none; d=zohomail.com; s=zohoarc; b=AVxIj1B06DWZefX/d0WPhgGA38mL+aJphVqtm5pKQQkiJG+knUVJk4hxHrb24IWJye+LmnJbh10iBSVmS7a1ZGtO+alJVI+5myrY+Uvlj4bfYzG4XEjhS2Oo3SVgNjRS1wGb8Ne7Fs2/lgssGcHG9TPOdJc/KYKI/EnXBUMviN0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654637084; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cAXNgU4itZ2dsKiiTmySi2ECsBUf4c+rnmlAuTmxdmU=; b=A1aoazgWEtZYtzD+IFuRS1wPKJVpXwl1XFauuL6zrRcGKW42rpej0jS0+3g27DWxN5GXvNDEe+ukqyFz9Kjq+5zdhApvAUsO2Foi6eTdsFwkbVXWblI9HCV9rt+cs/Rjvf64JD0x1Ha7XJwDdfssoHpVICgSOIDdAyLqJEDxJhQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654637084942812.9923393562187; Tue, 7 Jun 2022 14:24:44 -0700 (PDT) Received: from localhost ([::1]:36362 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyggt-0000Pb-PV for importer@patchew.org; Tue, 07 Jun 2022 17:24:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35506) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfwY-0006M4-EL for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:36:51 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:42537) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfwV-0008DU-0y for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:36:49 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d22so15786850plr.9 for ; Tue, 07 Jun 2022 13:36:46 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.36.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:36:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cAXNgU4itZ2dsKiiTmySi2ECsBUf4c+rnmlAuTmxdmU=; b=shkv9biQ1xROZfbWiQQAtQJu+TZv880hKnX232zJm2FcEt7nUhCvgU33I9oyHPxLTS CNPLAOj9BwVyeC+zbXO8LI9kJH5c4Nc1hBP6Hbb6eY5yDpnB0mqSd2YFRcX1dvb/7LrM LpDdIFDaSJlifduZShcm5WiNa8cNPGxYQkGl7W9n5NDBeONlxz2SXeiR0daJzQsGyP8a gBsS/9jWOn6ljOv2vf+g3sZ9RaHvjeV/clda+ShVaF9NAx0GGX/4miDBREnc69IudhOj IbXOPfpMAySj9Bp5ZD6w/rDBpPJjfca1w08nQEM2qvBZJGU1r/dNBSuS7fjuOu3sYd1M LBdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cAXNgU4itZ2dsKiiTmySi2ECsBUf4c+rnmlAuTmxdmU=; b=wAFJ6RiYdIqta2m+pgBsxENrA1WaMnqfGFEc2ejClXZLct2j4NR7Kb7GQQiKFpkceJ 8PTe6i7VCBVP/wx/a0fbR5xmfVIgMaE3URntXF9V6R/2tlo64OlJcyPw9Fswur5IbqM7 H4XvmTDxhQ3tTHRyA5AHe5rbzPqE4UeuMvlXPCQXgrvCOXwQTXxxDZJxdjaYQSZpLiaN ScokjyutBgOpjhmCGuxG9Xp8FsGqylyGuhDk8DiyaFumTdPJ8/5J4N8vP/XUUSQ1y133 sHDpS+z1fKZ9BFOBXLoVX86RYfMGYWI/o7qpWdPyn/S6a+7PoUOkPWwEFyN9WIwJ1pgQ GfbA== X-Gm-Message-State: AOAM533ulmo/S2k8YqnZKQricslEfnppn04cTxlyukND/a6v70VExLo3 SviZQ/oYx8SABV5TzqiVPEv5CHJ2j32Pog== X-Google-Smtp-Source: ABdhPJwg8ACbGqywDLBJu/xZNWd6ZSlREg/9sitDGbmjTPqSDJYQzqY2dc2d/3xJ+RH0fenItah20A== X-Received: by 2002:a17:903:248b:b0:160:f4b0:e663 with SMTP id p11-20020a170903248b00b00160f4b0e663mr30490511plw.49.1654634205692; Tue, 07 Jun 2022 13:36:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 41/71] target/arm: Add infrastructure for disas_sme Date: Tue, 7 Jun 2022 13:32:36 -0700 Message-Id: <20220607203306.657998-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654637086282100001 Content-Type: text/plain; charset="utf-8" This includes the build rules for the decoder, and the new file for translation, but excludes any instructions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.h | 1 + target/arm/translate-a64.c | 7 ++++++- target/arm/translate-sme.c | 35 +++++++++++++++++++++++++++++++++++ target/arm/meson.build | 2 ++ target/arm/sme.decode | 20 ++++++++++++++++++++ 5 files changed, 64 insertions(+), 1 deletion(-) create mode 100644 target/arm/translate-sme.c create mode 100644 target/arm/sme.decode diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index f0970c6b8c..789b6e8e78 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -146,6 +146,7 @@ static inline int pred_gvec_reg_size(DisasContext *s) } =20 bool disas_sve(DisasContext *, uint32_t); +bool disas_sme(DisasContext *, uint32_t); =20 void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b1d2840819..8a38fbc33b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14814,7 +14814,12 @@ static void aarch64_tr_translate_insn(DisasContext= Base *dcbase, CPUState *cpu) } =20 switch (extract32(insn, 25, 4)) { - case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ + case 0x0: + if (!disas_sme(s, insn)) { + unallocated_encoding(s); + } + break; + case 0x1: case 0x3: /* UNALLOCATED */ unallocated_encoding(s); break; case 0x2: diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c new file mode 100644 index 0000000000..786c93fb2d --- /dev/null +++ b/target/arm/translate-sme.c @@ -0,0 +1,35 @@ +/* + * AArch64 SME translation + * + * Copyright (c) 2022 Linaro, Ltd + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" +#include "tcg/tcg-gvec-desc.h" +#include "translate.h" +#include "exec/helper-gen.h" +#include "translate-a64.h" +#include "fpu/softfloat.h" + + +/* + * Include the generated decoder. + */ + +#include "decode-sme.c.inc" diff --git a/target/arm/meson.build b/target/arm/meson.build index 02c91f72bb..c47d86c609 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,5 +1,6 @@ gen =3D [ decodetree.process('sve.decode', extra_args: '--decode=3Ddisas_sve'), + decodetree.process('sme.decode', extra_args: '--decode=3Ddisas_sme'), decodetree.process('neon-shared.decode', extra_args: '--decode=3Ddisas_n= eon_shared'), decodetree.process('neon-dp.decode', extra_args: '--decode=3Ddisas_neon_= dp'), decodetree.process('neon-ls.decode', extra_args: '--decode=3Ddisas_neon_= ls'), @@ -50,6 +51,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'sme_helper.c', 'translate-a64.c', 'translate-sve.c', + 'translate-sme.c', )) =20 arm_softmmu_ss =3D ss.source_set() diff --git a/target/arm/sme.decode b/target/arm/sme.decode new file mode 100644 index 0000000000..c25c031a71 --- /dev/null +++ b/target/arm/sme.decode @@ -0,0 +1,20 @@ +# AArch64 SME instruction descriptions +# +# Copyright (c) 2022 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654637224; cv=none; d=zohomail.com; s=zohoarc; b=TGs4hisXbsLXrlCTcFMivgLCb3vsmGoQKonW4kssLijEPRmT0PHRjwmqTC088xEWFH7/O0iAhhK1PSUzzjcntVq6o8TDLICTVv09O3jY4a5habFFF5cu9Q5/6KyonSrDbDqbtSAof/7I1uNOIokmZ+Giu52wu8j6I48lfonvCF0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654637224; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=o4dPAx13CZAyM8P8W5/hpq9Dd6DtRbN5hoPmVjUWD/E=; b=jBLEPxTZVgjXWOy/oX4hvowS12B+FiiJjo6JciHc7x+6Ih6it+HrN/siSGjzWizSDU5vWR6jvpyV8KpBU6buw67wMf66B+U9nEE/lC6+Lu+mXSqA494GCnl0JJmiKlduKbJLf/6d9zZtbQkVkM0B2YA8oeIMSF6vraUwDvXY9yQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654637224972693.1692472857513; Tue, 7 Jun 2022 14:27:04 -0700 (PDT) Received: from localhost ([::1]:38896 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygj9-0002FC-5c for importer@patchew.org; Tue, 07 Jun 2022 17:27:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35640) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfwd-0006Oe-4t for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:36:55 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:38410) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfwV-0008Dd-WB for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:36:54 -0400 Received: by mail-pl1-x62e.google.com with SMTP id n18so15808341plg.5 for ; Tue, 07 Jun 2022 13:36:47 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.36.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:36:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=o4dPAx13CZAyM8P8W5/hpq9Dd6DtRbN5hoPmVjUWD/E=; b=R24yctcwKqHCsmiNTaetdgiI+TxGPBThybxb9fHJit9k2TYJekC/oOR28B5wjKPAnG ix6sI5nqxVnX8PNfN80hDIL0hu2NZBuckJexy3V6an6wF7kV0XaXZ+7BAfJfNMtZ//O2 PzLeKYlgu6lJI9djOCrkoJy//ikBAowC06blUKhO24XSkRw6a+E4sd5vSeQXgy62L64G X4bn9NTYOPZ+ZhoCtpiHYT9hMU98cpuJpZa3pVwKKfO3MjJA8dqY3io4kTW8eBzLMH01 2H/LcGiuHnJQNdG1U+VG6y0eKeSO2q0J2ANAFXkNuIW9Z36WfYZ23y2GKM9hlmjUUOT0 Jtnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o4dPAx13CZAyM8P8W5/hpq9Dd6DtRbN5hoPmVjUWD/E=; b=u9kPIQ+kmZZKSyFgb4kjHwkNbCK47ALAdLRktyZ+pkSLykmZA5Aslmjxs2X+WP7lyQ qwJCR7gY9eJ9x3EarCYKSYB7Ju+RDi/PSzVOP9AfcBcVrDeLhbvZ1J2YbXJwMNXv1PXT XG2F2ORVkYjHxbwYk8aC/un3hm0xjE6UZOOrp/HN3WuJMt/tLSqu3mxbfzkfLiVMaBG2 U1D0TCq3bKVPLfOKl59LNLTT7UjofFC9lTyabOcod2eBGGTrFt8C6LFs7yFaaQIYGljw S1z2WgNdFUfIbeHAgIGVlF3eJLd0Qv4CaXf4/HX8ebTvgBPz+hqiibfBwUnfRyvrtTu7 6hkQ== X-Gm-Message-State: AOAM532M8H/noFJUaNU9vKnkmXz99ajIqgz15YrHAS+GJDfbv2QaV7/r sWUzi6386iQ4dazNMtKvJ1welTXh/sqexA== X-Google-Smtp-Source: ABdhPJy+7v7O8ZVl4ZIzdeTIkCvqd3YZ4zGa6ulhkwvULPaXSzaO1kRhPvdmAr1Q+6Lc6L+csbv54w== X-Received: by 2002:a17:903:248:b0:155:e660:b774 with SMTP id j8-20020a170903024800b00155e660b774mr31077079plh.174.1654634206584; Tue, 07 Jun 2022 13:36:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 42/71] target/arm: Trap AdvSIMD usage when Streaming SVE is active Date: Tue, 7 Jun 2022 13:32:37 -0700 Message-Id: <20220607203306.657998-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654637226357100001 Content-Type: text/plain; charset="utf-8" This new behaviour is in the ARM pseudocode function AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32 via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which the trap would be delivered is in AArch64 mode. Given that ARMv9 drops support for AArch32 outside EL0, the trap EL detection ought to be trivially true, but the pseudocode still contains a number of conditions, and QEMU has not yet committed to dropping A32 support for EL[12] when v9 features are present. Since the computation of SME_TRAP_SIMD is necessarily different for the two modes, we might as well preserve bits within TBFLAG_ANY and allocate separate bits within TBFLAG_A32 and TBFLAG_A64 instead. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 +++ target/arm/translate.h | 3 ++ target/arm/helper.c | 42 ++++++++++++++++++ target/arm/translate-a64.c | 41 +++++++++++++++++- target/arm/translate-vfp.c | 13 ++++++ target/arm/translate.c | 1 + target/arm/meson.build | 1 + target/arm/sme-fa64.decode | 89 ++++++++++++++++++++++++++++++++++++++ 8 files changed, 194 insertions(+), 2 deletions(-) create mode 100644 target/arm/sme-fa64.decode diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 23d46c7d7d..7c46062f89 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3256,6 +3256,11 @@ FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) * the same thing as the current security state of the processor! */ FIELD(TBFLAG_A32, NS, 10, 1) +/* + * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. + * This requires an SME trap from AArch32 mode when using NEON. + */ +FIELD(TBFLAG_A32, SME_TRAP_SIMD, 11, 1) =20 /* * Bit usage when in AArch32 state, for M-profile only. @@ -3293,6 +3298,7 @@ FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) FIELD(TBFLAG_A64, SVL, 24, 4) +FIELD(TBFLAG_A64, SME_TRAP_SIMD, 28, 1) =20 /* * Helpers for using the above. diff --git a/target/arm/translate.h b/target/arm/translate.h index 1330281f8b..775297aa40 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -106,6 +106,9 @@ typedef struct DisasContext { bool pstate_sm; /* True if PSTATE.ZA is set. */ bool pstate_za; + /* True if AdvSIMD insns should raise an SME Streaming exception. */ + bool sme_trap_simd; + bool sme_trap_this_insn; /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ bool mve_no_pred; /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 2b38e82c22..3e0326af58 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6273,6 +6273,32 @@ int sme_exception_el(CPUARMState *env, int el) return 0; } =20 +/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */ +static bool sme_fa64(CPUARMState *env, int el) +{ + if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) { + return false; + } + + if (el <=3D 1 && !el_is_in_host(env, el)) { + if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) { + return false; + } + } + if (el <=3D 2 && arm_is_el2_enabled(env)) { + if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) { + return false; + } + } + if (arm_feature(env, ARM_FEATURE_EL3)) { + if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) { + return false; + } + } + + return true; +} + /* * Given that SVE is enabled, return the vector length for EL. */ @@ -13834,6 +13860,21 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMStat= e *env, int fp_el, DP_TBFLAG_ANY(flags, PSTATE__IL, 1); } =20 + /* + * The SME exception we are testing for is raised via + * AArch64.CheckFPAdvSIMDEnabled(), and for AArch32 this is called + * when EL1 is using A64 or EL2 using A64 and !TGE. + * See AArch32.CheckAdvSIMDOrFPEnabled(). + */ + if (el =3D=3D 0 + && FIELD_EX64(env->svcr, SVCR, SM) + && (!arm_is_el2_enabled(env) + || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE))) + && arm_el_is_aa64(env, 1) + && !sme_fa64(env, el)) { + DP_TBFLAG_A32(flags, SME_TRAP_SIMD, 1); + } + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } =20 @@ -13883,6 +13924,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState= *env, int el, int fp_el, } if (FIELD_EX64(env->svcr, SVCR, SM)) { DP_TBFLAG_A64(flags, PSTATE_SM, 1); + DP_TBFLAG_A64(flags, SME_TRAP_SIMD, !sme_fa64(env, el)); } DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8a38fbc33b..029c0a917c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1155,7 +1155,7 @@ static void do_vec_ld(DisasContext *s, int destidx, i= nt element, * unallocated-encoding checks (otherwise the syndrome information * for the resulting exception will be incorrect). */ -static bool fp_access_check(DisasContext *s) +static bool fp_access_check_only(DisasContext *s) { if (s->fp_excp_el) { assert(!s->fp_access_checked); @@ -1169,6 +1169,20 @@ static bool fp_access_check(DisasContext *s) return true; } =20 +static bool fp_access_check(DisasContext *s) +{ + if (!fp_access_check_only(s)) { + return false; + } + if (s->sme_trap_this_insn) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_Streaming, false), + default_exception_el(s)); + return false; + } + return true; +} + /* Check that SVE access is enabled. If it is, return true. * If not, emit code to generate an appropriate exception and return false. */ @@ -1994,7 +2008,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, default: g_assert_not_reached(); } - if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { + if ((ri->type & ARM_CP_FPU) && !fp_access_check_only(s)) { return; } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { return; @@ -14530,6 +14544,23 @@ static void disas_data_proc_simd_fp(DisasContext *= s, uint32_t insn) } } =20 +/* + * Include the generated SME FA64 decoder. + */ + +#include "decode-sme-fa64.c.inc" + +static bool trans_OK(DisasContext *s, arg_OK *a) +{ + return true; +} + +static bool trans_FAIL(DisasContext *s, arg_OK *a) +{ + s->sme_trap_this_insn =3D true; + return true; +} + /** * is_guarded_page: * @env: The cpu environment @@ -14662,6 +14693,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->mte_active[1] =3D EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE); dc->pstate_sm =3D EX_TBFLAG_A64(tb_flags, PSTATE_SM); dc->pstate_za =3D EX_TBFLAG_A64(tb_flags, PSTATE_ZA); + dc->sme_trap_simd =3D EX_TBFLAG_A64(tb_flags, SME_TRAP_SIMD); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; @@ -14813,6 +14845,11 @@ static void aarch64_tr_translate_insn(DisasContext= Base *dcbase, CPUState *cpu) } } =20 + if (s->sme_trap_simd) { + s->sme_trap_this_insn =3D false; + disas_sme_fa64(s, insn); + } + switch (extract32(insn, 25, 4)) { case 0x0: if (!disas_sme(s, insn)) { diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 40a513b822..476868622f 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -224,6 +224,19 @@ static bool vfp_access_check_a(DisasContext *s, bool i= gnore_vfp_enabled) return false; } =20 + /* + * Note that rebuild_hflags_a32 has already accounted for being in EL0 + * and the higher EL in A64 mode, etc. Unlike A64 mode, there do not + * appear to be any insns which touch VFP which are allowed. + */ + if (s->sme_trap_simd) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_Streaming, + s->base.pc_next - s->pc_curr =3D=3D= 2), + default_exception_el(s)); + return false; + } + if (!s->vfp_enabled && !ignore_vfp_enabled) { assert(!arm_dc_feature(s, ARM_FEATURE_M)); unallocated_encoding(s); diff --git a/target/arm/translate.c b/target/arm/translate.c index 87a899d638..a286024bad 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9365,6 +9365,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) dc->vec_len =3D EX_TBFLAG_A32(tb_flags, VECLEN); dc->vec_stride =3D EX_TBFLAG_A32(tb_flags, VECSTRIDE); } + dc->sme_trap_simd =3D EX_TBFLAG_A32(tb_flags, SME_TRAP_SIMD); } dc->cp_regs =3D cpu->cp_regs; dc->features =3D env->features; diff --git a/target/arm/meson.build b/target/arm/meson.build index c47d86c609..07bd9f3c0f 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,6 +1,7 @@ gen =3D [ decodetree.process('sve.decode', extra_args: '--decode=3Ddisas_sve'), decodetree.process('sme.decode', extra_args: '--decode=3Ddisas_sme'), + decodetree.process('sme-fa64.decode', extra_args: '--static-decode=3Ddis= as_sme_fa64'), decodetree.process('neon-shared.decode', extra_args: '--decode=3Ddisas_n= eon_shared'), decodetree.process('neon-dp.decode', extra_args: '--decode=3Ddisas_neon_= dp'), decodetree.process('neon-ls.decode', extra_args: '--decode=3Ddisas_neon_= ls'), diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode new file mode 100644 index 0000000000..4c2569477d --- /dev/null +++ b/target/arm/sme-fa64.decode @@ -0,0 +1,89 @@ +# AArch64 SME allowed instruction decoding +# +# Copyright (c) 2022 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# + +# These patterns are taken from Appendix E1.1 of DDI0616 A.a, +# Arm Architecture Reference Manual Supplement, +# The Scalable Matrix Extension (SME), for Armv9-A + +{ + [ + OK 0-00 1110 0000 0001 0010 11-- ---- ---- # SMOV W|Xd,Vn.B[0] + OK 0-00 1110 0000 0010 0010 11-- ---- ---- # SMOV W|Xd,Vn.H[0] + OK 0100 1110 0000 0100 0010 11-- ---- ---- # SMOV Xd,Vn.S[0] + OK 0000 1110 0000 0001 0011 11-- ---- ---- # UMOV Wd,Vn.B[0] + OK 0000 1110 0000 0010 0011 11-- ---- ---- # UMOV Wd,Vn.H[0] + OK 0000 1110 0000 0100 0011 11-- ---- ---- # UMOV Wd,Vn.S[0] + OK 0100 1110 0000 1000 0011 11-- ---- ---- # UMOV Xd,Vn.D[0] + ] + FAIL 0--0 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD vector o= perations +} + +{ + [ + OK 0101 1110 --1- ---- 11-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (= scalar) + OK 0101 1110 -10- ---- 00-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (= scalar, FP16) + OK 01-1 1110 1-10 0001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX = (scalar) + OK 01-1 1110 1111 1001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX = (scalar, FP16) + ] + FAIL 01-1 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD single-e= lement operations +} + +FAIL 0-00 110- ---- ---- ---- ---- ---- ---- # Advanced SIMD structur= e load/store +FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptogr= aphy extensions + +# These are the "avoidance of doubt" final table of Illegal Advanced SIMD = instructions +# We don't actually need to include these, as the default is OK. +# -001 111- ---- ---- ---- ---- ---- ---- # Scalar floating-point = operations +# --10 110- ---- ---- ---- ---- ---- ---- # Load/store pair of FP = registers +# --01 1100 ---- ---- ---- ---- ---- ---- # Load FP register (PC-r= elative literal) +# --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register= (unscaled imm) +# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register= (register offset) +# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register= (scaled imm) + +FAIL 0000 0100 --1- ---- 1010 ---- ---- ---- # ADR +FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA +FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT +FAIL 0010 0101 --01 100- 1111 000- ---0 ---- # RDFFR, RDFFRS +FAIL 0010 0101 --10 1--- 1001 ---- ---- ---- # WRFFR, SETFFR +FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP +FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b r= esult) +FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA +FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL +FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD +FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA +FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA +FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/cryp= to instructions +FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT = load (vector+scalar) +FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather pref= etch (vector+imm) +FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather pref= etch (scalar+vector) +FAIL 1000 010- -01- ---- 1--- ---- ---- ---- # SVE 32-bit gather load= (vector+imm) +FAIL 1000 0100 0-0- ---- 0--- ---- ---- ---- # SVE 32-bit gather load= byte (scalar+vector) +FAIL 1000 0100 1--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load= half (scalar+vector) +FAIL 1000 0101 0--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load= word (scalar+vector) +FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load= (scalar+scalar) +FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load= (scalar+imm) +FAIL 1010 010- -10- ---- 000- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+scalar) +FAIL 1010 010- -100 ---- 001- ---- ---- ---- # SVE load & replicate 3= 2 bytes (scalar+imm) +FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load= /prefetch +FAIL 1110 010- -00- ---- 001- ---- ---- ---- # SVE2 64-bit scatter NT= store (vector+scalar) +FAIL 1110 010- -10- ---- 001- ---- ---- ---- # SVE2 32-bit scatter NT= store (vector+scalar) +FAIL 1110 010- ---- ---- 1-0- ---- ---- ---- # SVE scatter store (sca= lar+32-bit vector) +FAIL 1110 010- ---- ---- 101- ---- ---- ---- # SVE scatter store (mis= c) --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.36.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:36:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LaAdc3vpJrtjbCOAPYhIA7+KAdo0UJCuCASVQA/g2u8=; b=yhzCWaiGDUjbUwdP980NYnh2pu/2tn+NrOw5E7jA3aRdEnf7ZGHqKM7MyYnaNKLwsL nwiMsJh3wgfuPDBorOTwMYNpK1BLJDja23gzYpsMnJDfSYl5WrYt2hCdRtMpzVLGoySP TlZ/CQXhD0o+s1iedjh8d7s14X7qqkkhg12QgLICgztqY22SA3yWXhpsn/oAmNE/ngh2 D4AYzI+K4OjtM3zGMvH5GPuO4L8z/Kqq7uF+DgxA1MiKeg4GSYbPsQW4Ur6Uz4F3NA0h sGWfnqFuHW4Oxs4BEJWyXtV9wcfRFy/02TLWN/1GY3a+bvzIh7FDeGgQrCKW/44LUyCe W9Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LaAdc3vpJrtjbCOAPYhIA7+KAdo0UJCuCASVQA/g2u8=; b=OolG3bfJkdiAhsXqsHNpXScqp+BuEtioz3/OqHgLpJ3FflHpHtRK6qtjczE+Ek12Bm bXi6xCLuDG/XrEZ+pUsn5csjw3bq+fhTG4yT/rZYFBpoFYF6NNO0RhW0JVrttOFAxnCW 1A4zZTqq3LAG4WZ7GyElzpX1Cqe3eq6ARfYudvcTh3hZyMdRgBx3Q84geKRsno9ThzO2 PHXKKioygDFMGrjimrASrL65Ah+J+0E2KFwdvmYHfdDfjpiwJz/L9d9lN0JcRb4wTvcn wkE6++il8SjSMrCCfZUs1EqxTNRxLAFXAic76J9Z1RUVpGELhI+oGGKHoEXVLCku77Lw dtJw== X-Gm-Message-State: AOAM5320Ecid9wK78hGENpS/a6I7JkNKrt2LAuYkTPXI+DL/0TCdCfE1 ZXgzJtegYjG90l85qdiUoDiBVCuXDDtxvQ== X-Google-Smtp-Source: ABdhPJyGNGJLWjtpQt6VWEH0GDt4QPdBW0YygNs9OGuzEy6gJ7TJbZi4KRSzgdRBTorPSL6E6RSiiQ== X-Received: by 2002:a63:1666:0:b0:3fd:a62f:94a6 with SMTP id 38-20020a631666000000b003fda62f94a6mr12034615pgw.360.1654634207584; Tue, 07 Jun 2022 13:36:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 43/71] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL Date: Tue, 7 Jun 2022 13:32:38 -0700 Message-Id: <20220607203306.657998-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654636425731100001 Content-Type: text/plain; charset="utf-8" These SME instructions are nominally within the SVE decode space, so we add them to sve.decode and translate-sve.c. Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 1 + target/arm/translate-a64.c | 15 +++++++++++++++ target/arm/translate-sve.c | 38 ++++++++++++++++++++++++++++++++++++++ target/arm/sve.decode | 5 ++++- 4 files changed, 58 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 789b6e8e78..6bd1b2eb4b 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -29,6 +29,7 @@ void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v); bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, unsigned int imms, unsigned int immr); bool sve_access_check(DisasContext *s); +bool sme_enabled_check(DisasContext *s); TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, int log2_size); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 029c0a917c..222f93d42d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1216,6 +1216,21 @@ static bool sme_access_check(DisasContext *s) return true; } =20 +/* Note that this function corresponds to CheckSMEEnabled. */ +bool sme_enabled_check(DisasContext *s) +{ + /* + * Note that unlike sve_excp_el, we have not constrained sme_excp_el + * to be zero when fp_excp_el has priority. This is because we need + * sme_excp_el by itself for cpregs access checks. + */ + if (!s->fp_excp_el || s->sme_excp_el < s->fp_excp_el) { + s->fp_access_checked =3D true; + return sme_access_check(s); + } + return fp_access_check_only(s); +} + /* * This utility function is for doing register extension with an * optional shift. You will likely want to pass a temporary for the diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 62b5f3040c..13bdd027a5 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1286,6 +1286,19 @@ static bool trans_ADDVL(DisasContext *s, arg_ADDVL *= a) return true; } =20 +static bool trans_ADDSVL(DisasContext *s, arg_ADDSVL *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_enabled_check(s)) { + TCGv_i64 rd =3D cpu_reg_sp(s, a->rd); + TCGv_i64 rn =3D cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(rd, rn, a->imm * s->svl); + } + return true; +} + static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) { if (!dc_isar_feature(aa64_sve, s)) { @@ -1299,6 +1312,19 @@ static bool trans_ADDPL(DisasContext *s, arg_ADDPL *= a) return true; } =20 +static bool trans_ADDSPL(DisasContext *s, arg_ADDSPL *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_enabled_check(s)) { + TCGv_i64 rd =3D cpu_reg_sp(s, a->rd); + TCGv_i64 rn =3D cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(rd, rn, a->imm * (s->svl / 8)); + } + return true; +} + static bool trans_RDVL(DisasContext *s, arg_RDVL *a) { if (!dc_isar_feature(aa64_sve, s)) { @@ -1311,6 +1337,18 @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a) return true; } =20 +static bool trans_RDSVL(DisasContext *s, arg_RDSVL *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_enabled_check(s)) { + TCGv_i64 reg =3D cpu_reg(s, a->rd); + tcg_gen_movi_i64(reg, a->imm * s->svl); + } + return true; +} + /* *** SVE Compute Vector Address Group */ diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a54feb2f61..bbdaac6ac7 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -449,14 +449,17 @@ INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 r= d:5 # SVE index generation (register start, register increment) INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm =20 -### SVE Stack Allocation Group +### SVE / Streaming SVE Stack Allocation Group =20 # SVE stack frame adjustment ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 +ADDSVL 00000100 001 ..... 01011 ...... ..... @rd_rn_i6 ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 +ADDSPL 00000100 011 ..... 01011 ...... ..... @rd_rn_i6 =20 # SVE stack frame size RDVL 00000100 101 11111 01010 imm:s6 rd:5 +RDSVL 00000100 101 11111 01011 imm:s6 rd:5 =20 ### SVE Bitwise Shift - Unpredicated Group =20 --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654636906; cv=none; d=zohomail.com; s=zohoarc; b=OmWOQ94PcdrBRX6Jj62rTN7QkZwkf1dvtoym3iLe7cl9LEslf8bImpGyncEYNfG5Vsvam8COfY4L/mvCZ4mI1nv66Wb5dL/lHm2xrLaLXu3a/I0R3dMc/kFO4ppPhODF1er/OorQF9Z54taBggLbK96tL96GjHuvu1mjhSSgboI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654636906; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wPGkoMeCdhx99y01psdS4/penQAneUPj/+BZk+ezxUo=; b=Fpeyx/766kct4C1UhW99/q0yNxdQUjmG7/9iPPQXAK+DfiuWQzO9nm5OZR+RRBAEfIkfHSmYxjTHHeRyskzCj1moNU0tSu+/psgrokNl3BOiFa6/iNrqpuFnbkGCDg8RWZvrpZzrP9Ct1wA5lvzDW4ttsX9txcM2YgisayC8iEk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654636906875970.5717101580454; Tue, 7 Jun 2022 14:21:46 -0700 (PDT) Received: from localhost ([::1]:58594 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyge1-0004cQ-QL for importer@patchew.org; Tue, 07 Jun 2022 17:21:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35604) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfwb-0006O2-Vp for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:36:54 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:54999) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfwX-0008E0-SL for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:36:53 -0400 Received: by mail-pj1-x1031.google.com with SMTP id j7so16657334pjn.4 for ; Tue, 07 Jun 2022 13:36:49 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.36.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:36:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wPGkoMeCdhx99y01psdS4/penQAneUPj/+BZk+ezxUo=; b=MBCABkNBS4UKmJbfBgclu2IurQIf5vGeWY84AAlUMzfS+YB0isS2FI+IO59pbSyh8c sfWhpdTK1IlJnqOx9d72JI4XfZwymEnztH+YQbHTdV3R7oHq9D/6wPx3N/vMnRJp64pE /UnWzzgDd3NQYIJirrMCrLM4ASNJ5B0KLiTvwjYeSe5Gm3B7DdNltN8zbdCs9PBn1CfR +3CiMbOnbcS35exXIKRf53lY/iOi+vm7xMDYwYGCddVZxLBKb6UZAWERsi4B/zBWfTCU yL+uIwk8Zte6uOGTpxO48ATWcJdqEJv9a63TusAPd4XlyQhk7/HHBUNObdS/MZUtN+EP 05qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654636907282100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 2 ++ target/arm/translate-a64.h | 1 + target/arm/sme_helper.c | 25 +++++++++++++++++++++++++ target/arm/translate-a64.c | 15 +++++++++++++++ target/arm/translate-sme.c | 13 +++++++++++++ target/arm/sme.decode | 4 ++++ 6 files changed, 60 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 3bd48c235f..c4ee1f09e4 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -19,3 +19,5 @@ =20 DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32) + +DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 6bd1b2eb4b..ec5d580ba0 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -30,6 +30,7 @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned in= t immn, unsigned int imms, unsigned int immr); bool sve_access_check(DisasContext *s); bool sme_enabled_check(DisasContext *s); +bool sme_za_enabled_check(DisasContext *s); TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, int log2_size); diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index b215725594..e5b5723a15 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -59,3 +59,28 @@ void helper_set_pstate_za(CPUARMState *env, uint32_t i) memset(env->zarray, 0, sizeof(env->zarray)); } } + +void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl) +{ + uint32_t i; + + /* + * Special case clearing the entire ZA space. + * This falls into the CONSTRAINED UNPREDICTABLE zeroing of any + * parts of the ZA storage outside of SVL. + */ + if (imm =3D=3D 0xff) { + memset(env->zarray, 0, sizeof(env->zarray)); + return; + } + + /* + * Recall that ZAnH.D[m] is spread across ZA[n+8*m]. + * Unless SVL =3D=3D ARM_MAX_VQ, each row is discontiguous. + */ + for (i =3D 0; i < svl; i++) { + if (imm & (1 << (i % 8))) { + memset(&env->zarray[i], 0, svl); + } + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 222f93d42d..660c5dbf5b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1231,6 +1231,21 @@ bool sme_enabled_check(DisasContext *s) return fp_access_check_only(s); } =20 +/* Note that this function corresponds to CheckSMEAndZAEnabled. */ +bool sme_za_enabled_check(DisasContext *s) +{ + if (!sme_enabled_check(s)) { + return false; + } + if (!s->pstate_za) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_InactiveZA, false), + default_exception_el(s)); + return false; + } + return true; +} + /* * This utility function is for doing register extension with an * optional shift. You will likely want to pass a temporary for the diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 786c93fb2d..d526c74456 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -33,3 +33,16 @@ */ =20 #include "decode-sme.c.inc" + + +static bool trans_ZERO(DisasContext *s, arg_ZERO *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_za_enabled_check(s)) { + gen_helper_sme_zero(cpu_env, tcg_constant_i32(a->imm), + tcg_constant_i32(s->svl)); + } + return true; +} diff --git a/target/arm/sme.decode b/target/arm/sme.decode index c25c031a71..6e4483fdce 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -18,3 +18,7 @@ # # This file is processed by scripts/decodetree.py # + +### SME Misc + +ZERO 11000000 00 001 00000000000 imm:8 --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654637650; cv=none; d=zohomail.com; s=zohoarc; b=W2/gRHrXlRgy5dd8LwSg4Mdki3DTCxhScj0sI+AxrkjqXHMZ3WOznfeRb9XGPsqYiO55drbvUpspAq0p3LgKP5F0RE7WJJ2tJKnOqq02dx5HJLvk6KY9W0EvQs6jZE50fMMiuF5owZHZQGnD+/Zc389l7Fc7372MqvWD2ChAKck= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654637650; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cGWWtgQOmUC1oO416fCbKUBf9KcbSCbcFAMf9iiJDm0=; b=BkBFWp4hXq9S17S87t3Ll6FNft6Aq9QeltZk+I2jnDn6OMqfXepphmCrSmG7xg3F5XRSysNravHSa6kYIV3aq2VXaGw69P6RdprRCyCkOO1mtA5HZ9YRsoz7PQK3y6wRRVXHhrW6r3U3OVxYX6tezLdH6Vq5tIIWBAytZ2k3ZzA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654637650402594.3577698111169; Tue, 7 Jun 2022 14:34:10 -0700 (PDT) Received: from localhost ([::1]:53548 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygq1-00042O-9l for importer@patchew.org; Tue, 07 Jun 2022 17:34:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35680) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfwe-0006S6-2G for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:36:56 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:42714) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfwY-0008EH-WE for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:36:55 -0400 Received: by mail-pj1-x102e.google.com with SMTP id d12-20020a17090abf8c00b001e2eb431ce4so16450321pjs.1 for ; Tue, 07 Jun 2022 13:36:50 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.36.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:36:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cGWWtgQOmUC1oO416fCbKUBf9KcbSCbcFAMf9iiJDm0=; b=IQge3VyTEzK7Rir1imq7VeEYb4PmVDyv7Q1l4PZxw0/3ukWx+mhTRXuPGtAl8+IwdQ wOcOSgAHS//83b5LJwyGgLVF7iY4j62eOlTbE/o6t6h1XWPERJ5+sR/P69aIS/N2WOr5 d4H7+wPKkyhwlrdI5gBsyz5kjAjcOt4ix1nqWYFKtpXOofKLffESiYxE7Ipif2pg+ZRg BUyRLJHQ4KLnubNRqPvrEKmdHy4Dot+Guy1JLWre/XWmn+0k4Vz/m9ZZiZuSnzhMmnfr i6+WnoaW7iHdbGxe3CFj6ujaHT5/oiB+ub4ULMSN16oHykOZRhax2tIzjtUoz9uAcoUa 9cSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cGWWtgQOmUC1oO416fCbKUBf9KcbSCbcFAMf9iiJDm0=; b=3AUjdefw6Vm6hjQfAgApWMjbpznIbSpnPa7AU7d2kqyVCTQPm/vyYd439SkzKWCm3K r4tTOTgB/8UoARZKnsGkVa3wPXqhlqqnD+XQ2FcAhurj+Pc8gPIcJNlL4gUfBvn0w4kb tX5Cox7RP5GKVasNvV8JOtVcA+xGC+xwiXgEfOzYUobKWgHribpCwGQM0mfg7VBISxeM 5/+MF2Z8emaRusJ3jOsVDt1An10jofgtTNJh/yxnMtLcG6klJ+qOHJDXVDRBQKslcvvV /YCDFUQamv8veNCIR/iaeqlz0Lr2kxu46b1ccdTxFZSBuQfplm4nZEGn4vpWKi2wWfwk Unkg== X-Gm-Message-State: AOAM533C2tkQJ0N/noLi5JdlCnaOLAOs58KR4mB8TJ/FkOTvMxxqZ8Q7 zyq/+p+fcW6b+yO6WMZu3gMp2FanWUNOAQ== X-Google-Smtp-Source: ABdhPJwOdX4/XkSdUTi0X/zyFzOFc8BC3faOMDp3QRpxq8VwVyYsUOf3CerQCuJWHJgyOFOdF8aLvA== X-Received: by 2002:a17:902:d2c9:b0:163:bdee:b2df with SMTP id n9-20020a170902d2c900b00163bdeeb2dfmr30980748plc.98.1654634209383; Tue, 07 Jun 2022 13:36:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 45/71] target/arm: Implement SME MOVA Date: Tue, 7 Jun 2022 13:32:40 -0700 Message-Id: <20220607203306.657998-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654637651113100001 Content-Type: text/plain; charset="utf-8" We can reuse the SVE functions for implementing moves to/from horizontal tile slices, but we need new ones for moves to/from vertical tile slices. Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 11 ++++ target/arm/helper-sve.h | 2 + target/arm/translate-a64.h | 9 +++ target/arm/translate.h | 5 ++ target/arm/sme_helper.c | 110 ++++++++++++++++++++++++++++++++++++- target/arm/sve_helper.c | 12 ++++ target/arm/translate-a64.c | 21 +++++++ target/arm/translate-sme.c | 105 +++++++++++++++++++++++++++++++++++ target/arm/sme.decode | 15 +++++ 9 files changed, 289 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index c4ee1f09e4..600346e08c 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -21,3 +21,14 @@ DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void,= env, i32) DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32) =20 DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32) + +DEF_HELPER_FLAGS_4(sme_mova_avz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sme_mova_zav_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sme_mova_avz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sme_mova_zav_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sme_mova_avz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sme_mova_zav_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sme_mova_avz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sme_mova_zav_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sme_mova_avz_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) +DEF_HELPER_FLAGS_4(sme_mova_zav_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index dc629f851a..ab0333400f 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -325,6 +325,8 @@ DEF_HELPER_FLAGS_5(sve_sel_zpzz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve_sel_zpzz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_sel_zpzz_q, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_5(sve2_addp_zpzz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index ec5d580ba0..c341c95582 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -31,6 +31,7 @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned in= t immn, bool sve_access_check(DisasContext *s); bool sme_enabled_check(DisasContext *s); bool sme_za_enabled_check(DisasContext *s); +bool sme_smza_enabled_check(DisasContext *s); TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, int log2_size); @@ -147,6 +148,14 @@ static inline int pred_gvec_reg_size(DisasContext *s) return size_for_gvec(pred_full_reg_size(s)); } =20 +/* Return a newly allocated pointer to the predicate register. */ +static inline TCGv_ptr pred_full_reg_ptr(DisasContext *s, int regno) +{ + TCGv_ptr ret =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ret, cpu_env, pred_full_reg_offset(s, regno)); + return ret; +} + bool disas_sve(DisasContext *, uint32_t); bool disas_sme(DisasContext *, uint32_t); =20 diff --git a/target/arm/translate.h b/target/arm/translate.h index 775297aa40..d03afd0034 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -159,6 +159,11 @@ static inline int plus_2(DisasContext *s, int x) return x + 2; } =20 +static inline int plus_12(DisasContext *s, int x) +{ + return x + 12; +} + static inline int times_2(DisasContext *s, int x) { return x * 2; diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index e5b5723a15..99524ead4d 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -19,8 +19,10 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "internals.h" +#include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" +#include "qemu/int128.h" +#include "vec_internal.h" =20 /* ResetSVEState */ void arm_reset_sve_state(CPUARMState *env) @@ -84,3 +86,109 @@ void helper_sme_zero(CPUARMState *env, uint32_t imm, ui= nt32_t svl) } } } + +#define DO_MOVA_A(NAME, TYPE, H) \ +void HELPER(NAME)(void *za, void *vn, void *vg, uint32_t desc) \ +{ \ + int i, oprsz =3D simd_oprsz(desc); \ + for (i =3D 0; i < oprsz; ) { \ + uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); \ + do { \ + if (pg & 1) { \ + *(TYPE *)za =3D *(TYPE *)(vn + H(i)); \ + } \ + za +=3D sizeof(ARMVectorReg) * sizeof(TYPE); \ + i +=3D sizeof(TYPE); \ + pg >>=3D sizeof(TYPE); \ + } while (i & 15); \ + } \ +} + +#define DO_MOVA_Z(NAME, TYPE, H) \ +void HELPER(NAME)(void *vd, void *za, void *vg, uint32_t desc) \ +{ \ + int i, oprsz =3D simd_oprsz(desc); \ + for (i =3D 0; i < oprsz; ) { \ + uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); \ + do { \ + if (pg & 1) { \ + *(TYPE *)(vd + H(i)) =3D *(TYPE *)za; \ + } \ + za +=3D sizeof(ARMVectorReg) * sizeof(TYPE); \ + i +=3D sizeof(TYPE); \ + pg >>=3D sizeof(TYPE); \ + } while (i & 15); \ + } \ +} + +DO_MOVA_A(sme_mova_avz_b, uint8_t, H1) +DO_MOVA_A(sme_mova_avz_h, uint16_t, H2) +DO_MOVA_A(sme_mova_avz_s, uint32_t, H4) + +DO_MOVA_Z(sme_mova_zav_b, uint8_t, H1) +DO_MOVA_Z(sme_mova_zav_h, uint16_t, H2) +DO_MOVA_Z(sme_mova_zav_s, uint32_t, H4) + +void HELPER(sme_mova_avz_d)(void *za, void *vn, void *vg, uint32_t desc) +{ + int i, oprsz =3D simd_oprsz(desc) / 8; + uint8_t *pg =3D vg; + uint64_t *n =3D vn; + uint64_t *a =3D za; + + /* + * Note that the rows of the ZAV.D tile are 8 absolute rows apart, + * so while the address arithmetic below looks funny, it is right. + */ + for (i =3D 0; i < oprsz; i++) { + if (pg[H1_2(i)] & 1) { + a[i * sizeof(ARMVectorReg)] =3D n[i]; + } + } +} + +void HELPER(sme_mova_zav_d)(void *vd, void *za, void *vg, uint32_t desc) +{ + int i, oprsz =3D simd_oprsz(desc) / 8; + uint8_t *pg =3D vg; + uint64_t *d =3D vd; + uint64_t *a =3D za; + + for (i =3D 0; i < oprsz; i++) { + if (pg[H1_2(i)] & 1) { + d[i] =3D a[i * sizeof(ARMVectorReg)]; + } + } +} + +void HELPER(sme_mova_avz_q)(void *za, void *vn, void *vg, uint32_t desc) +{ + int i, oprsz =3D simd_oprsz(desc) / 16; + uint16_t *pg =3D vg; + Int128 *n =3D vn; + Int128 *a =3D za; + + /* + * Note that the rows of the ZAV.Q tile are 16 absolute rows apart, + * so while the address arithmetic below looks funny, it is right. + */ + for (i =3D 0; i < oprsz; i++) { + if (pg[H2(i)] & 1) { + a[i * sizeof(ARMVectorReg)] =3D n[i]; + } + } +} + +void HELPER(sme_mova_zav_q)(void *za, void *vn, void *vg, uint32_t desc) +{ + int i, oprsz =3D simd_oprsz(desc) / 16; + uint16_t *pg =3D vg; + Int128 *n =3D vn; + Int128 *a =3D za; + + for (i =3D 0; i < oprsz; i++, za +=3D sizeof(ARMVectorReg)) { + if (pg[H2(i)] & 1) { + n[i] =3D a[i * sizeof(ARMVectorReg)]; + } + } +} diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 1654c0bbf9..9a26f253e0 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -3565,6 +3565,18 @@ void HELPER(sve_sel_zpzz_d)(void *vd, void *vn, void= *vm, } } =20 +void HELPER(sve_sel_zpzz_q)(void *vd, void *vn, void *vm, + void *vg, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 16; + Int128 *d =3D vd, *n =3D vn, *m =3D vm; + uint16_t *pg =3D vg; + + for (i =3D 0; i < opr_sz; i +=3D 1) { + d[i] =3D (pg[H2(i)] & 1 ? n : m)[i]; + } +} + /* Two operand comparison controlled by a predicate. * ??? It is very tempting to want to be able to expand this inline * with x86 instructions, e.g. diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 660c5dbf5b..2b4baa2684 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1246,6 +1246,27 @@ bool sme_za_enabled_check(DisasContext *s) return true; } =20 +/* Note that this function corresponds to CheckStreamingSVEAndZAEnabled. */ +bool sme_smza_enabled_check(DisasContext *s) +{ + if (!sme_enabled_check(s)) { + return false; + } + if (!s->pstate_sm) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_NotStreaming, false), + default_exception_el(s)); + return false; + } + if (!s->pstate_za) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_InactiveZA, false), + default_exception_el(s)); + return false; + } + return true; +} + /* * This utility function is for doing register extension with an * optional shift. You will likely want to pass a temporary for the diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index d526c74456..d2a7232491 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -35,6 +35,54 @@ #include "decode-sme.c.inc" =20 =20 +static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs, + int tile_index, bool vertical) +{ + int tile =3D tile_index >> (4 - esz); + int index =3D esz =3D=3D MO_128 ? 0 : extract32(tile_index, 0, 4 - esz= ); + int pos, len, offset; + TCGv_i32 t_index; + TCGv_ptr addr; + + /* Resolve tile.size[index] to an untyped ZA slice index. */ + t_index =3D tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t_index, cpu_reg(s, rs)); + tcg_gen_addi_i32(t_index, t_index, index); + + len =3D ctz32(s->svl) - esz; + pos =3D esz; + offset =3D tile; + + /* + * Horizontal slice. Index row N, column 0. + * The helper will iterate by the element size. + */ + if (!vertical) { + pos +=3D ctz32(sizeof(ARMVectorReg)); + offset *=3D sizeof(ARMVectorReg); + } + offset +=3D offsetof(CPUARMState, zarray); + + tcg_gen_deposit_z_i32(t_index, t_index, pos, len); + tcg_gen_addi_i32(t_index, t_index, offset); + + /* + * Vertical tile slice. Index row 0, column N. + * The helper will iterate by the row spacing in the array. + * Need to adjust addressing for elements smaller than uint64_t for BE. + */ + if (HOST_BIG_ENDIAN && vertical && esz < MO_64) { + tcg_gen_xori_i32(t_index, t_index, 8 - (1 << esz)); + } + + addr =3D tcg_temp_new_ptr(); + tcg_gen_ext_i32_ptr(addr, t_index); + tcg_temp_free_i32(t_index); + tcg_gen_add_ptr(addr, addr, cpu_env); + + return addr; +} + static bool trans_ZERO(DisasContext *s, arg_ZERO *a) { if (!dc_isar_feature(aa64_sme, s)) { @@ -46,3 +94,60 @@ static bool trans_ZERO(DisasContext *s, arg_ZERO *a) } return true; } + +static bool trans_MOVA(DisasContext *s, arg_MOVA *a) +{ + static gen_helper_gvec_4 * const h_fns[5] =3D { + gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h, + gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d, + gen_helper_sve_sel_zpzz_q + }; + static gen_helper_gvec_3 * const avz_fns[5] =3D { + gen_helper_sme_mova_avz_b, gen_helper_sme_mova_avz_h, + gen_helper_sme_mova_avz_s, gen_helper_sme_mova_avz_d, + gen_helper_sme_mova_avz_q, + }; + static gen_helper_gvec_3 * const zav_fns[5] =3D { + gen_helper_sme_mova_zav_b, gen_helper_sme_mova_zav_h, + gen_helper_sme_mova_zav_s, gen_helper_sme_mova_zav_d, + gen_helper_sme_mova_zav_q, + }; + + TCGv_ptr t_za, t_zr, t_pg; + TCGv_i32 t_desc; + + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (!sme_smza_enabled_check(s)) { + return true; + } + + t_za =3D get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v); + t_zr =3D vec_full_reg_ptr(s, a->zr); + t_pg =3D pred_full_reg_ptr(s, a->pg); + + t_desc =3D tcg_constant_i32(simd_desc(s->svl, s->svl, 0)); + + if (a->v) { + /* Vertical slice -- use sme mova helpers. */ + if (a->to_vec) { + zav_fns[a->esz](t_za, t_zr, t_pg, t_desc); + } else { + avz_fns[a->esz](t_zr, t_za, t_pg, t_desc); + } + } else { + /* Horizontal slice -- reuse sve sel helpers. */ + if (a->to_vec) { + h_fns[a->esz](t_zr, t_za, t_zr, t_pg, t_desc); + } else { + h_fns[a->esz](t_za, t_zr, t_za, t_pg, t_desc); + } + } + + tcg_temp_free_ptr(t_za); + tcg_temp_free_ptr(t_zr); + tcg_temp_free_ptr(t_pg); + + return true; +} diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 6e4483fdce..241b4895b7 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -22,3 +22,18 @@ ### SME Misc =20 ZERO 11000000 00 001 00000000000 imm:8 + +### SME Move into/from Array + +%mova_rs 13:2 !function=3Dplus_12 +&mova esz rs pg zr za_imm v:bool to_vec:bool + +MOVA 11000000 esz:2 00000 0 v:1 .. pg:3 zr:5 0 za_imm:4 \ + &mova to_vec=3D0 rs=3D%mova_rs +MOVA 11000000 11 00000 1 v:1 .. pg:3 zr:5 0 za_imm:4 \ + &mova to_vec=3D0 rs=3D%mova_rs esz=3D4 + +MOVA 11000000 esz:2 00001 0 v:1 .. pg:3 0 za_imm:4 zr:5 \ + &mova to_vec=3D1 rs=3D%mova_rs +MOVA 11000000 11 00001 1 v:1 .. pg:3 0 za_imm:4 zr:5 \ + &mova to_vec=3D1 rs=3D%mova_rs esz=3D4 --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.36.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:36:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=78VUj9FNNPnZZYMCcvRS8XTvv9xoABgkLp6amWRFUM0=; b=UrtfuCiTLOyTiBcEmYNiIHIBUF388y7iltMVqa5Fpoixs93Ea2xDkkEK8AhevYStdn 8N3dh/KAMOOslipWmcaftjnJGHSgjZwRN1zyM3yhJlWXA+RypvnfpMp+Pu7PIsmDo9X5 APo65qVoTu1m2PE0RrsTNrjqoZohlWwuFI18Te3xNCfhe20TrC2S31nGUI5Z8PLvk+gj XADoe6XHYMM4RNGQA0qsKfQUskxlCQW1P+mZ8yOA0Ph19VQhkNqy3MBw1zyY5mbwIgN4 BrzqllP76hC2aA651AwyfdJMfuCxKy35BfovjU7XE87TuBYzIQ7NwVU6bEi6Y6DxbzFt Jeng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=78VUj9FNNPnZZYMCcvRS8XTvv9xoABgkLp6amWRFUM0=; b=4qs/PBK8XTtU9FRnIj0cV7XCYxD4axCuH/bWZUp9LhY83Zd6ZkmkIamUaxOAj8km+U L/D4TW0FhL4AsXOkI4Z3yc19/Ae/KZshFW5YZwjPEINV7Qz0TGnMxJPwNKokQ3w383jK pKVY3F2xjr8pQTHU8R2WeBAsAtrvdE475tcEl3AQd6VCZ8+JNkYK3sh2nMiZZhQdmbRh 2z63Kq103EwuSE6PLzuqPykQaP+SQmTVrODChFkSrnrH9eubryP1HjjoHBa1uh2zxfnZ y2yEwujODJ3N06u7YVZBK3iZnNg1bjAuLCD1p364vOycPYhB3EMFp6rIoJK4Bz16ZMfv priw== X-Gm-Message-State: AOAM53078WOmwP3iGzC0sCgeDSgHEHUU35xeZDaa1B2JXMW6Qf1rlCZ9 cTdRSHwCM4Cf9ErYSuwEJiJgJw8hj6OmZw== X-Google-Smtp-Source: ABdhPJwVPbyTja0qy8rjzLP3b2WmVgBGlzqHrT3sXXLEA6SL7H/X1cNmv4Cb79SGO9lIPiVDbXnBAA== X-Received: by 2002:a17:902:dac7:b0:166:4ce4:7e32 with SMTP id q7-20020a170902dac700b001664ce47e32mr26872316plx.168.1654634210244; Tue, 07 Jun 2022 13:36:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 46/71] target/arm: Implement SME LD1, ST1 Date: Tue, 7 Jun 2022 13:32:41 -0700 Message-Id: <20220607203306.657998-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654636931351100001 Content-Type: text/plain; charset="utf-8" We cannot reuse the SVE functions for LD[1-4] and ST[1-4], because those functions accept only a Zreg register number. For SME, we want to pass a pointer into ZA storage. Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 82 +++++ target/arm/sme_helper.c | 615 +++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 69 +++++ target/arm/sme.decode | 9 + 4 files changed, 775 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 600346e08c..5cca01f372 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -32,3 +32,85 @@ DEF_HELPER_FLAGS_4(sme_mova_avz_d, TCG_CALL_NO_RWG, void= , ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sme_mova_zav_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) DEF_HELPER_FLAGS_4(sme_mova_avz_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) DEF_HELPER_FLAGS_4(sme_mova_zav_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i= 32) + +DEF_HELPER_FLAGS_5(sme_ld1b_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_5(sme_ld1b_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_5(sme_ld1b_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl= , i32) +DEF_HELPER_FLAGS_5(sme_ld1b_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl= , i32) + +DEF_HELPER_FLAGS_5(sme_ld1h_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1h_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1h_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_ld1s_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1s_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1s_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_ld1d_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1d_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1d_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_ld1q_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1q_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_ld1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1b_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_5(sme_st1b_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i3= 2) +DEF_HELPER_FLAGS_5(sme_st1b_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl= , i32) +DEF_HELPER_FLAGS_5(sme_st1b_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl= , i32) + +DEF_HELPER_FLAGS_5(sme_st1h_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1h_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1h_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1s_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1s_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1s_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1d_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1d_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1d_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1q_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1q_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl,= i32) +DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 99524ead4d..0c51fbbd49 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -19,10 +19,14 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "internals.h" #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" +#include "exec/cpu_ldst.h" +#include "exec/exec-all.h" #include "qemu/int128.h" #include "vec_internal.h" +#include "sve_ldst_internal.h" =20 /* ResetSVEState */ void arm_reset_sve_state(CPUARMState *env) @@ -192,3 +196,614 @@ void HELPER(sme_mova_zav_q)(void *za, void *vn, void = *vg, uint32_t desc) } } } + +/* + * Clear elements in a tile slice comprising len bytes. + */ + +typedef void ClearFn(void *ptr, size_t off, size_t len); + +static void clear_horizontal(void *ptr, size_t off, size_t len) +{ + memset(ptr + off, 0, len); +} + +static void clear_vertical_b(void *vptr, size_t off, size_t len) +{ + uint8_t *ptr =3D vptr; + size_t i; + + for (i =3D 0; i < len; ++i) { + ptr[(i + off) * sizeof(ARMVectorReg)] =3D 0; + } +} + +static void clear_vertical_h(void *vptr, size_t off, size_t len) +{ + uint16_t *ptr =3D vptr; + size_t i; + + for (i =3D 0; i < len / 2; ++i) { + ptr[(i + off) * sizeof(ARMVectorReg)] =3D 0; + } +} + +static void clear_vertical_s(void *vptr, size_t off, size_t len) +{ + uint32_t *ptr =3D vptr; + size_t i; + + for (i =3D 0; i < len / 4; ++i) { + ptr[(i + off) * sizeof(ARMVectorReg)] =3D 0; + } +} + +static void clear_vertical_d(void *vptr, size_t off, size_t len) +{ + uint64_t *ptr =3D vptr; + size_t i; + + for (i =3D 0; i < len / 8; ++i) { + ptr[(i + off) * sizeof(ARMVectorReg)] =3D 0; + } +} + +static void clear_vertical_q(void *vptr, size_t off, size_t len) +{ + Int128 *ptr =3D vptr, zero =3D int128_zero(); + size_t i; + + for (i =3D 0; i < len / 16; ++i) { + ptr[(i + off) * sizeof(ARMVectorReg)] =3D zero; + } +} + +/* + * Copy elements from an array into a tile slice comprising len bytes. + */ + +typedef void CopyFn(void *dst, const void *src, size_t len); + +static void copy_horizontal(void *dst, const void *src, size_t len) +{ + memcpy(dst, src, len); +} + +static void copy_vertical_b(void *vdst, const void *vsrc, size_t len) +{ + const uint8_t *src =3D vsrc; + uint8_t *dst =3D vdst; + size_t i; + + for (i =3D 0; i < len; ++i) { + dst[i * sizeof(ARMVectorReg)] =3D src[i]; + } +} + +static void copy_vertical_h(void *vdst, const void *vsrc, size_t len) +{ + const uint16_t *src =3D vsrc; + uint16_t *dst =3D vdst; + size_t i; + + for (i =3D 0; i < len / 2; ++i) { + dst[i * sizeof(ARMVectorReg)] =3D src[i]; + } +} + +static void copy_vertical_s(void *vdst, const void *vsrc, size_t len) +{ + const uint32_t *src =3D vsrc; + uint32_t *dst =3D vdst; + size_t i; + + for (i =3D 0; i < len / 4; ++i) { + dst[i * sizeof(ARMVectorReg)] =3D src[i]; + } +} + +static void copy_vertical_d(void *vdst, const void *vsrc, size_t len) +{ + const uint64_t *src =3D vsrc; + uint64_t *dst =3D vdst; + size_t i; + + for (i =3D 0; i < len / 8; ++i) { + dst[i * sizeof(ARMVectorReg)] =3D src[i]; + } +} + +static void copy_vertical_q(void *vdst, const void *vsrc, size_t len) +{ + const Int128 *src =3D vsrc; + Int128 *dst =3D vdst; + size_t i; + + for (i =3D 0; i < len / 16; ++i) { + dst[i * sizeof(ARMVectorReg)] =3D src[i]; + } +} + +/* + * Host and TLB primitives for vertical tile slice addressing. + */ + +#define DO_LD(NAME, TYPE, HOST, TLB) = \ +static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host)= \ +{ = \ + TYPE val =3D HOST(host); = \ + *(TYPE *)(za + off * sizeof(ARMVectorReg)) =3D val; = \ +} = \ +static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za, = \ + intptr_t off, target_ulong addr, uintptr_t ra) = \ +{ = \ + TYPE val =3D TLB(env, useronly_clean_ptr(addr), ra); = \ + *(TYPE *)(za + off * sizeof(ARMVectorReg)) =3D val; = \ +} + +#define DO_ST(NAME, TYPE, HOST, TLB) = \ +static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host)= \ +{ = \ + TYPE val =3D *(TYPE *)(za + off * sizeof(ARMVectorReg)); = \ + HOST(host, val); = \ +} = \ +static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za, = \ + intptr_t off, target_ulong addr, uintptr_t ra) = \ +{ = \ + TYPE val =3D *(TYPE *)(za + off * sizeof(ARMVectorReg)); = \ + TLB(env, useronly_clean_ptr(addr), val, ra); = \ +} + +/* + * FIXME: The ARMVectorReg elements are stored in host-endian 64-bit units. + * We do not have a defined ordering of the 64-bit units for host-endian + * 128-bit quantities. For now, just leave the host words in little-endian + * order and hope for the best. + */ +#define DO_LDQ(HNAME, VNAME, BE, HOST, TLB) = \ +static inline void HNAME##_host(void *za, intptr_t off, void *host) = \ +{ = \ + uint64_t val0 =3D HOST(host), val1 =3D HOST(host + 8); = \ + uint64_t *ptr =3D za + off; = \ + ptr[0] =3D BE ? val1 : val0, ptr[1] =3D BE ? val0 : val1; = \ +} = \ +static inline void VNAME##_v_host(void *za, intptr_t off, void *host) = \ +{ = \ + HNAME##_host(za, off * sizeof(ARMVectorReg), host); = \ +} = \ +static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, = \ + target_ulong addr, uintptr_t ra) = \ +{ = \ + uint64_t val0 =3D TLB(env, useronly_clean_ptr(addr), ra); = \ + uint64_t val1 =3D TLB(env, useronly_clean_ptr(addr + 8), ra); = \ + uint64_t *ptr =3D za + off; = \ + ptr[0] =3D BE ? val1 : val0, ptr[1] =3D BE ? val0 : val1; = \ +} = \ +static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off,= \ + target_ulong addr, uintptr_t ra) = \ +{ = \ + HNAME##_tlb(env, za, off * sizeof(ARMVectorReg), addr, ra); = \ +} + +#define DO_STQ(HNAME, VNAME, BE, HOST, TLB) = \ +static inline void HNAME##_host(void *za, intptr_t off, void *host) = \ +{ = \ + uint64_t *ptr =3D za + off; = \ + HOST(host, ptr[BE]); = \ + HOST(host + 1, ptr[!BE]); = \ +} = \ +static inline void VNAME##_v_host(void *za, intptr_t off, void *host) = \ +{ = \ + HNAME##_host(za, off * sizeof(ARMVectorReg), host); = \ +} = \ +static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, = \ + target_ulong addr, uintptr_t ra) = \ +{ = \ + uint64_t *ptr =3D za + off; = \ + TLB(env, useronly_clean_ptr(addr), ptr[BE], ra); = \ + TLB(env, useronly_clean_ptr(addr + 8), ptr[!BE], ra); = \ +} = \ +static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off,= \ + target_ulong addr, uintptr_t ra) = \ +{ = \ + HNAME##_tlb(env, za, off * sizeof(ARMVectorReg), addr, ra); = \ +} + +DO_LD(ld1b, uint8_t, ldub_p, cpu_ldub_data_ra) +DO_LD(ld1h_be, uint16_t, lduw_be_p, cpu_lduw_be_data_ra) +DO_LD(ld1h_le, uint16_t, lduw_le_p, cpu_lduw_le_data_ra) +DO_LD(ld1s_be, uint32_t, ldl_be_p, cpu_ldl_be_data_ra) +DO_LD(ld1s_le, uint32_t, ldl_le_p, cpu_ldl_le_data_ra) +DO_LD(ld1d_be, uint64_t, ldq_be_p, cpu_ldq_be_data_ra) +DO_LD(ld1d_le, uint64_t, ldq_le_p, cpu_ldq_le_data_ra) + +DO_LDQ(sve_ld1qq_be, sme_ld1q_be, 1, ldq_be_p, cpu_ldq_be_data_ra) +DO_LDQ(sve_ld1qq_le, sme_ld1q_le, 0, ldq_le_p, cpu_ldq_le_data_ra) + +DO_ST(st1b, uint8_t, stb_p, cpu_stb_data_ra) +DO_ST(st1h_be, uint16_t, stw_be_p, cpu_stw_be_data_ra) +DO_ST(st1h_le, uint16_t, stw_le_p, cpu_stw_le_data_ra) +DO_ST(st1s_be, uint32_t, stl_be_p, cpu_stl_be_data_ra) +DO_ST(st1s_le, uint32_t, stl_le_p, cpu_stl_le_data_ra) +DO_ST(st1d_be, uint64_t, stq_be_p, cpu_stq_be_data_ra) +DO_ST(st1d_le, uint64_t, stq_le_p, cpu_stq_le_data_ra) + +DO_STQ(sve_st1qq_be, sme_st1q_be, 1, stq_be_p, cpu_stq_be_data_ra) +DO_STQ(sve_st1qq_le, sme_st1q_le, 0, stq_le_p, cpu_stq_le_data_ra) + +#undef DO_LD +#undef DO_ST +#undef DO_LDQ +#undef DO_STQ + +/* + * Common helper for all contiguous predicated loads. + */ + +static inline QEMU_ALWAYS_INLINE +void sme_ld1(CPUARMState *env, void *za, uint64_t *vg, + const target_ulong addr, uint32_t desc, const uintptr_t ra, + const int esz, uint32_t mtedesc, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn, + ClearFn *clr_fn, + CopyFn *cpy_fn) +{ + const intptr_t reg_max =3D simd_oprsz(desc); + const intptr_t esize =3D 1 << esz; + intptr_t reg_off, reg_last; + SVEContLdSt info; + void *host; + int flags; + + /* Find the active elements. */ + if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, esize)) { + /* The entire predicate was false; no load occurs. */ + clr_fn(za, 0, reg_max); + return; + } + + /* Probe the page(s). Exit with exception for any invalid page. */ + sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, ra); + + /* Handle watchpoints for all active elements. */ + sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize, + BP_MEM_READ, ra); + + /* + * Handle mte checks for all active elements. + * Since TBI must be set for MTE, !mtedesc =3D> !mte_active. + */ + if (mtedesc) { + sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize, + mtedesc, ra); + } + + flags =3D info.page[0].flags | info.page[1].flags; + if (unlikely(flags !=3D 0)) { +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + /* + * At least one page includes MMIO. + * Any bus operation can fail with cpu_transaction_failed, + * which for ARM will raise SyncExternal. Perform the load + * into scratch memory to preserve register state until the end. + */ + ARMVectorReg scratch =3D { }; + + reg_off =3D info.reg_off_first[0]; + reg_last =3D info.reg_off_last[1]; + if (reg_last < 0) { + reg_last =3D info.reg_off_split; + if (reg_last < 0) { + reg_last =3D info.reg_off_last[0]; + } + } + + do { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + tlb_fn(env, &scratch, reg_off, addr + reg_off, ra); + } + reg_off +=3D esize; + } while (reg_off & 63); + } while (reg_off <=3D reg_last); + + cpy_fn(za, &scratch, reg_max); + return; +#endif + } + + /* The entire operation is in RAM, on valid pages. */ + + reg_off =3D info.reg_off_first[0]; + reg_last =3D info.reg_off_last[0]; + host =3D info.page[0].host; + + if (!vertical) { + memset(za, 0, reg_max); + } else if (reg_off) { + clr_fn(za, 0, reg_off); + } + + while (reg_off <=3D reg_last) { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } else if (vertical) { + clr_fn(za, reg_off, esize); + } + reg_off +=3D esize; + } while (reg_off <=3D reg_last && (reg_off & 63)); + } + + /* + * Use the slow path to manage the cross-page misalignment. + * But we know this is RAM and cannot trap. + */ + reg_off =3D info.reg_off_split; + if (unlikely(reg_off >=3D 0)) { + tlb_fn(env, za, reg_off, addr + reg_off, ra); + } + + reg_off =3D info.reg_off_first[1]; + if (unlikely(reg_off >=3D 0)) { + reg_last =3D info.reg_off_last[1]; + host =3D info.page[1].host; + + do { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } else if (vertical) { + clr_fn(za, reg_off, esize); + } + reg_off +=3D esize; + } while (reg_off & 63); + } while (reg_off <=3D reg_last); + } +} + +static inline QEMU_ALWAYS_INLINE +void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg, + target_ulong addr, uint32_t desc, uintptr_t ra, + const int esz, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn, + ClearFn *clr_fn, + CopyFn *cpy_fn) +{ + uint32_t mtedesc =3D desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + int bit55 =3D extract64(addr, 55, 1); + + /* Remove mtedesc from the normal sve descriptor. */ + desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + + /* Perform gross MTE suppression early. */ + if (!tbi_check(desc, bit55) || + tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { + mtedesc =3D 0; + } + + sme_ld1(env, za, vg, addr, desc, ra, esz, mtedesc, vertical, + host_fn, tlb_fn, clr_fn, cpy_fn); +} + +#define DO_LD(L, END, ESZ) = \ +void HELPER(sme_ld1##L##END##_h)(CPUARMState *env, void *za, void *vg, = \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_ld1(env, za, vg, addr, desc, GETPC(), ESZ, 0, false, = \ + sve_ld1##L##L##END##_host, sve_ld1##L##L##END##_tlb, = \ + clear_horizontal, copy_horizontal); = \ +} = \ +void HELPER(sme_ld1##L##END##_v)(CPUARMState *env, void *za, void *vg, = \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_ld1(env, za, vg, addr, desc, GETPC(), ESZ, 0, true, = \ + sme_ld1##L##END##_v_host, sme_ld1##L##END##_v_tlb, = \ + clear_vertical_##L, copy_vertical_##L); = \ +} = \ +void HELPER(sme_ld1##L##END##_h_mte)(CPUARMState *env, void *za, void *vg,= \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_ld1_mte(env, za, vg, addr, desc, GETPC(), ESZ, false, = \ + sve_ld1##L##L##END##_host, sve_ld1##L##L##END##_tlb, = \ + clear_horizontal, copy_horizontal); = \ +} = \ +void HELPER(sme_ld1##L##END##_v_mte)(CPUARMState *env, void *za, void *vg,= \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_ld1_mte(env, za, vg, addr, desc, GETPC(), ESZ, true, = \ + sme_ld1##L##END##_v_host, sme_ld1##L##END##_v_tlb, = \ + clear_vertical_##L, copy_vertical_##L); = \ +} + +DO_LD(b, , MO_8) +DO_LD(h, _be, MO_16) +DO_LD(h, _le, MO_16) +DO_LD(s, _be, MO_32) +DO_LD(s, _le, MO_32) +DO_LD(d, _be, MO_64) +DO_LD(d, _le, MO_64) +DO_LD(q, _be, MO_128) +DO_LD(q, _le, MO_128) + +#undef DO_LD + +/* + * Common helper for all contiguous predicated stores. + */ + +static inline QEMU_ALWAYS_INLINE +void sme_st1(CPUARMState *env, void *za, uint64_t *vg, + const target_ulong addr, uint32_t desc, const uintptr_t ra, + const int esz, uint32_t mtedesc, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn) +{ + const intptr_t reg_max =3D simd_oprsz(desc); + const intptr_t esize =3D 1 << esz; + intptr_t reg_off, reg_last; + SVEContLdSt info; + void *host; + int flags; + + /* Find the active elements. */ + if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, esize)) { + /* The entire predicate was false; no store occurs. */ + return; + } + + /* Probe the page(s). Exit with exception for any invalid page. */ + sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_STORE, ra); + + /* Handle watchpoints for all active elements. */ + sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize, + BP_MEM_WRITE, ra); + + /* + * Handle mte checks for all active elements. + * Since TBI must be set for MTE, !mtedesc =3D> !mte_active. + */ + if (mtedesc) { + sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize, + mtedesc, ra); + } + + flags =3D info.page[0].flags | info.page[1].flags; + if (unlikely(flags !=3D 0)) { +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + /* + * At least one page includes MMIO. + * Any bus operation can fail with cpu_transaction_failed, + * which for ARM will raise SyncExternal. We cannot avoid + * this fault and will leave with the store incomplete. + */ + reg_off =3D info.reg_off_first[0]; + reg_last =3D info.reg_off_last[1]; + if (reg_last < 0) { + reg_last =3D info.reg_off_split; + if (reg_last < 0) { + reg_last =3D info.reg_off_last[0]; + } + } + + do { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + tlb_fn(env, za, reg_off, addr + reg_off, ra); + } + reg_off +=3D esize; + } while (reg_off & 63); + } while (reg_off <=3D reg_last); + return; +#endif + } + + reg_off =3D info.reg_off_first[0]; + reg_last =3D info.reg_off_last[0]; + host =3D info.page[0].host; + + while (reg_off <=3D reg_last) { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } + reg_off +=3D 1 << esz; + } while (reg_off <=3D reg_last && (reg_off & 63)); + } + + /* + * Use the slow path to manage the cross-page misalignment. + * But we know this is RAM and cannot trap. + */ + reg_off =3D info.reg_off_split; + if (unlikely(reg_off >=3D 0)) { + tlb_fn(env, za, reg_off, addr + reg_off, ra); + } + + reg_off =3D info.reg_off_first[1]; + if (unlikely(reg_off >=3D 0)) { + reg_last =3D info.reg_off_last[1]; + host =3D info.page[1].host; + + do { + uint64_t pg =3D vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } + reg_off +=3D 1 << esz; + } while (reg_off & 63); + } while (reg_off <=3D reg_last); + } +} + +static inline QEMU_ALWAYS_INLINE +void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong ad= dr, + uint32_t desc, uintptr_t ra, int esz, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn) +{ + uint32_t mtedesc =3D desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + int bit55 =3D extract64(addr, 55, 1); + + /* Remove mtedesc from the normal sve descriptor. */ + desc =3D extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + + /* Perform gross MTE suppression early. */ + if (!tbi_check(desc, bit55) || + tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { + mtedesc =3D 0; + } + + sme_st1(env, za, vg, addr, desc, ra, esz, mtedesc, + vertical, host_fn, tlb_fn); +} + +#define DO_ST(L, END, ESZ) = \ +void HELPER(sme_st1##L##END##_h)(CPUARMState *env, void *za, void *vg, = \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_st1(env, za, vg, addr, desc, GETPC(), ESZ, 0, false, = \ + sve_st1##L##L##END##_host, sve_st1##L##L##END##_tlb); = \ +} = \ +void HELPER(sme_st1##L##END##_v)(CPUARMState *env, void *za, void *vg, = \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_st1(env, za, vg, addr, desc, GETPC(), ESZ, 0, true, = \ + sme_st1##L##END##_v_host, sme_st1##L##END##_v_tlb); = \ +} = \ +void HELPER(sme_st1##L##END##_h_mte)(CPUARMState *env, void *za, void *vg,= \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_st1_mte(env, za, vg, addr, desc, GETPC(), ESZ, false, = \ + sve_st1##L##L##END##_host, sve_st1##L##L##END##_tlb); = \ +} = \ +void HELPER(sme_st1##L##END##_v_mte)(CPUARMState *env, void *za, void *vg,= \ + target_ulong addr, uint32_t desc) = \ +{ = \ + sme_st1_mte(env, za, vg, addr, desc, GETPC(), ESZ, true, = \ + sme_st1##L##END##_v_host, sme_st1##L##END##_v_tlb); = \ +} + +DO_ST(b, , MO_8) +DO_ST(h, _be, MO_16) +DO_ST(h, _le, MO_16) +DO_ST(s, _be, MO_32) +DO_ST(s, _le, MO_32) +DO_ST(d, _be, MO_64) +DO_ST(d, _le, MO_64) +DO_ST(q, _be, MO_128) +DO_ST(q, _le, MO_128) + +#undef DO_ST diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index d2a7232491..978af74d1d 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -151,3 +151,72 @@ static bool trans_MOVA(DisasContext *s, arg_MOVA *a) =20 return true; } + +static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) +{ + typedef void GenLdSt1(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv, TCGv_i32); + + /* + * Indexed by [esz][be][v][mte][st], which is (except for load/store) + * also the order in which the elements appear in the function names, + * and so how we must concatenate the pieces. + */ + +#define FN_LS(F) { gen_helper_sme_ld1##F, gen_helper_sme_st1##F } +#define FN_MTE(F) { FN_LS(F), FN_LS(F##_mte) } +#define FN_HV(F) { FN_MTE(F##_h), FN_MTE(F##_v) } +#define FN_END(L, B) { FN_HV(L), FN_HV(B) } + + static GenLdSt1 * const fns[5][2][2][2][2] =3D { + FN_END(b, b), + FN_END(h_le, h_be), + FN_END(s_le, s_be), + FN_END(d_le, d_be), + FN_END(q_le, q_be), + }; + +#undef FN_LS +#undef FN_MTE +#undef FN_HV +#undef FN_END + + TCGv_ptr t_za, t_pg; + TCGv_i64 addr; + int desc =3D 0; + bool be =3D s->be_data =3D=3D MO_BE; + bool mte =3D s->mte_active[0]; + + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (!sme_smza_enabled_check(s)) { + return true; + } + + t_za =3D get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v); + t_pg =3D pred_full_reg_ptr(s, a->pg); + addr =3D tcg_temp_new_i64(); + + tcg_gen_shli_i64(addr, cpu_reg(s, a->rn), a->esz); + tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rm)); + + if (mte) { + desc =3D FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); + desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); + desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); + desc =3D FIELD_DP32(desc, MTEDESC, WRITE, a->st); + desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1); + desc <<=3D SVE_MTEDESC_SHIFT; + } else { + addr =3D clean_data_tbi(s, addr); + } + desc =3D simd_desc(s->svl, s->svl, desc); + + fns[a->esz][be][a->v][mte][a->st](cpu_env, t_za, t_pg, addr, + tcg_constant_i32(desc)); + + tcg_temp_free_ptr(t_za); + tcg_temp_free_ptr(t_pg); + tcg_temp_free_i64(addr); + return true; +} diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 241b4895b7..900e3f2a07 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -37,3 +37,12 @@ MOVA 11000000 esz:2 00001 0 v:1 .. pg:3 0 za_= imm:4 zr:5 \ &mova to_vec=3D1 rs=3D%mova_rs MOVA 11000000 11 00001 1 v:1 .. pg:3 0 za_imm:4 zr:5 \ &mova to_vec=3D1 rs=3D%mova_rs esz=3D4 + +### SME Memory + +&ldst esz rs pg rn rm za_imm v:bool st:bool + +LDST1 1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ + &ldst rs=3D%mova_rs +LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ + &ldst esz=3D4 rs=3D%mova_rs --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.36.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:36:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hBZdPZWCdnFknqirCWCAN0zMysKwnh33zUMVY3zWbxw=; b=VnPzvct6ExBmqMauq/Z/J/Bydf16zwg4LzVs6t3BqGDDomRBR6quyXt+yN7JHasilb XWWQs+UA08/SPKrJUDtaMkQCGh+EAQChha3mg8N+HUzObk+QfYFWLlS5NN+eA6nzxcr6 enBZRCR3hnL5k08XyW/mfLdkzrzrWJraJb8yvL+EpMKyki2DiEpWWGQwqK2bUw19grVO fMJrfoB1626+5NcnwoC+q/AsnXOgGRH9D7mK+0+NOZDvAy/mbXWRy9ewrNrtPm0DiK0Q YJmC24LR5cRA49BNgM2um3a6QisP8FjxNidX2cpXR3D55BIZx1fkZ0GO5VuBNHveWmOW c40Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hBZdPZWCdnFknqirCWCAN0zMysKwnh33zUMVY3zWbxw=; b=7l9z/d7g52sIzJfEds4i8gBsgVCF59bRGgqnDerKUyuwRwK6Z6Kcpvo/ahu6NgCKUi HoGwYgIoGfLAJehtixeURf7/sd5Y7noSoEQzHyeaI5ToDda6xRsWbbPbYqNqXmh/gNtz bZr2yEwmKw6TGm7ZlVj7zesJi4sd8J7gKghkQP5XN3X7M23sMNRHVONI/wC1shlnU6xR r3zTSZjEM3x2qzg1lFZnY4ghZm39hzkhEonb6fTLJY7WonfJ8EDNSoOXkAPJbmi2vbTx CxMTnEbpN7eJKPPt9rSQGcQIzMJNY+XfT97Muuw7R0USz8BTrzgKHTIfikndsIOcagZ4 fwzg== X-Gm-Message-State: AOAM533mCw7rpyqFLcdiqHjarUGnB5nYQ8Sos4oRNmYLcptR95WV9SUP VPnyUsx9ms+8uK+NaiWkq6ECSUIk+cRplg== X-Google-Smtp-Source: ABdhPJzM2Irey8UN76H0elPdMn4gjy4KpPdJ5heMAmvX9JNQCvbO9gVoJ01NS1ji5n2zrCTaTc8vug== X-Received: by 2002:a17:902:b090:b0:167:7ae5:e13b with SMTP id p16-20020a170902b09000b001677ae5e13bmr12546288plr.170.1654634211213; Tue, 07 Jun 2022 13:36:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 47/71] target/arm: Export unpredicated ld/st from translate-sve.c Date: Tue, 7 Jun 2022 13:32:42 -0700 Message-Id: <20220607203306.657998-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654636659923100001 Content-Type: text/plain; charset="utf-8" Add a TCGv_ptr base argument, which will be cpu_env for SVE. We will reuse this for SME save and restore array insns. Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 3 +++ target/arm/translate-sve.c | 48 ++++++++++++++++++++++++++++---------- 2 files changed, 39 insertions(+), 12 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index c341c95582..54503745a9 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -165,4 +165,7 @@ void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint3= 2_t rn_ofs, uint32_t rm_ofs, int64_t shift, uint32_t opr_sz, uint32_t max_sz); =20 +void gen_sve_ldr(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int= imm); +void gen_sve_str(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int= imm); + #endif /* TARGET_ARM_TRANSLATE_A64_H */ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 13bdd027a5..adf0cd3e68 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4294,7 +4294,8 @@ TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz, * The load should begin at the address Rn + IMM. */ =20 -static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int im= m) +void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs, + int len, int rn, int imm) { int len_align =3D QEMU_ALIGN_DOWN(len, 8); int len_remain =3D len % 8; @@ -4320,7 +4321,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, in= t len, int rn, int imm) t0 =3D tcg_temp_new_i64(); for (i =3D 0; i < len_align; i +=3D 8) { tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ); - tcg_gen_st_i64(t0, cpu_env, vofs + i); + tcg_gen_st_i64(t0, base, vofs + i); tcg_gen_addi_i64(clean_addr, clean_addr, 8); } tcg_temp_free_i64(t0); @@ -4333,6 +4334,12 @@ static void do_ldr(DisasContext *s, uint32_t vofs, i= nt len, int rn, int imm) clean_addr =3D new_tmp_a64_local(s); tcg_gen_mov_i64(clean_addr, t0); =20 + if (base !=3D cpu_env) { + TCGv_ptr b =3D tcg_temp_local_new_ptr(); + tcg_gen_mov_ptr(b, base); + base =3D b; + } + gen_set_label(loop); =20 t0 =3D tcg_temp_new_i64(); @@ -4340,7 +4347,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, in= t len, int rn, int imm) tcg_gen_addi_i64(clean_addr, clean_addr, 8); =20 tp =3D tcg_temp_new_ptr(); - tcg_gen_add_ptr(tp, cpu_env, i); + tcg_gen_add_ptr(tp, base, i); tcg_gen_addi_ptr(i, i, 8); tcg_gen_st_i64(t0, tp, vofs); tcg_temp_free_ptr(tp); @@ -4348,6 +4355,11 @@ static void do_ldr(DisasContext *s, uint32_t vofs, i= nt len, int rn, int imm) =20 tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); tcg_temp_free_ptr(i); + + if (base !=3D cpu_env) { + tcg_temp_free_ptr(base); + assert(len_remain =3D=3D 0); + } } =20 /* @@ -4376,13 +4388,14 @@ static void do_ldr(DisasContext *s, uint32_t vofs, = int len, int rn, int imm) default: g_assert_not_reached(); } - tcg_gen_st_i64(t0, cpu_env, vofs + len_align); + tcg_gen_st_i64(t0, base, vofs + len_align); tcg_temp_free_i64(t0); } } =20 /* Similarly for stores. */ -static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int im= m) +void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs, + int len, int rn, int imm) { int len_align =3D QEMU_ALIGN_DOWN(len, 8); int len_remain =3D len % 8; @@ -4408,7 +4421,7 @@ static void do_str(DisasContext *s, uint32_t vofs, in= t len, int rn, int imm) =20 t0 =3D tcg_temp_new_i64(); for (i =3D 0; i < len_align; i +=3D 8) { - tcg_gen_ld_i64(t0, cpu_env, vofs + i); + tcg_gen_ld_i64(t0, base, vofs + i); tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); tcg_gen_addi_i64(clean_addr, clean_addr, 8); } @@ -4422,11 +4435,17 @@ static void do_str(DisasContext *s, uint32_t vofs, = int len, int rn, int imm) clean_addr =3D new_tmp_a64_local(s); tcg_gen_mov_i64(clean_addr, t0); =20 + if (base !=3D cpu_env) { + TCGv_ptr b =3D tcg_temp_local_new_ptr(); + tcg_gen_mov_ptr(b, base); + base =3D b; + } + gen_set_label(loop); =20 t0 =3D tcg_temp_new_i64(); tp =3D tcg_temp_new_ptr(); - tcg_gen_add_ptr(tp, cpu_env, i); + tcg_gen_add_ptr(tp, base, i); tcg_gen_ld_i64(t0, tp, vofs); tcg_gen_addi_ptr(i, i, 8); tcg_temp_free_ptr(tp); @@ -4437,12 +4456,17 @@ static void do_str(DisasContext *s, uint32_t vofs, = int len, int rn, int imm) =20 tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); tcg_temp_free_ptr(i); + + if (base !=3D cpu_env) { + tcg_temp_free_ptr(base); + assert(len_remain =3D=3D 0); + } } =20 /* Predicate register stores can be any multiple of 2. */ if (len_remain) { t0 =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(t0, cpu_env, vofs + len_align); + tcg_gen_ld_i64(t0, base, vofs + len_align); =20 switch (len_remain) { case 2: @@ -4474,7 +4498,7 @@ static bool trans_LDR_zri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D vec_full_reg_size(s); int off =3D vec_full_reg_offset(s, a->rd); - do_ldr(s, off, size, a->rn, a->imm * size); + gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } @@ -4487,7 +4511,7 @@ static bool trans_LDR_pri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D pred_full_reg_size(s); int off =3D pred_full_reg_offset(s, a->rd); - do_ldr(s, off, size, a->rn, a->imm * size); + gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } @@ -4500,7 +4524,7 @@ static bool trans_STR_zri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D vec_full_reg_size(s); int off =3D vec_full_reg_offset(s, a->rd); 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([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.36.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:36:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I30aLppER5tQQ7h0Mg89eOPMXEx89vDljlXptRvoUBA=; b=EgRD1GvARjzSsF/ibUsYkZu/godbzrorx3g2Fh0Ox9xwnri/mqzc7EmcEDpFdKt4Yv UcWh6JzAw/QLN06o6aeQmH3dkmAP3E45aBHuPenBIGtrkcUQeMILHH1259XcU/esYojq MTn/Cn9vWLESW5unQTNszLgpUgDeEalBRvfp9jvX/kslsGt/Axt8Lu33PlwYssqwkf8R CXJ3cfAR3Wyijb6EO7KBBKYTstVvmIQTbKbgyT0RjnHNltRlO1wp77vLgmYo/8L48sqh K1rugkmtlCC+ES2oIlIB71vQ7sKRi0mgLLpZj0awSQHJJtbG7zaDKInLbN5OO0sSPisO TKIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I30aLppER5tQQ7h0Mg89eOPMXEx89vDljlXptRvoUBA=; b=5UB/l0EOmO2S6s2dXiXWADhYleX381n3MshUkzJ2+73D+TUt/PCtVe5S9hStWlERtj yM623CLl3ZjjmCvM9cYWs3v2fkqUSedamE2Ki+Ih2deGsgiT9c+AjgGwkJ4yjG88vm3p WsvvDKhHc2RP11Ga1GGW8GKPdbVyKRo0BynRIRvv+PcqKMhQkFqWpqqOzmjW4GX24TMG 8fH2ld66ShsXZ6v7/vspvAyUDlVkQtLUooQ7WeIxfeINyCsLOEc9XaXMX+uREsUjBybt BH1V+isGl1MsHSMMOR2RJvXSZkpPXaxQl+WFQwfix6Vm134NfsJe6lUU9QWgCjUAH1ng ZMRA== X-Gm-Message-State: AOAM530YN3wI8McmjdckVo2w1dFYVRyNhVZwCXVRpcM08dHlLenAVKk2 6Gm8rBrPY+Zo1dfeBSqMOFK8M4/1bQCBpw== X-Google-Smtp-Source: ABdhPJxzBYxkqLBM/ihwGJlYcY4QnxJFvnXQCrJhN2zQLJsbuPv247LZfO4WyokaVCYSFeGtVZUzog== X-Received: by 2002:a17:903:22ca:b0:163:e2b6:e10b with SMTP id y10-20020a17090322ca00b00163e2b6e10bmr31645695plg.28.1654634212249; Tue, 07 Jun 2022 13:36:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 48/71] target/arm: Implement SME LDR, STR Date: Tue, 7 Jun 2022 13:32:43 -0700 Message-Id: <20220607203306.657998-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654637609114100003 Content-Type: text/plain; charset="utf-8" We can reuse the SVE functions for LDR and STR, passing in the base of the ZA vector and a zero offset. Signed-off-by: Richard Henderson --- target/arm/translate-sme.c | 23 +++++++++++++++++++++++ target/arm/sme.decode | 7 +++++++ 2 files changed, 30 insertions(+) diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 978af74d1d..c3e544d69c 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -220,3 +220,26 @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) tcg_temp_free_i64(addr); return true; } + +typedef void GenLdStR(DisasContext *, TCGv_ptr, int, int, int, int); + +static bool do_ldst_r(DisasContext *s, arg_ldstr *a, GenLdStR *fn) +{ + int imm =3D a->imm; + TCGv_ptr base; + + if (!sme_za_enabled_check(s)) { + return true; + } + + /* ZA[n] equates to ZA0H.B[n]. */ + base =3D get_tile_rowcol(s, MO_8, a->rv, imm, false); + + fn(s, base, 0, s->svl, a->rn, imm * s->svl); + + tcg_temp_free_ptr(base); + return true; +} + +TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr) +TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 900e3f2a07..f1ebd857a5 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -46,3 +46,10 @@ LDST1 1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn= :5 0 za_imm:4 \ &ldst rs=3D%mova_rs LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ &ldst esz=3D4 rs=3D%mova_rs + +&ldstr rv rn imm +@ldstr ....... ... . ...... .. ... rn:5 . imm:4 \ + &ldstr rv=3D%mova_rs + +LDR 1110000 100 0 000000 .. 000 ..... 0 .... @ldstr +STR 1110000 100 1 000000 .. 000 ..... 0 .... @ldstr --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654637909; cv=none; d=zohomail.com; s=zohoarc; b=ANqJf9jKwkQTMwMYZVe2qafgy7llXt+6+2z3TCggSFpmYkp4+5OmA/V33hmfRzNjczXxSiZH/5HJ+87kxJ0wIPHQlybgq2sGiWSNK/A/8vnrzDhyw37KmjHEiyss/Bf9YNWdzr2Mj8xv2JE+cgPoMgT6fCelrADIt/pXj0phHDM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654637909; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=g0HsCUjIgZZWzcxGdFc7tKjvpxevFVa5wNGuN3GzHiA=; b=HT0m7qCv3pOgLszqrXVOJ8n0Kvi28lQJ4N16a2hoHVQZI4KIteaIhPYRogQuhoK0zAPZ5nT6JoTPHyYunZdK6BxmxSHwV6R/8l2yFS8nrBSjDY05bS2fI3atciy1IQwGuAyop5yToEd5e8NsoeT3ci/DzSmreprSiLuHJ3zCEPw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654637909629746.0399795620743; Tue, 7 Jun 2022 14:38:29 -0700 (PDT) Received: from localhost ([::1]:35570 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyguC-0002Rb-JI for importer@patchew.org; Tue, 07 Jun 2022 17:38:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35862) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfwj-0006dg-GT for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:01 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:33271) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfwc-0008GF-SW for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:01 -0400 Received: by mail-pj1-x102a.google.com with SMTP id hv24-20020a17090ae41800b001e33eebdb5dso14600264pjb.0 for ; Tue, 07 Jun 2022 13:36:54 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.36.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:36:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g0HsCUjIgZZWzcxGdFc7tKjvpxevFVa5wNGuN3GzHiA=; b=FgtOXI8lWESByZpbreNbKtT9srI308uPfFl+m4DA1mt5N4ZWnpsB7UlqZSkl6ElMWi SpJXhIV/pOJk7m21eHAeMGOhM8JR7QbXLpo8rnoTI4Vb3s60088IGaQ4q0r8jVxUcTnm +A53nfbFQ0uQ38z5gs+/V/5uAv+jHvAUIY3fqE5LPQOEnNdgLUIZk/i6GDT/FVySWUFf jg7hEMNZ1SFQIr6O9qxaXBcD8QKMeMfsqUy+B4yJ6FCHngwHkfzncth3ECsmKCc85uJv kgV0qmZxDKfXzX/wxFKXBYhKN1CQtkuXPkPIoFpLW12MZa0UG9S1cHWp7iqGlFXtOT8u fGyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654637910783100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 5 +++ target/arm/sme_helper.c | 90 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 30 +++++++++++++ target/arm/sme.decode | 11 +++++ 4 files changed, 136 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 5cca01f372..6f0fce7e2c 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -114,3 +114,8 @@ DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, v= oid, env, ptr, ptr, tl, i DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) +DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) +DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) +DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 0c51fbbd49..799e44c047 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -807,3 +807,93 @@ DO_ST(q, _be, MO_128) DO_ST(q, _le, MO_128) =20 #undef DO_ST + +void HELPER(sme_addha_s)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 4; + uint64_t *pn =3D vpn, *pm =3D vpm; + uint32_t * restrict zda =3D vzda, * restrict zn =3D vzn; + + for (row =3D 0; row < oprsz; ) { + uint64_t pa =3D pn[row >> 4]; + do { + if (pa & 1) { + for (col =3D 0; col < oprsz; ) { + uint64_t pb =3D pm[col >> 4]; + do { + if (pb & 1) { + zda[row * sizeof(ARMVectorReg) + col] +=3D zn[= col]; + } + pb >>=3D 4; + } while (++col & 15); + } + } + pa >>=3D 4; + } while (++row & 15); + } +} + +void HELPER(sme_addha_d)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8; + uint8_t *pn =3D vpn, *pm =3D vpm; + uint64_t * restrict zda =3D vzda, * restrict zn =3D vzn; + + for (row =3D 0; row < oprsz; ++row) { + if (pn[H1(row)] & 1) { + for (col =3D 0; col < oprsz; ++col) { + if (pm[H1(col)] & 1) { + zda[row * sizeof(ARMVectorReg) + col] +=3D zn[col]; + } + } + } + } +} + +void HELPER(sme_addva_s)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 4; + uint64_t *pn =3D vpn, *pm =3D vpm; + uint32_t * restrict zda =3D vzda, * restrict zn =3D vzn; + + for (row =3D 0; row < oprsz; ) { + uint64_t pa =3D pn[row >> 4]; + do { + if (pa & 1) { + uint32_t zn_row =3D zn[row]; + for (col =3D 0; col < oprsz; ) { + uint64_t pb =3D pm[col >> 4]; + do { + if (pb & 1) { + zda[row * sizeof(ARMVectorReg) + col] +=3D zn_= row; + } + pb >>=3D 4; + } while (++col & 15); + } + } + pa >>=3D 4; + } while (++row & 15); + } +} + +void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8; + uint8_t *pn =3D vpn, *pm =3D vpm; + uint64_t * restrict zda =3D vzda, * restrict zn =3D vzn; + + for (row =3D 0; row < oprsz; ++row) { + if (pn[H1(row)] & 1) { + uint64_t zn_row =3D zn[row]; + for (col =3D 0; col < oprsz; ++col) { + if (pm[H1(col)] & 1) { + zda[row * sizeof(ARMVectorReg) + col] +=3D zn_row; + } + } + } + } +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index c3e544d69c..e9676b2415 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -243,3 +243,33 @@ static bool do_ldst_r(DisasContext *s, arg_ldstr *a, G= enLdStR *fn) =20 TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr) TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str) + +static bool do_adda(DisasContext *s, arg_adda *a, MemOp esz, + gen_helper_gvec_4 *fn) +{ + uint32_t desc =3D simd_desc(s->svl, s->svl, 0); + TCGv_ptr za, zn, pn, pm; + + if (!sme_smza_enabled_check(s)) { + return true; + } + + /* Sum XZR+zad to find ZAd. */ + za =3D get_tile_rowcol(s, esz, 31, a->zad, false); + zn =3D vec_full_reg_ptr(s, a->zn); + pn =3D pred_full_reg_ptr(s, a->pn); + pm =3D pred_full_reg_ptr(s, a->pm); + + fn(za, zn, pn, pm, tcg_constant_i32(desc)); + + tcg_temp_free_ptr(za); + tcg_temp_free_ptr(zn); + tcg_temp_free_ptr(pn); + tcg_temp_free_ptr(pm); + return true; +} + +TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addha_s) +TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s) +TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= ha_d) +TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= va_d) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index f1ebd857a5..8cb6c4053c 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -53,3 +53,14 @@ LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn= :5 0 za_imm:4 \ =20 LDR 1110000 100 0 000000 .. 000 ..... 0 .... @ldstr STR 1110000 100 1 000000 .. 000 ..... 0 .... @ldstr + +### SME Add Vector to Array + +&adda zad zn pm pn +@adda_32 ........ .. ..... . pm:3 pn:3 zn:5 ... zad:2 &adda +@adda_64 ........ .. ..... . pm:3 pn:3 zn:5 .. zad:3 &adda + +ADDHA_s 11000000 10 01000 0 ... ... ..... 000 .. @adda_32 +ADDVA_s 11000000 10 01000 1 ... ... ..... 000 .. @adda_32 +ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64 +ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64 --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654637330844100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 5 +++ target/arm/sme_helper.c | 67 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 33 +++++++++++++++++++ target/arm/sme.decode | 9 +++++ 4 files changed, 114 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 6f0fce7e2c..727095a3eb 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -119,3 +119,8 @@ DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) + +DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 799e44c047..62d9690cae 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -25,6 +25,7 @@ #include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "qemu/int128.h" +#include "fpu/softfloat.h" #include "vec_internal.h" #include "sve_ldst_internal.h" =20 @@ -897,3 +898,69 @@ void HELPER(sme_addva_d)(void *vzda, void *vzn, void *= vpn, } } } + +void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, void *vst, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_maxsz(desc); + uint32_t neg =3D simd_data(desc) << 31; + uint16_t *pn =3D vpn, *pm =3D vpm; + + bool save_dn =3D get_default_nan_mode(vst); + set_default_nan_mode(true, vst); + + for (row =3D 0; row < oprsz; ) { + uint16_t pa =3D pn[H2(row >> 4)]; + do { + if (pa & 1) { + void *vza_row =3D vza + row * sizeof(ARMVectorReg); + uint32_t n =3D *(uint32_t *)(vzn + row) ^ neg; + + for (col =3D 0; col < oprsz; ) { + uint16_t pb =3D pm[H2(col >> 4)]; + do { + if (pb & 1) { + uint32_t *a =3D vza_row + col; + uint32_t *m =3D vzm + col; + *a =3D float32_muladd(n, *m, *a, 0, vst); + } + col +=3D 4; + pb >>=3D 4; + } while (col & 15); + } + } + row +=3D 4; + pa >>=3D 4; + } while (row & 15); + } + + set_default_nan_mode(save_dn, vst); +} + +void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, void *vst, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8; + uint64_t neg =3D (uint64_t)simd_data(desc) << 63; + uint64_t *za =3D vza, *zn =3D vzn, *zm =3D vzm; + uint8_t *pn =3D vpn, *pm =3D vpm; + + bool save_dn =3D get_default_nan_mode(vst); + set_default_nan_mode(true, vst); + + for (row =3D 0; row < oprsz; ++row) { + if (pn[H1(row)] & 1) { + uint64_t *za_row =3D &za[row * sizeof(ARMVectorReg)]; + uint64_t n =3D zn[row] ^ neg; + + for (col =3D 0; col < oprsz; ++col) { + if (pm[H1(col)] & 1) { + uint64_t *a =3D &za_row[col]; + *a =3D float64_muladd(n, zm[col], *a, 0, vst); + } + } + } + } + + set_default_nan_mode(save_dn, vst); +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index e9676b2415..e6e4541e76 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -273,3 +273,36 @@ TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_h= elper_sme_addha_s) TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s) TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= ha_d) TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= va_d) + +static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, + gen_helper_gvec_5_ptr *fn) +{ + uint32_t desc =3D simd_desc(s->svl, s->svl, a->sub); + TCGv_ptr za, zn, zm, pn, pm, fpst; + + if (!sme_smza_enabled_check(s)) { + return true; + } + + /* Sum XZR+zad to find ZAd. */ + za =3D get_tile_rowcol(s, esz, 31, a->zad, false); + zn =3D vec_full_reg_ptr(s, a->zn); + zm =3D vec_full_reg_ptr(s, a->zm); + pn =3D pred_full_reg_ptr(s, a->pn); + pm =3D pred_full_reg_ptr(s, a->pm); + fpst =3D fpstatus_ptr(FPST_FPCR); + + fn(za, zn, zm, pn, pm, fpst, tcg_constant_i32(desc)); + + tcg_temp_free_ptr(za); + tcg_temp_free_ptr(zn); + tcg_temp_free_ptr(pn); + tcg_temp_free_ptr(pm); + tcg_temp_free_ptr(fpst); + return true; +} + +TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, + a, MO_32, gen_helper_sme_fmopa_s) +TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, + a, MO_64, gen_helper_sme_fmopa_d) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 8cb6c4053c..ba4774d174 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -64,3 +64,12 @@ ADDHA_s 11000000 10 01000 0 ... ... ..... 000 ..= @adda_32 ADDVA_s 11000000 10 01000 1 ... ... ..... 000 .. @adda_32 ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64 ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64 + +### SME Outer Product + +&op zad zn zm pm pn sub:bool +@op_32 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 .. zad:2 &op +@op_64 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 . zad:3 &op + +FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32 +FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654637844448100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 2 ++ target/arm/sme_helper.c | 52 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 29 +++++++++++++++++++++ target/arm/sme.decode | 2 ++ 4 files changed, 85 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 727095a3eb..6b36542133 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -124,3 +124,5 @@ DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 62d9690cae..61bab73cb7 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -964,3 +964,55 @@ void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *v= zm, void *vpn, =20 set_default_nan_mode(save_dn, vst); } + +/* + * Alter PAIR as needed for controlling predicates being false, + * and for NEG on an enabled row element. + */ +static inline uint32_t f16mop_adj_pair(uint32_t pair, uint32_t pg, uint32_= t neg) +{ + pair ^=3D neg; + if (!(pg & 1)) { + pair &=3D 0xffff0000u; + } + if (!(pg & 4)) { + pair &=3D 0x0000ffffu; + } + return pair; +} + +void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_maxsz(desc); + uint32_t neg =3D simd_data(desc) << 15; + uint16_t *pn =3D vpn, *pm =3D vpm; + + for (row =3D 0; row < oprsz; ) { + uint16_t pa =3D pn[H2(row >> 4)]; + do { + void *vza_row =3D vza + row * sizeof(ARMVectorReg); + uint32_t n =3D *(uint32_t *)(vzn + row); + + n =3D f16mop_adj_pair(n, pa, neg); + + for (col =3D 0; col < oprsz; ) { + uint16_t pb =3D pm[H2(col >> 4)]; + do { + if ((pa & 0b0101) =3D=3D 0b0101 || (pb & 0b0101) =3D= =3D 0b0101) { + uint32_t *a =3D vza_row + col; + uint32_t m =3D *(uint32_t *)(vzm + col); + + m =3D f16mop_adj_pair(m, pb, neg); + *a =3D bfdotadd(*a, n, m); + + col +=3D 4; + pb >>=3D 4; + } + } while (col & 15); + } + row +=3D 4; + pa >>=3D 4; + } while (row & 15); + } +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index e6e4541e76..581bf9174f 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -274,6 +274,32 @@ TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_h= elper_sme_addva_s) TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= ha_d) TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= va_d) =20 +static bool do_outprod(DisasContext *s, arg_op *a, MemOp esz, + gen_helper_gvec_5 *fn) +{ + uint32_t desc =3D simd_desc(s->svl, s->svl, a->sub); + TCGv_ptr za, zn, zm, pn, pm; + + if (!sme_smza_enabled_check(s)) { + return true; + } + + /* Sum XZR+zad to find ZAd. */ + za =3D get_tile_rowcol(s, esz, 31, a->zad, false); + zn =3D vec_full_reg_ptr(s, a->zn); + zm =3D vec_full_reg_ptr(s, a->zm); + pn =3D pred_full_reg_ptr(s, a->pn); + pm =3D pred_full_reg_ptr(s, a->pm); + + fn(za, zn, zm, pn, pm, tcg_constant_i32(desc)); + + tcg_temp_free_ptr(za); + tcg_temp_free_ptr(zn); + tcg_temp_free_ptr(pn); + tcg_temp_free_ptr(pm); + return true; +} + static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, gen_helper_gvec_5_ptr *fn) { @@ -306,3 +332,6 @@ TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_s) TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_fmopa_d) + +/* TODO: FEAT_EBF16 */ +TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index ba4774d174..afd9c0dffd 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -73,3 +73,5 @@ ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... = @adda_64 =20 FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32 FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 + +BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654638482547100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 2 ++ target/arm/sme_helper.c | 74 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 2 ++ target/arm/sme.decode | 1 + 4 files changed, 79 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 6b36542133..ecc957be14 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -120,6 +120,8 @@ DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) =20 +DEF_HELPER_FLAGS_7(sme_fmopa_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 61bab73cb7..6863a204d4 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -981,6 +981,80 @@ static inline uint32_t f16mop_adj_pair(uint32_t pair, = uint32_t pg, uint32_t neg) return pair; } =20 +static float32 f16_dotadd(float32 sum, uint32_t e1, uint32_t e2, + float_status *s) +{ + float64 e1r =3D float16_to_float64(e1 & 0xffff, true, s); + float64 e1c =3D float16_to_float64(e1 >> 16, true, s); + float64 e2r =3D float16_to_float64(e2 & 0xffff, true, s); + float64 e2c =3D float16_to_float64(e2 >> 16, true, s); + float64 t64; + float32 t32; + + /* + * The ARM pseudocode function FPDot performs both multiplies + * and the add with a single rounding operation. Emulate this + * by performing the first multiply in round-to-odd, then doing + * the second multiply as fused multiply-add, and rounding to + * float32 all in one step. + */ + FloatRoundMode old_rm =3D get_float_rounding_mode(s); + set_float_rounding_mode(float_round_to_odd, s); + + t64 =3D float64_mul(e1r, e2r, s); + + set_float_rounding_mode(old_rm, s); + + t64 =3D float64r32_muladd(e1c, e2c, t64, 0, s); + + /* This conversion is exact, because we've already rounded. */ + t32 =3D float64_to_float32(t64, s); + + /* The final accumulation step is not fused. */ + return float32_add(sum, t32, s); +} + +void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, void *vst, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_maxsz(desc); + uint32_t neg =3D simd_data(desc) << 15; + uint16_t *pn =3D vpn, *pm =3D vpm; + + bool save_dn =3D get_default_nan_mode(vst); + set_default_nan_mode(true, vst); + + for (row =3D 0; row < oprsz; ) { + uint16_t pa =3D pn[H2(row >> 4)]; + do { + void *vza_row =3D vza + row * sizeof(ARMVectorReg); + uint32_t n =3D *(uint32_t *)(vzn + row); + + n =3D f16mop_adj_pair(n, pa, neg); + + for (col =3D 0; col < oprsz; ) { + uint16_t pb =3D pm[H2(col >> 4)]; + do { + if ((pa & 0b0101) =3D=3D 0b0101 || (pb & 0b0101) =3D= =3D 0b0101) { + uint32_t *a =3D vza_row + col; + uint32_t m =3D *(uint32_t *)(vzm + col); + + m =3D f16mop_adj_pair(m, pb, neg); + *a =3D f16_dotadd(*a, n, m, vst); + + col +=3D 4; + pb >>=3D 4; + } + } while (col & 15); + } + row +=3D 4; + pa >>=3D 4; + } while (row & 15); + } + + set_default_nan_mode(save_dn, vst); +} + void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, void *vpm, uint32_t desc) { diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 581bf9174f..847f2274b1 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -328,6 +328,8 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a,= MemOp esz, return true; } =20 +TRANS_FEAT(FMOPA_h, aa64_sme, do_outprod_fpst, + a, MO_32, gen_helper_sme_fmopa_h) TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_s) TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, diff --git a/target/arm/sme.decode b/target/arm/sme.decode index afd9c0dffd..e8d27fd8a0 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -75,3 +75,4 @@ FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. = @op_32 FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 =20 BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 +FMOPA_h 10000001 101 ..... ... ... ..... . 00 .. @op_32 --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654639019; cv=none; d=zohomail.com; s=zohoarc; b=QlycmqkP6Td1CEP5tMHWy5g4ijozalb9dfwY5aReyj6VZTSWLALwuskaQjBlO2EF4P2sqYbk3nUJClmkK7FsZwWQ9/aCkPQDwaYrJBqzX1E58QKVqJRHX7V/K/lyHU04DafpyCf5fnI/1L2MLRFBJcRtGstAnkImkhtf/OwVCDw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654639019; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=P3dYy/A12nx0G1t49jYKdalrUiIu02UDHCUpuUcsXPY=; b=ThSOw8HMzqAgCq+qM8DF5cFRrxcA38BOAKviX5UeKYKe6vQdHYgpyY8fpkdckxqxcRZB0nEMBQT8oYDZITpPwO9lmT5C7tdYd0Sdi192+iVEZDBYw/1Zn6y6X8kR85gGf9edpb3xdiWgIERkytv67hoe1MBZU67g3SfRagPryPs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654639019312132.0323500777613; Tue, 7 Jun 2022 14:56:59 -0700 (PDT) Received: from localhost ([::1]:47038 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyhC5-0004Hn-3C for importer@patchew.org; Tue, 07 Jun 2022 17:56:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36202) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfws-00077U-I5 for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:10 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:39743) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfwg-0008I6-9N for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:10 -0400 Received: by mail-pf1-x42d.google.com with SMTP id y196so16509350pfb.6 for ; Tue, 07 Jun 2022 13:36:57 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.36.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:36:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P3dYy/A12nx0G1t49jYKdalrUiIu02UDHCUpuUcsXPY=; b=YytLFE4J+SP/ubtkWeW6OIeAUeuukVU2wnxaQLQcgqanDZGQvXRJLyRqG0vJvRcFrn usCeGCnIm8rvmymdMW66JBNBmS4mmaaLLhyun+9K9egEUhJclTx1azWPeRN3DL8XO+WY 2p/lNe1p6aFHMDxyRl300fbAXBSbdfpI3Eka5N+FvwQczdm+9a8XddhXsqAMNWFfIZeH oQdksqCLJadZiSnRqEBY3QdnyTglpPs19umlApQoi3txDTNqMiMBi6E0oesOX62aQxjX drstlRItTJRJSfzZxPvSV54BwIpXzAG3u+LKH6K0D24iCN1yfR2880UPC8RjliS+b+F/ 1h5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P3dYy/A12nx0G1t49jYKdalrUiIu02UDHCUpuUcsXPY=; b=U6EcZk5x3sMDgmyH3zEW8cHNV72jGiwUacE/nGB21koHsOBykh7ol4qEFbXih7bAfT z1rpaciw95W8gexCElBNQa6whYJ3Kwjr8GGUacLsr+4Sk3E1av1fBOPkHw+EGqcC4lPh zJ370DGW5SgYJGvh8bqjtIe3jm2OJY78MLp4n2cOH8TY+sl6ChNvJF08zuGE3iVkbxjI jdS1g82XpQOwGACsYTLxB8EFtKtQUlxVb2+1dyUq22dtTBApgO9KF3tGwCdX4m6J4/TR vzzVK9mpnfiD1V/V0PBn8cHvE50zB0IpN6jyt+KlE+WDlgyhPHfF2aJnsHZRYML1djPD 8xng== X-Gm-Message-State: AOAM532tO9MghXl1RO14cXYls0adc5tAZYo3ZtNNIUqp3jhIQgYLH2MK S4+LQAXn/iOEf5FV4BNJZdJl2k3b9PwA+A== X-Google-Smtp-Source: ABdhPJwtsXSSZ2sYI0PKxo4bIB5XghuZk1f9L58ozqhEMGOujRt9EMGfmT2lZt3L2bBt5mN1spK08A== X-Received: by 2002:a05:6a00:1745:b0:51b:de90:aefb with SMTP id j5-20020a056a00174500b0051bde90aefbmr25278053pfc.11.1654634216902; Tue, 07 Jun 2022 13:36:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 53/71] target/arm: Implement SME integer outer product Date: Tue, 7 Jun 2022 13:32:48 -0700 Message-Id: <20220607203306.657998-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654639019806100001 Content-Type: text/plain; charset="utf-8" This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16. Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 16 ++++++++ target/arm/sme_helper.c | 82 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 14 +++++++ target/arm/sme.decode | 10 +++++ 4 files changed, 122 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index ecc957be14..31562551ee 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -128,3 +128,19 @@ DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_smopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_umopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_sumopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_usmopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_smopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_umopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_sumopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_usmopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 6863a204d4..f1c7e6ae56 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -1090,3 +1090,85 @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *= vzm, void *vpn, } while (row & 15); } } + +typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool); + +static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm, + uint8_t *pn, uint8_t *pm, + uint32_t desc, IMOPFn *fn) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8; + bool neg =3D simd_data(desc); + + for (row =3D 0; row < oprsz; ++row) { + uint8_t pa =3D pn[H1(row)]; + uint64_t *za_row =3D &za[row * sizeof(ARMVectorReg)]; + uint64_t n =3D zn[row]; + + for (col =3D 0; col < oprsz; ++col) { + uint8_t pb =3D pm[H1(col)]; + uint64_t *a =3D &za_row[col]; + + *a =3D fn(n, zm[col], *a, pa & pb, neg); + } + } +} + +#define DEF_IMOP_32(NAME, NTYPE, MTYPE) \ +static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool n= eg) \ +{ = \ + uint32_t sum0 =3D 0, sum1 =3D 0; = \ + /* Apply P to N as a mask, making the inactive elements 0. */ = \ + n &=3D expand_pred_b(p); = \ + sum0 +=3D (NTYPE)(n >> 0) * (MTYPE)(m >> 0); = \ + sum0 +=3D (NTYPE)(n >> 8) * (MTYPE)(m >> 8); = \ + sum0 +=3D (NTYPE)(n >> 16) * (MTYPE)(m >> 16); = \ + sum0 +=3D (NTYPE)(n >> 24) * (MTYPE)(m >> 24); = \ + sum1 +=3D (NTYPE)(n >> 32) * (MTYPE)(m >> 32); = \ + sum1 +=3D (NTYPE)(n >> 40) * (MTYPE)(m >> 40); = \ + sum1 +=3D (NTYPE)(n >> 48) * (MTYPE)(m >> 48); = \ + sum1 +=3D (NTYPE)(n >> 56) * (MTYPE)(m >> 56); = \ + if (neg) { = \ + sum0 =3D (uint32_t)a - sum0, sum1 =3D (uint32_t)(a >> 32) - sum1; = \ + } else { = \ + sum0 =3D (uint32_t)a + sum0, sum1 =3D (uint32_t)(a >> 32) + sum1; = \ + } = \ + return ((uint64_t)sum1 << 32) | sum0; = \ +} + +#define DEF_IMOP_64(NAME, NTYPE, MTYPE) \ +static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool n= eg) \ +{ = \ + uint64_t sum =3D 0; = \ + /* Apply P to N as a mask, making the inactive elements 0. */ = \ + n &=3D expand_pred_h(p); = \ + sum +=3D (NTYPE)(n >> 0) * (MTYPE)(m >> 0); = \ + sum +=3D (NTYPE)(n >> 16) * (MTYPE)(m >> 16); = \ + sum +=3D (NTYPE)(n >> 32) * (MTYPE)(m >> 32); = \ + sum +=3D (NTYPE)(n >> 48) * (MTYPE)(m >> 48); = \ + return neg ? a - sum : a + sum; = \ +} + +DEF_IMOP_32(smopa_s, int8_t, int8_t) +DEF_IMOP_32(umopa_s, uint8_t, uint8_t) +DEF_IMOP_32(sumopa_s, int8_t, uint8_t) +DEF_IMOP_32(usmopa_s, uint8_t, int8_t) + +DEF_IMOP_64(smopa_d, int16_t, int16_t) +DEF_IMOP_64(umopa_d, uint16_t, uint16_t) +DEF_IMOP_64(sumopa_d, int16_t, uint16_t) +DEF_IMOP_64(usmopa_d, uint16_t, int16_t) + +#define DEF_IMOPH(NAME) \ + void HELPER(sme_##NAME)(void *vza, void *vzn, void *vzm, void *vpn, = \ + void *vpm, uint32_t desc) = \ + { do_imopa(vza, vzn, vzm, vpn, vpm, desc, NAME); } + +DEF_IMOPH(smopa_s) +DEF_IMOPH(umopa_s) +DEF_IMOPH(sumopa_s) +DEF_IMOPH(usmopa_s) +DEF_IMOPH(smopa_d) +DEF_IMOPH(umopa_d) +DEF_IMOPH(sumopa_d) +DEF_IMOPH(usmopa_d) diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 847f2274b1..4aa0aff25c 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -337,3 +337,17 @@ TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, =20 /* TODO: FEAT_EBF16 */ TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa) + +TRANS_FEAT(SMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_smopa_s) +TRANS_FEAT(UMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_umopa_s) +TRANS_FEAT(SUMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_sumopa= _s) +TRANS_FEAT(USMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_usmopa= _s) + +TRANS_FEAT(SMOPA_d, aa64_sme_i16i64, do_outprod, + a, MO_64, gen_helper_sme_smopa_d) +TRANS_FEAT(UMOPA_d, aa64_sme_i16i64, do_outprod, + a, MO_64, gen_helper_sme_umopa_d) +TRANS_FEAT(SUMOPA_d, aa64_sme_i16i64, do_outprod, + a, MO_64, gen_helper_sme_sumopa_d) +TRANS_FEAT(USMOPA_d, aa64_sme_i16i64, do_outprod, + a, MO_64, gen_helper_sme_usmopa_d) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index e8d27fd8a0..628804e37a 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -76,3 +76,13 @@ FMOPA_d 10000000 110 ..... ... ... ..... . 0 ...= @op_64 =20 BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 FMOPA_h 10000001 101 ..... ... ... ..... . 00 .. @op_32 + +SMOPA_s 1010000 0 10 0 ..... ... ... ..... . 00 .. @op_32 +SUMOPA_s 1010000 0 10 1 ..... ... ... ..... . 00 .. @op_32 +USMOPA_s 1010000 1 10 0 ..... ... ... ..... . 00 .. @op_32 +UMOPA_s 1010000 1 10 1 ..... ... ... ..... . 00 .. @op_32 + +SMOPA_d 1010000 0 11 0 ..... ... ... ..... . 0 ... @op_64 +SUMOPA_d 1010000 0 11 1 ..... ... ... ..... . 0 ... @op_64 +USMOPA_d 1010000 1 11 0 ..... ... ... ..... . 0 ... @op_64 +UMOPA_d 1010000 1 11 1 ..... ... ... ..... . 0 ... @op_64 --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654637886; cv=none; d=zohomail.com; s=zohoarc; b=Z3kdN5OMg3EjwRcCAvo8DfWf4prPKWh8qghLg2UlFLzfpFN8rFJVrgnfP9TjpqUAuvU07R+nkWuBaNCw+2ZaDG3KlW0zVMjblXIGUqnHba2QayMyxs5EAc9KoyjXgo6Gg52UnsgecZA1D3HNtlVisvkHBbmA4eGqrss4Xz2Yhfw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654637886; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NiB9V9EV1LP0rfQ3iNUj/Y5UvVHOZ8S0mDKCyW2xkxg=; b=lKZWs3ejQxiRaqiu0DAAPiQIz5Gxu4gvtiqukNHfA2UNTHjrrhgXfMb3dU6JXareCatNBoRzpBcsJK8VM/BFD4cZTrA0KgTYFsVxLswRILun66yHiAjBXUejMFNiV1faf8PajgKtGz+BGYYeoWVdbWBk8tjRk5cjXEv5O31Q+HU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654637886596815.9191385471801; Tue, 7 Jun 2022 14:38:06 -0700 (PDT) Received: from localhost ([::1]:34228 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygtp-0001Yg-Fv for importer@patchew.org; Tue, 07 Jun 2022 17:38:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36032) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfwo-0006vb-Jr for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:06 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:46733) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfwg-0008IP-W4 for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:06 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d13so141414plh.13 for ; Tue, 07 Jun 2022 13:36:58 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654637888589100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 57 ++++++++++++++++++++++++++++++++++++++ target/arm/sve.decode | 20 +++++++++++++ 2 files changed, 77 insertions(+) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index adf0cd3e68..58d0894e15 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7379,3 +7379,60 @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr= _esz *a, bool sel) =20 TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false) TRANS_FEAT(BFMLALT_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, true) + +static bool trans_PSEL(DisasContext *s, arg_psel *a) +{ + int vl =3D vec_full_reg_size(s); + int pl =3D pred_gvec_reg_size(s); + int elements =3D vl >> a->esz; + TCGv_i64 tmp, didx, dbit; + TCGv_ptr ptr; + + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (!sve_access_check(s)) { + return true; + } + + tmp =3D tcg_temp_new_i64(); + dbit =3D tcg_temp_new_i64(); + didx =3D tcg_temp_new_i64(); + ptr =3D tcg_temp_new_ptr(); + + /* Compute the predicate element. */ + tcg_gen_addi_i64(tmp, cpu_reg(s, a->rv), a->imm); + if (is_power_of_2(elements)) { + tcg_gen_andi_i64(tmp, tmp, elements - 1); + } else { + tcg_gen_remu_i64(tmp, tmp, tcg_constant_i64(elements)); + } + + /* Extract the predicate byte and bit indices. */ + tcg_gen_shli_i64(tmp, tmp, a->esz); + tcg_gen_andi_i64(dbit, tmp, 7); + tcg_gen_shri_i64(didx, tmp, 3); + if (HOST_BIG_ENDIAN) { + tcg_gen_xori_i64(didx, didx, 7); + } + + /* Load the predicate word. */ + tcg_gen_trunc_i64_ptr(ptr, didx); + tcg_gen_add_ptr(ptr, ptr, cpu_env); + tcg_gen_ld8u_i64(tmp, ptr, pred_full_reg_offset(s, a->pm)); + + /* Extract the predicate bit and replicate to MO_64. */ + tcg_gen_shr_i64(tmp, tmp, dbit); + tcg_gen_andi_i64(tmp, tmp, 1); + tcg_gen_neg_i64(tmp, tmp); + + /* Apply to either copy the source, or write zeros. */ + tcg_gen_gvec_ands(MO_64, pred_full_reg_offset(s, a->pd), + pred_full_reg_offset(s, a->pn), tmp, pl, pl); + + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(dbit); + tcg_temp_free_i64(didx); + tcg_temp_free_ptr(ptr); + return true; +} diff --git a/target/arm/sve.decode b/target/arm/sve.decode index bbdaac6ac7..bf561c270a 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1674,3 +1674,23 @@ BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ...= .. @rrxr_3a esz=3D2 =20 ### SVE2 floating-point bfloat16 dot-product (indexed) BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=3D2 + +### SVE broadcast predicate element + +&psel esz pd pn pm rv imm +%psel_rv 16:2 !function=3Dplus_12 +%psel_imm_b 22:2 19:2 +%psel_imm_h 22:2 20:1 +%psel_imm_s 22:2 +%psel_imm_d 23:1 +@psel ........ .. . ... .. .. pn:4 . pm:4 . pd:4 \ + &psel rv=3D%psel_rv + +PSEL 00100101 .. 1 ..1 .. 01 .... 0 .... 0 .... \ + @psel esz=3D0 imm=3D%psel_imm_b +PSEL 00100101 .. 1 .10 .. 01 .... 0 .... 0 .... \ + @psel esz=3D1 imm=3D%psel_imm_h +PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \ + @psel esz=3D2 imm=3D%psel_imm_s +PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ + @psel esz=3D3 imm=3D%psel_imm_d --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654638150549100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 2 ++ target/arm/sve_helper.c | 16 ++++++++++++++++ target/arm/translate-sve.c | 2 ++ target/arm/sve.decode | 1 + 4 files changed, 21 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index ab0333400f..cc4e1d8948 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -719,6 +719,8 @@ DEF_HELPER_FLAGS_4(sve_revh_d, TCG_CALL_NO_RWG, void, p= tr, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_4(sve_revw_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(sme_revd_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(sve_rbit_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_rbit_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_rbit_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 9a26f253e0..5de82696b5 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -931,6 +931,22 @@ DO_ZPZ_D(sve_revh_d, uint64_t, hswap64) =20 DO_ZPZ_D(sve_revw_d, uint64_t, wswap64) =20 +void HELPER(sme_revd_q)(void *vd, void *vn, void *vg, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc) / 8; + uint64_t *d =3D vd, *n =3D vn; + uint8_t *pg =3D vg; + + for (i =3D 0; i < opr_sz; i +=3D 2) { + if (pg[H1(i)] & 1) { + uint64_t n0 =3D n[i + 0]; + uint64_t n1 =3D n[i + 1]; + d[i + 0] =3D n1; + d[i + 1] =3D n0; + } + } +} + DO_ZPZ(sve_rbit_b, uint8_t, H1, revbit8) DO_ZPZ(sve_rbit_h, uint16_t, H1_2, revbit16) DO_ZPZ(sve_rbit_s, uint32_t, H1_4, revbit32) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 58d0894e15..1129f1fc56 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -2896,6 +2896,8 @@ TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh= _fns[a->esz], a, 0) TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz, a->esz =3D=3D 3 ? gen_helper_sve_revw_d : NULL, a, 0) =20 +TRANS_FEAT(REVD, aa64_sme, gen_gvec_ool_arg_zpz, gen_helper_sme_revd_q, a,= 0) + TRANS_FEAT(SPLICE, aa64_sve, gen_gvec_ool_arg_zpzz, gen_helper_sve_splice, a, a->esz) =20 diff --git a/target/arm/sve.decode b/target/arm/sve.decode index bf561c270a..d1e229fd6e 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -652,6 +652,7 @@ REVB 00000101 .. 1001 00 100 ... ..... .....= @rd_pg_rn REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn +REVD 00000101 00 1011 10 100 ... ..... ..... @rd_pg_rn_= e0 =20 # SVE vector splice (predicated, destructive) SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654638281178100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper.h | 18 +++++++ target/arm/translate-sve.c | 102 +++++++++++++++++++++++++++++++++++++ target/arm/vec_helper.c | 24 +++++++++ target/arm/sve.decode | 5 ++ 4 files changed, 149 insertions(+) diff --git a/target/arm/helper.h b/target/arm/helper.h index 5bca7255f1..f9bc4b29b4 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1017,6 +1017,24 @@ DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_uclamp_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 1129f1fc56..40c5bf1a55 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7438,3 +7438,105 @@ static bool trans_PSEL(DisasContext *s, arg_psel *a) tcg_temp_free_ptr(ptr); return true; } + +static void gen_sclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a) +{ + tcg_gen_smax_i32(d, a, n); + tcg_gen_smin_i32(d, d, m); +} + +static void gen_sclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a) +{ + tcg_gen_smax_i64(d, a, n); + tcg_gen_smin_i64(d, d, m); +} + +static void gen_sclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n, + TCGv_vec m, TCGv_vec a) +{ + tcg_gen_smax_vec(vece, d, a, n); + tcg_gen_smin_vec(vece, d, d, m); +} + +static void gen_sclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m, + uint32_t a, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop[] =3D { + INDEX_op_smin_vec, INDEX_op_smax_vec, 0 + }; + static const GVecGen4 ops[4] =3D { + { .fniv =3D gen_sclamp_vec, + .fno =3D gen_helper_gvec_sclamp_b, + .opt_opc =3D vecop, + .vece =3D MO_8 }, + { .fniv =3D gen_sclamp_vec, + .fno =3D gen_helper_gvec_sclamp_h, + .opt_opc =3D vecop, + .vece =3D MO_16 }, + { .fni4 =3D gen_sclamp_i32, + .fniv =3D gen_sclamp_vec, + .fno =3D gen_helper_gvec_sclamp_s, + .opt_opc =3D vecop, + .vece =3D MO_32 }, + { .fni8 =3D gen_sclamp_i64, + .fniv =3D gen_sclamp_vec, + .fno =3D gen_helper_gvec_sclamp_d, + .opt_opc =3D vecop, + .vece =3D MO_64, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64 } + }; + tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]); +} + +TRANS_FEAT(SCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_sclamp, a) + +static void gen_uclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a) +{ + tcg_gen_umax_i32(d, a, n); + tcg_gen_umin_i32(d, d, m); +} + +static void gen_uclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a) +{ + tcg_gen_umax_i64(d, a, n); + tcg_gen_umin_i64(d, d, m); +} + +static void gen_uclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n, + TCGv_vec m, TCGv_vec a) +{ + tcg_gen_umax_vec(vece, d, a, n); + tcg_gen_umin_vec(vece, d, d, m); +} + +static void gen_uclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m, + uint32_t a, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop[] =3D { + INDEX_op_umin_vec, INDEX_op_umax_vec, 0 + }; + static const GVecGen4 ops[4] =3D { + { .fniv =3D gen_uclamp_vec, + .fno =3D gen_helper_gvec_uclamp_b, + .opt_opc =3D vecop, + .vece =3D MO_8 }, + { .fniv =3D gen_uclamp_vec, + .fno =3D gen_helper_gvec_uclamp_h, + .opt_opc =3D vecop, + .vece =3D MO_16 }, + { .fni4 =3D gen_uclamp_i32, + .fniv =3D gen_uclamp_vec, + .fno =3D gen_helper_gvec_uclamp_s, + .opt_opc =3D vecop, + .vece =3D MO_32 }, + { .fni8 =3D gen_uclamp_i64, + .fniv =3D gen_uclamp_vec, + .fno =3D gen_helper_gvec_uclamp_d, + .opt_opc =3D vecop, + .vece =3D MO_64, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64 } + }; + tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]); +} + +TRANS_FEAT(UCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_uclamp, a) diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 9a9c034e36..f59d3b26ea 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -2690,3 +2690,27 @@ void HELPER(gvec_bfmlal_idx)(void *vd, void *vn, voi= d *vm, } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +#define DO_CLAMP(NAME, TYPE) \ +void HELPER(NAME)(void *d, void *n, void *m, void *a, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc); \ + for (i =3D 0; i < opr_sz; i +=3D sizeof(TYPE)) { = \ + TYPE aa =3D *(TYPE *)(a + i); \ + TYPE nn =3D *(TYPE *)(n + i); \ + TYPE mm =3D *(TYPE *)(m + i); \ + TYPE dd =3D MIN(MAX(aa, nn), mm); \ + *(TYPE *)(d + i) =3D dd; \ + } \ + clear_tail(d, opr_sz, simd_maxsz(desc)); \ +} + +DO_CLAMP(gvec_sclamp_b, int8_t) +DO_CLAMP(gvec_sclamp_h, int16_t) +DO_CLAMP(gvec_sclamp_s, int32_t) +DO_CLAMP(gvec_sclamp_d, int64_t) + +DO_CLAMP(gvec_uclamp_b, uint8_t) +DO_CLAMP(gvec_uclamp_h, uint16_t) +DO_CLAMP(gvec_uclamp_s, uint32_t) +DO_CLAMP(gvec_uclamp_d, uint64_t) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index d1e229fd6e..ad411b5790 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1695,3 +1695,8 @@ PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0= .... \ @psel esz=3D2 imm=3D%psel_imm_s PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ @psel esz=3D3 imm=3D%psel_imm_d + +### SVE clamp + +SCLAMP 01000100 .. 0 ..... 110000 ..... ..... @rda_rn_rm +UCLAMP 01000100 .. 0 ..... 110001 ..... ..... @rda_rn_rm --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.36.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:37:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xCRHyiBxfCdHSn9JLF03/2mnxPSf+jP5kgzcaj+4wgM=; b=N04GvOk4K5p0AnqkIX0Wj0j2pIcvfpejB8Rc6S3RpcwrjhQnEbeejrAnxu4RrPo1Dr lzqUdonhPpnmb7DTPjL9PP093FVHPpoMz0A2ssO1eptyOvbuhX2e7Zx1Xpajwe+o8rGq w//43SYKUhR+0JQXd1ivERrH5NxtiP1RNzz9WyXBV9/G/258j8kBHpH9EHUp6YVtJmZr PDy1DHsCVzyYTFxBuwrMJjMWjTYVZ1/9dwQX1LaVE0ovKX5UHn6pDMLmOrlV6SfLFEp0 Rlde28i3NsYB62+8Ozks30hrtI2yCxgeavAWb9wtdZhixdUOQI3CqUSrWhazf2d6jHRA pq/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xCRHyiBxfCdHSn9JLF03/2mnxPSf+jP5kgzcaj+4wgM=; b=5XcYXjOfyKjFZPGcBNDgrSqHO7XklKvWtKEDYcqpAMLulDG4dfhXAVAgTgYhXBoogm YHbTz1lebyolhaoLuvl+Cdo1PWuJzmrSZcjAuGmg8sQSVrTNpr7v5x63ei8yZDoJLFNl xcrpefur8YQqJdjCXr/cOiTXGYA90mKUDt2ZhqkPtDlmxkTM7lQNtOG1RscaJXy8SiRP dC0bGUow6ZhULkpSsed8Ied6YhQD3+QDRZqrbNC4Xv/aKhaD9yLx6K/rMwbYDhH8mps3 GgJM0UypipNoAOmMP11AabRY7b6Pp7boIhvK2qjTGX4CAK/g93lqusHSvTb6w90jwkUA W37Q== X-Gm-Message-State: AOAM533bCJQVFYdJ2YYoEF2NjFJayjNMLCFqCcJ7WtBa4nLtANPkp/Hb B8YxTArdcvzZl/w2ySR+SqLx6RGC8H48BQ== X-Google-Smtp-Source: ABdhPJyhTH1Ntm8K3Pvv+eJN4aSA3gndVIY9R9bsb5X6U9DdhK+jsJ63WRvCRGaspLxzCzitN3RKZQ== X-Received: by 2002:a17:903:2310:b0:167:5310:9f03 with SMTP id d16-20020a170903231000b0016753109f03mr21484018plh.48.1654634220842; Tue, 07 Jun 2022 13:37:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 57/71] target/arm: Reset streaming sve state on exception boundaries Date: Tue, 7 Jun 2022 13:32:52 -0700 Message-Id: <20220607203306.657998-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654638754532100001 Content-Type: text/plain; charset="utf-8" We can handle both exception entry and exception return by hooking into aarch64_sve_change_el. Signed-off-by: Richard Henderson --- target/arm/helper.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3e0326af58..205fbbbe42 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -14276,6 +14276,19 @@ void aarch64_sve_change_el(CPUARMState *env, int o= ld_el, return; } =20 + old_a64 =3D old_el ? arm_el_is_aa64(env, old_el) : el0_a64; + new_a64 =3D new_el ? arm_el_is_aa64(env, new_el) : el0_a64; + + /* + * Both AArch64.TakeException and AArch64.ExceptionReturn + * invoke ResetSVEState when taking an exception from, or + * returning to, AArch32 state when PSTATE.SM is enabled. + */ + if (old_a64 !=3D new_a64 && FIELD_EX64(env->svcr, SVCR, SM)) { + arm_reset_sve_state(env); + return; + } + /* * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped * at ELx, or not available because the EL is in AArch32 state, then @@ -14288,10 +14301,8 @@ void aarch64_sve_change_el(CPUARMState *env, int o= ld_el, * we already have the correct register contents when encountering the * vq0->vq0 transition between EL0->EL1. */ - old_a64 =3D old_el ? arm_el_is_aa64(env, old_el) : el0_a64; old_len =3D (old_a64 && !sve_exception_el(env, old_el) ? sve_vqm1_for_el(env, old_el) : 0); - new_a64 =3D new_el ? arm_el_is_aa64(env, new_el) : el0_a64; new_len =3D (new_a64 && !sve_exception_el(env, new_el) ? sve_vqm1_for_el(env, new_el) : 0); =20 --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654637607; cv=none; d=zohomail.com; s=zohoarc; b=eUt3gMlEcxCWXxS1ZmL6dp+wKpgYYMZJ9ccw8ZAsIYzf8WEpOw7egkDzhPXXwTRuVBJlRFwS5L9np1HbHpBY9qjLlSaYvS3q7EQ2iePVuP9z6+F0g33JpO21wli8Az0ybdZfvAyJ91pSdQTzhqdpfJhw01fxw2u+xGaOpl70cHY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654637607; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=82yuKxX8pMTqpPKtHE5QelO5OO41QYfrwZUlFAo4P7w=; b=I1qTX1Y48AL8R3XkyHq6TD9Ied401/gnq6wkA5BZFmuPpidjSF25A0Yae8SJkHUX4NGRycMtALiCfGRxO/wlLCALPZqt8EB0j+ld73qozW4LTOYzoP1aWQc8itvaKk3KOLWHXORHp2ZUpzn6C1GMCOuUKqKTg8VRt9wSHuX7hmA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165463760789412.921114952258563; Tue, 7 Jun 2022 14:33:27 -0700 (PDT) Received: from localhost ([::1]:51322 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygpK-0002Yi-Ch for importer@patchew.org; Tue, 07 Jun 2022 17:33:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36172) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfwr-00074V-MH for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:09 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:44681) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfwk-0008FN-Fe for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:09 -0400 Received: by mail-pl1-x62c.google.com with SMTP id h1so15783115plf.11 for ; Tue, 07 Jun 2022 13:37:02 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.37.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:37:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=82yuKxX8pMTqpPKtHE5QelO5OO41QYfrwZUlFAo4P7w=; b=BreawBXY9enZFIP3Rs46FVFvH6xUeZTQmqf1OvRZ/7IUZGyYuRSAiybGHJGMfxBl9Z GpApFx6nU/hms+mSfe5x4iSw273YUu5YvyQonzZCClPphSnbHX/plOCqjm3c87HqEmac KUipLn7hBLOwucGwWDkwXlq6GMgJeb9/1nKGwV3wuzkEFjtV/uJ48X+LA/znU8r6lOxb OZfn7d5Ky/earCyKN9bzE8mPsw/6IgV0nnvBw3hSCQdZ13qTYJymNJW9PQhLbnluq1oS q4opxK7DSiobmya5pSi9Xo1/HFU/XKyLcsQhi3UPTOJZ0wohaVQ9JY1X9BvjKDeoZXSk 01MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=82yuKxX8pMTqpPKtHE5QelO5OO41QYfrwZUlFAo4P7w=; b=vHDFIrx5vMG04R2ik7T0Ie48Lht9T/EW63xyqZkLgXFqyr0Orp1YgfsA1jbkuNvLJI DTRcMnetlfFAI2WdtWKyJALWpgINxIJMfFs8Tx1hIMfwu8fvl9OzynGL7J7tHcx1AZ6V 4dqJQSoWuxoB+8UoLq4g2dyXklmIJBFI04iifjC1FkS/D4OrxFJcVJQ/TtJIprQA82Qr FHz1iPdF2V3HjeFwSL0KxqSmilimTxQ+RURkuW8gbVA7JS2KfTYS4KLacUoI+wfcQhrj SrOFtnUmn76e8YM12tBLkPFAv1rAQI4k7KnJJkRxvuXWhfT48V/JX/lboOJ+hF3b9lVm +iIw== X-Gm-Message-State: AOAM533R/W3h+lD20s3PfQsbqFgj2ACV46DSZ+4PCM8YmZSB4ZC0hnnJ ugrlDeP8oKs/EH1Q5jCfMDV/mzcDGgs2wQ== X-Google-Smtp-Source: ABdhPJzG9H51z15HpuzVMNiQ5RsKUiJ3WHQJdb2LGtUfO6rcOelwpdKqi/WgoWFrH9qWS34EU1meOA== X-Received: by 2002:a17:903:2cf:b0:151:a932:f1f0 with SMTP id s15-20020a17090302cf00b00151a932f1f0mr31356879plk.130.1654634221623; Tue, 07 Jun 2022 13:37:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 58/71] target/arm: Enable SME for -cpu max Date: Tue, 7 Jun 2022 13:32:53 -0700 Message-Id: <20220607203306.657998-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654637609050100001 Content-Type: text/plain; charset="utf-8" Note that SME remains effectively disabled for user-only, because we do not yet set CPACR_EL1.SMEN. This needs to wait until the kernel ABI is implemented. Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 11 +++++++++++ docs/system/arm/emulation.rst | 4 ++++ 2 files changed, 15 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index aaf2c243d6..d77522e278 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1017,6 +1017,7 @@ static void aarch64_max_initfn(Object *obj) * we do for EL2 with the virtualization=3Don property. */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr1 =3D t; =20 @@ -1067,6 +1068,16 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 + t =3D cpu->isar.id_aa64smfr0; + t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ + t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ + cpu->isar.id_aa64smfr0 =3D t; + /* Replicate the same data to the 32-bit id registers. */ aa32_max_features(cpu); =20 diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 49cc3e8340..834289cb8e 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -63,6 +63,10 @@ the following architecture extensions: - FEAT_SHA512 (Advanced SIMD SHA512 instructions) - FEAT_SM3 (Advanced SIMD SM3 instructions) - FEAT_SM4 (Advanced SIMD SM4 instructions) +- FEAT_SME (Scalable Matrix Extension) +- FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode) +- FEAT_SME_F64F64 (Double-precision floating-point outer product instructi= ons) +- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instruc= tions) - FEAT_SPECRES (Speculation restriction instructions) - FEAT_SSBS (Speculative Store Bypass Safe) - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain) --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654638396; cv=none; d=zohomail.com; s=zohoarc; b=M/JT3Z23nXfMKyQ+/uShM5/ZVK81pd8OvWREWtRJglsHmrBmJnz3eioCMNPqd4pV5GJtMRmWm264Db1/4lS817CzRzYHmf+yQWkge+398pibOCRteCRgBdhJZ3bvDYYxjYfYvdIwCAI8dbboMjl2husbHBom5ZVofbkzZgHXXL4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654638396; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=h8NNZqBa/oaHcQdJifd9wVEds8arqW1sbQgko9Vs+gQ=; b=EjNcfh1u9Smmdg8V5XLbdzcs5SQnHBGEMRrna0uWAwoTJYd833cW3/2lPcNQkGQkQTN+Avz7Emo0yHKL+FGAsQkZNK6ipurBWjrAUlh2Lo/4oKlzc6oaeCJj5r7e/H6dOXHAEfdJ9YHm7B2vy42hYr3pumacu7EpTYZfhhbN6vQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165463839676465.74193424479404; Tue, 7 Jun 2022 14:46:36 -0700 (PDT) Received: from localhost ([::1]:54166 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyh23-0006R6-O7 for importer@patchew.org; Tue, 07 Jun 2022 17:46:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36186) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfwu-00076E-49 for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:12 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:35738) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfwl-0008Jx-NI for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:09 -0400 Received: by mail-pl1-x62b.google.com with SMTP id o6so10727746plg.2 for ; Tue, 07 Jun 2022 13:37:03 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654638397891100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- linux-user/aarch64/target_cpu.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cp= u.h index 97a477bd3e..f90359faf2 100644 --- a/linux-user/aarch64/target_cpu.h +++ b/linux-user/aarch64/target_cpu.h @@ -34,10 +34,13 @@ static inline void cpu_clone_regs_parent(CPUARMState *e= nv, unsigned flags) =20 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) { - /* Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is + /* + * Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is * different from AArch32 Linux, which uses TPIDRRO. */ env->cp15.tpidr_el[0] =3D newtls; + /* TPIDR2_EL0 is cleared with CLONE_SETTLS. */ + env->cp15.tpidr2_el0 =3D 0; } =20 static inline abi_ulong get_sp_from_cpustate(CPUARMState *state) --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654639346; cv=none; d=zohomail.com; s=zohoarc; b=g2+EMp66YcVjiHXUJpyuJPEcFmDScWMBLX/JYnaKKt6ED7vazoXEYfjvdi4MuBdr3WR5FzK9HisxMa8J23JhyhRH3y6EswIEcyXqY99Urr7v0FZycaxtNwxGfgdU/5RizFQXdbDOiNBPtVmDch8NtLYc2wc5rZ4+9YOWp7UzWvI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654639347496100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 3b273f6299..4af6996d57 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -89,6 +89,15 @@ void cpu_loop(CPUARMState *env) =20 switch (trapnr) { case EXCP_SWI: + /* + * On syscall, PSTATE.ZA is preserved, along with the ZA matri= x. + * PSTATE.SM is cleared, per SMSTOP, which does ResetSVEState. + */ + if (FIELD_EX64(env->svcr, SVCR, SM)) { + env->svcr =3D FIELD_DP64(env->svcr, SVCR, SM, 0); + arm_rebuild_hflags(env); + arm_reset_sve_state(env); + } ret =3D do_syscall(env, env->xregs[8], env->xregs[0], --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654638674; cv=none; d=zohomail.com; s=zohoarc; b=nsaQOz0BG/eofadoHhHkSfWNKb53tJPq9T8o0Xg6RKzdwlrH6JlF/iDvKjeKjmlaCMdAMzC4xjzrjaOIwvY2F0/Yp5i/sjSHY243Y86lSx89LvHIIVmUecqQH6a+GgO2NrXIxlLscWCMlaugJxc8PP7B5HhmSnOa3hAc7XgKC5U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654638674; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FjmC/46ARakxFpcFGMLJHjfrHdRZ+a4Hi4clf4uxgwU=; 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([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.37.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:37:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FjmC/46ARakxFpcFGMLJHjfrHdRZ+a4Hi4clf4uxgwU=; b=ZAjjgadE2Bg7RCCjuuzOFXghuaZuR+KAvojV219qSd6n63WjYs4xH4LEiBjFWYO9pH 3Ue/N/ygU0PdOwhYoXQ5lE3uZD9zCPWbfDZ2rkbRO0xJmbzcRgzPgRekEhHjNGMLAFDd oZBrNsaFpX3oCRjDVl7Zw/rF3WUF6dnD3I6VEHD4itUHpu4NrlTm/QKNNKltBk4pJ61C z5DqwJ9kr1NcJ1sK1yt6WkMd+ofjYFuW8BlTwzCCgAOFFZBKNJtcd2kHsy+XT4zDqQv5 f0PQfkbrTdjuCe10SNL58DRJmyg2W+mjnZEze8Cfl624d84oOz0NmswrfDg/Nie7aNcY grIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FjmC/46ARakxFpcFGMLJHjfrHdRZ+a4Hi4clf4uxgwU=; b=ywteUHb68rQQDX26kjIyuxmJPUP2147TeB4PG2qv54NHUZXLkN6sjm2+8FfWNBRYql isxdAXeFR5DNqotKFuvuADvJILcMa/Nn+2gEb7Putn8I4yJ0oWguwxL653c8j0lsCjQ4 kyb4s6a1fidbXVOaeqX5LoJezLAIPtJExxDL8gxqMzLVxL+e+2MeeuGnE0pGyLZw5aeC wzGvoHaAAfJC3dbASwNAydbV69Ql11+Aap4tq/A6SGQDXIsCHX9wTMfWJqvSR8ZfJZxP RZQXJ/tlArjz+lKx0Zz/IKTR/QpbNpCC0e0t4SeqD6Yd4yXFOhQAsTDIQ1q4VUpvm2DF lXEg== X-Gm-Message-State: AOAM531Qw8U4eWCZuNcOL4SkFiBKVeUKj/JTsuJD5yqVRG5Nks2IrkXd n2hwX5p4levsf4DAWC5vUFIc1XrYLWUttw== X-Google-Smtp-Source: ABdhPJxznaQ36xxPSw6xOrLAfNDqyNd16M8wD1SFiVsPqbzbdJz6PclkH1jbPKsXhvlmIh8FV6UfXA== X-Received: by 2002:a17:902:7b8f:b0:162:467:db7c with SMTP id w15-20020a1709027b8f00b001620467db7cmr29671017pll.140.1654634224007; Tue, 07 Jun 2022 13:37:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 61/71] linux-user/aarch64: Add SM bit to SVE signal context Date: Tue, 7 Jun 2022 13:32:56 -0700 Message-Id: <20220607203306.657998-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654638676098100001 Content-Type: text/plain; charset="utf-8" Make sure to zero the currently reserved fields. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 7da0e36c6d..3cef2f44cf 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -78,7 +78,8 @@ struct target_extra_context { struct target_sve_context { struct target_aarch64_ctx head; uint16_t vl; - uint16_t reserved[3]; + uint16_t flags; + uint16_t reserved[2]; /* The actual SVE data immediately follows. It is laid out * according to TARGET_SVE_SIG_{Z,P}REG_OFFSET, based off of * the original struct pointer. @@ -101,6 +102,8 @@ struct target_sve_context { #define TARGET_SVE_SIG_CONTEXT_SIZE(VQ) \ (TARGET_SVE_SIG_PREG_OFFSET(VQ, 17)) =20 +#define TARGET_SVE_SIG_FLAG_SM 1 + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -177,9 +180,13 @@ static void target_setup_sve_record(struct target_sve_= context *sve, { int i, j; =20 + memset(sve, 0, sizeof(*sve)); __put_user(TARGET_SVE_MAGIC, &sve->head.magic); __put_user(size, &sve->head.size); __put_user(vq * TARGET_SVE_VQ_BYTES, &sve->vl); + if (FIELD_EX64(env->svcr, SVCR, SM)) { + __put_user(TARGET_SVE_SIG_FLAG_SM, &sve->flags); + } =20 /* Note that SVE regs are stored as a byte stream, with each byte elem= ent * at a subsequent address. This corresponds to a little-endian store --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654638154; cv=none; d=zohomail.com; s=zohoarc; b=d/mL27A6kM9ni9f5t9JDTHe6hkIV3OIpnLfoPT0gHqRTV96+SVPCKYycWPOfC2sRBRE07zLZ0fyku7eXSSCt+EZIPFMF/J07XjfaLqqtmtzr4RJNeBP8dog5IHgA+Nm2FW5TLtMKRl01b/u/aZLhAnNr8nBoV8U1ISHCPdUfV/o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654638154; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VPMml4Tfq67+y3oqJMSmdBs/iUTANF8r3DziFKMfYRY=; b=BUMvuA0M3gSPk3Wt4oH26eZdgyT2TCxBpjLDws7YkEElYzkF4wUjjc1OyBV6AFWM1JBHCxVtjdedC9MALyVr/x1wW1FXo+IB14VzyRtfKUT4Q2LCAszrH49XYHR4/afH8aBLj3rkXaWH64mJCtNI6ZFgH3M1DnjJW5jx9Ca7Us4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654638154913122.57060328642547; Tue, 7 Jun 2022 14:42:34 -0700 (PDT) Received: from localhost ([::1]:44782 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygy9-00008L-Tt for importer@patchew.org; Tue, 07 Jun 2022 17:42:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36328) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfww-0007Ij-AY for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:14 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:53061) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfwo-0008LT-LT for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:14 -0400 Received: by mail-pj1-x1034.google.com with SMTP id gd1so16677941pjb.2 for ; Tue, 07 Jun 2022 13:37:06 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.37.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:37:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VPMml4Tfq67+y3oqJMSmdBs/iUTANF8r3DziFKMfYRY=; b=nfz1MpKCsMT7Ha55I8sMlCCDjs8bWbhEPVNCx5AgdWzPszcMGHln+rAdK7Lzw3/qRQ Nnor7vO7dFiwwbly/9IzCuo+jOZkV92gAcq+lIT4oLr0P867whnsS9qHAjVf6hbtap+R TVXQO7HqMN5gJdaSUT0oYHqj3GnGOz1FuPKFVsH6k+GxkolqXHjh8ECjj40fAZnXdNLC K8QT150+ygfbjw/TkzRGsQ3Nz+tSpWnpiPcWf9NakKVriOkliKfXR7FhYY5welnS6bl2 rvhtnQKjf9Om+paGqG8hkJb592N2UBNIFi9tM8/S3X+VIT3lKAqYe5mmWozzayVQR5Y5 2+WA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VPMml4Tfq67+y3oqJMSmdBs/iUTANF8r3DziFKMfYRY=; b=KWVHjCw2/S+9pbWmnE7gIP/DVGZR6T12xECoco9DJm+piIBePiOyZQeloGnCPUQJKI SFYIq6rFmLmeH8rPx+m65POc+OcCJh/q6wbLdycnna8Kl+paSMt2Z61qiyxOFvuYBU1J m7+5rk8JHALr5Y/0KNFXvAJ3qnhrRWzWO+CsGFMjS+HXVYWK/zbHYFkITGn5dG15b+dm Uz7LzymExkwwRxGq2y4SkiuzN85vxgiCO46t7w3j4oz0fXDPa3rKixEhDAmR7ZFzJZDk AxS5n8Kq0a8ZqauXwXEvZhH5sXjdqelBYiYcMvtUMqjKx+yrocqijxMCztpahLtsxihR F7DQ== X-Gm-Message-State: AOAM531UMvyfeWnMptDfD+y0nMjZRb3EdKn4fVPJAi9E0Lu0IKj8reAU Ji+1Hphq09xf/d/TiV52WRRYvqKHEExMUw== X-Google-Smtp-Source: ABdhPJwliS/9Of3poseG4MGNaKlX8AFDdoXsxLQSwZx+NILAxL8TnKyn41CdcfmC2RP8JkUm68GH2w== X-Received: by 2002:a17:902:d0cb:b0:167:8f4d:92e6 with SMTP id n11-20020a170902d0cb00b001678f4d92e6mr6489076pln.83.1654634225313; Tue, 07 Jun 2022 13:37:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 62/71] linux-user/aarch64: Tidy target_restore_sigframe error return Date: Tue, 7 Jun 2022 13:32:57 -0700 Message-Id: <20220607203306.657998-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654638156529100001 Content-Type: text/plain; charset="utf-8" Fold the return value setting into the goto, so each point of failure need not do both. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 3cef2f44cf..8b352abb97 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -287,7 +287,6 @@ static int target_restore_sigframe(CPUARMState *env, struct target_sve_context *sve =3D NULL; uint64_t extra_datap =3D 0; bool used_extra =3D false; - bool err =3D false; int vq =3D 0, sve_size =3D 0; =20 target_restore_general_frame(env, sf); @@ -301,8 +300,7 @@ static int target_restore_sigframe(CPUARMState *env, switch (magic) { case 0: if (size !=3D 0) { - err =3D true; - goto exit; + goto err; } if (used_extra) { ctx =3D NULL; @@ -314,8 +312,7 @@ static int target_restore_sigframe(CPUARMState *env, =20 case TARGET_FPSIMD_MAGIC: if (fpsimd || size !=3D sizeof(struct target_fpsimd_context)) { - err =3D true; - goto exit; + goto err; } fpsimd =3D (struct target_fpsimd_context *)ctx; break; @@ -329,13 +326,11 @@ static int target_restore_sigframe(CPUARMState *env, break; } } - err =3D true; - goto exit; + goto err; =20 case TARGET_EXTRA_MAGIC: if (extra || size !=3D sizeof(struct target_extra_context)) { - err =3D true; - goto exit; + goto err; } __get_user(extra_datap, &((struct target_extra_context *)ctx)->datap); @@ -348,8 +343,7 @@ static int target_restore_sigframe(CPUARMState *env, /* Unknown record -- we certainly didn't generate it. * Did we in fact get out of sync? */ - err =3D true; - goto exit; + goto err; } ctx =3D (void *)ctx + size; } @@ -358,17 +352,19 @@ static int target_restore_sigframe(CPUARMState *env, if (fpsimd) { target_restore_fpsimd_record(env, fpsimd); } else { - err =3D true; + goto err; } =20 /* SVE data, if present, overwrites FPSIMD data. */ if (sve) { target_restore_sve_record(env, sve, vq); } - - exit: unlock_user(extra, extra_datap, 0); - return err; + return 0; + + err: + unlock_user(extra, extra_datap, 0); + return 1; } =20 static abi_ulong get_sigframe(struct target_sigaction *ka, --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654638389; cv=none; d=zohomail.com; s=zohoarc; b=KqkjOXyGFdk0gsnyic4mp9OuL6CuzVqUpdao9zEpK4x4FzgVB+cI9u4yK1xmP87/EiBaiVOEbRRGOFB5Ir4oz8yyW1krSR/CMGuEybX1Al1e3Z9Fzcid+9+br0Q2p6UgsJkFXM8wj4QaJhJjoUHUiMWG0WHhd8VeEQXxiUQUI2o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654638389; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Khgw4zesO+K18d95Nf0OQk5x631DSo+q5LDKVsiqTz0=; b=EHFkfOA3NN/NTgE0+lv1fVphDVtaSRjzDBHZBZCpeLYU1QpieO3WgIWKiVWncJaZlcuSr/5MKOiJw1ORX0MB0/tU0uvf9thzCjSbt8++BJVipDD+DHIbb5ugkxrAAYfM5ZP1nevGWkXO+23nIv0FYVhh3ojmrLyZCgXACwwGTqA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654638389115614.1310476365159; Tue, 7 Jun 2022 14:46:29 -0700 (PDT) Received: from localhost ([::1]:53478 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyh1w-0005we-4V for importer@patchew.org; Tue, 07 Jun 2022 17:46:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36430) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfwy-0007SV-I7 for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:16 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:43954) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfwp-0008Ln-TP for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:16 -0400 Received: by mail-pg1-x529.google.com with SMTP id s135so1321361pgs.10 for ; Tue, 07 Jun 2022 13:37:06 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.37.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:37:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Khgw4zesO+K18d95Nf0OQk5x631DSo+q5LDKVsiqTz0=; b=N9gZLZL0XzwCu+XWXFvYMP66wJtfVAkHIA8iEBlADwAqwOsUqlWMc/E8i83Hi1uirJ wW8q9Mt4vHtZhyMZXTCXLJzAJKyordQwIIefMScAK1qusuP0Urk71IT7KNQKpJ5OjJNA 9MAcV8TMI0cvoFuqQO59zUzmJr1y0KLqjZSIzWmrJBiFgoPfFLw73zKPalDCqW2MZXi5 wjjkYRwvURAaoiLuq8+GTHC5In1ye4r6OI6mhoNSMqv8TG1dUyIAx4U7zIJc70FpB0up RLJJJPO21n1V82aCQ7RP5g8RBofeQVrsMW6EpcZ5iHTfSeHirJ0WopZYC6VrlbHWKPKx xnFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Khgw4zesO+K18d95Nf0OQk5x631DSo+q5LDKVsiqTz0=; b=B3X2vrdSFtyVdXZLx5iq8C4mY25yW4PbCMmRRhRS6/Q3PBVr+5oZ9OT/avtmGZ3sTZ Hp7yV/y74Hv+4eCe1uJCOX78rv7gvYMvXfmvGE4CgVVcpw87zcjs/jAtpaplhHtZD1pf fWrkFd6t3QKwN2t6vPo3vY1RbH6BV/4wg+loqjO0KgnAegIt/D5CHRT91dh+UUNw03BF tWsmdFXcOs2wIknyOfkkPk6jZnndk1oD04X2RlYa3CHyqSEmW4A5EnQBUe+m6COlewKg hgTDJpcKhXckWY+Zu4zBAEXE9CzDtXxD0BFqGU+nDpPiQJ7KVfdPYax5LsOI+L3CrNMV Z5BA== X-Gm-Message-State: AOAM531ztl5SFPYPKtJYVwA6dCeW+F+jp39s931kSUAENQ0ss7wEGO52 YW/+tm6MunBEX0tFmARpQQ+h+5Oqg3w9Jw== X-Google-Smtp-Source: ABdhPJzfgWi/dB/dlLJgpKzbeEhPUMpb4l5Lo0mAoRsL5E/OB2hD81t+O8ImkoOo6pqJumW6chwdng== X-Received: by 2002:a63:524a:0:b0:3fc:7f18:685d with SMTP id s10-20020a63524a000000b003fc7f18685dmr27469956pgl.387.1654634226114; Tue, 07 Jun 2022 13:37:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 63/71] linux-user/aarch64: Do not allow duplicate or short sve records Date: Tue, 7 Jun 2022 13:32:58 -0700 Message-Id: <20220607203306.657998-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654638389744100001 Content-Type: text/plain; charset="utf-8" In parse_user_sigframe, the kernel rejects duplicate sve records, or records that are smaller than the header. We were silently allowing these cases to pass, dropping the record. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 8b352abb97..8fbe98d72f 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -318,10 +318,13 @@ static int target_restore_sigframe(CPUARMState *env, break; =20 case TARGET_SVE_MAGIC: + if (sve || size < sizeof(struct target_sve_context)) { + goto err; + } if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { vq =3D sve_vq(env); sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq)= , 16); - if (!sve && size =3D=3D sve_size) { + if (size =3D=3D sve_size) { sve =3D (struct target_sve_context *)ctx; break; } --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654638962; cv=none; d=zohomail.com; s=zohoarc; b=b99SezhLw+kBme4/MipBRy/N2JWWOwH9NVcFF24buK3jGI8a1JJ6KDURkEqhhpQuRBo0B5NJmm83u+DNceRfuutJEDko5iXggD81TfPMluEFZu2siU8G2vxWZZy0/0wg3PCz5KVilngh2y25PRNRVtWkLvhpbl5g/cXqrgzkhX4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654638962; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jX6jS4dtrhW1QeYx18wps/PVKx5vjATldMSj/oHyJlI=; b=ME4KVFk098Mx9QD6XUvKZEB1KVOeVaaZErRoIEZwzXl+jk4mmHrBJ3PO3L6EzdSYahPBtXNortguK2eIPV+jdadOPHfp1fyOM0p2sjgE1qWfBEDAE/nRZ6AraFSSoXTNdQ6Vzvt/hcxjQ39deNk84SLeor1OgHBLZmKsF/HzLRs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654638961997110.64016306281644; Tue, 7 Jun 2022 14:56:01 -0700 (PDT) Received: from localhost ([::1]:45304 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyhBA-00038Z-KO for importer@patchew.org; Tue, 07 Jun 2022 17:56:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36404) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfwx-0007Q5-VU for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:15 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:43879) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfwp-0008EG-KU for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:15 -0400 Received: by mail-pj1-x102c.google.com with SMTP id l7-20020a17090aaa8700b001dd1a5b9965so16437566pjq.2 for ; Tue, 07 Jun 2022 13:37:07 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654638963641100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 8fbe98d72f..9ff79da4be 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -340,6 +340,9 @@ static int target_restore_sigframe(CPUARMState *env, __get_user(extra_size, &((struct target_extra_context *)ctx)->size); extra =3D lock_user(VERIFY_READ, extra_datap, extra_size, 0); + if (!extra) { + return 1; + } break; =20 default: --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654637947; cv=none; d=zohomail.com; s=zohoarc; b=eK3grm3Y6YT5ntSMAiWUqsQ7BVVhPAMjyfz5vgcGJ09y48VHdYFA3hN6yFs/cudvEAWD9y6znrUrkw0xdDzElWmZSCVonxtmH4eIO3hsQQAg4w6AhuOwFuk2+gnfZJFIDJkqkOv0opWtX+eYrH5nbicjsjEab8xpzhabxxCX17Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654637947; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pyZCOGTvs2PmDR4WHKguGZ+NHJT+1M/Dn/XfXNcerpI=; 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([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.37.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:37:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pyZCOGTvs2PmDR4WHKguGZ+NHJT+1M/Dn/XfXNcerpI=; b=q8spuEpNSiC5KQFE3GOsN7tYvcrEC/bl2kgFDlo/ElW12e4k7pylrE2D9twSnFWeYU X1tzK2EFh75lJs5PTpwVG7eCl9oCDxPnKZz9ZeMlkcv4OrEa8EZanBxWRj7OMNlMHlIX cza+ZHx6QaKRu/dkwVsUPXLL+ZdDCglXRwwx4SP5UHrTCuUe4MBFAM3OgaHETTVqwsWj 9+hZJneML3V8njnfVxwjuhAPxtOfy4pzMxoY+UE0BiIpbDuWILEaUUPiRPa0lXOA4qk/ SwDnU1swwLPtnf6XBoo/oLl0HGARQfCiwRMQnqKL/Ox9DYFprPOvNs1tAQECVInmQKu6 j7Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pyZCOGTvs2PmDR4WHKguGZ+NHJT+1M/Dn/XfXNcerpI=; b=WMqzDeM/z6iF/W/vYu0t/HvmARhYa1ldQlI98NKGE73TeNvZdCXyRG0E3yYlnM1h0W QMVcd9eYKzUgmuesGiEu1YjGwSgdEw+I3Ta66/CXNyufR53FnrpiNSCuxqJxmj+xTkCI yIrq+01TMB99IN+IMqzE9MTNj4Wx9fA0lPXuFMfRm5mU07lnLxM0zvARhUUMfUkyHEB9 XY4Q8Xtys/W7m2p1EqKJZVsol8J1XXYh9POHJXrzXlfA+/RfPvLbnYtf2Gt3k0XFC5SP vjrORzjEcPRSsgmbQCphetLujfyHWxxe5cddhyXTVNCAk2TNiG5jfDrLacXxu6JkcHkr Z9kw== X-Gm-Message-State: AOAM5336eqop6HarpCMBhtEkDOCjNXStyQlWA48SVdIO0carElNY6Fh2 m6maPJioB4EotEtAiwlFvlUmXxMICazIlg== X-Google-Smtp-Source: ABdhPJx6guHcnZFnR65GhHV2GLzF9iJNHQhw1yo583NNF7Tw+R37BvUL4P7cpkdTCiLRhDNI+0nwJg== X-Received: by 2002:a63:f915:0:b0:3fd:876b:808e with SMTP id h21-20020a63f915000000b003fd876b808emr14116646pgi.403.1654634227784; Tue, 07 Jun 2022 13:37:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 65/71] linux-user/aarch64: Move sve record checks into restore Date: Tue, 7 Jun 2022 13:33:00 -0700 Message-Id: <20220607203306.657998-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654637949593100001 Content-Type: text/plain; charset="utf-8" Move the checks out of the parsing loop and into the restore function. This more closely mirrors the code structure in the kernel, and is slightly clearer. Reject rather than silently skip incorrect VL and SVE record sizes. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 51 +++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 16 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 9ff79da4be..22d0b8b4ec 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -250,12 +250,36 @@ static void target_restore_fpsimd_record(CPUARMState = *env, } } =20 -static void target_restore_sve_record(CPUARMState *env, - struct target_sve_context *sve, int = vq) +static bool target_restore_sve_record(CPUARMState *env, + struct target_sve_context *sve, + int size) { - int i, j; + int i, j, vl, vq; =20 - /* Note that SVE regs are stored as a byte stream, with each byte elem= ent + if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) { + return false; + } + + __get_user(vl, &sve->vl); + vq =3D sve_vq(env); + + /* Reject mismatched VL. */ + if (vl !=3D vq * TARGET_SVE_VQ_BYTES) { + return false; + } + + /* Accept empty record -- used to clear PSTATE.SM. */ + if (size <=3D sizeof(*sve)) { + return true; + } + + /* Reject non-empty but incomplete record. */ + if (size < TARGET_SVE_SIG_CONTEXT_SIZE(vq)) { + return false; + } + + /* + * Note that SVE regs are stored as a byte stream, with each byte elem= ent * at a subsequent address. This corresponds to a little-endian load * of our 64-bit hunks. */ @@ -277,6 +301,7 @@ static void target_restore_sve_record(CPUARMState *env, } } } + return true; } =20 static int target_restore_sigframe(CPUARMState *env, @@ -287,7 +312,7 @@ static int target_restore_sigframe(CPUARMState *env, struct target_sve_context *sve =3D NULL; uint64_t extra_datap =3D 0; bool used_extra =3D false; - int vq =3D 0, sve_size =3D 0; + int sve_size =3D 0; =20 target_restore_general_frame(env, sf); =20 @@ -321,15 +346,9 @@ static int target_restore_sigframe(CPUARMState *env, if (sve || size < sizeof(struct target_sve_context)) { goto err; } - if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { - vq =3D sve_vq(env); - sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq)= , 16); - if (size =3D=3D sve_size) { - sve =3D (struct target_sve_context *)ctx; - break; - } - } - goto err; + sve =3D (struct target_sve_context *)ctx; + sve_size =3D size; + break; =20 case TARGET_EXTRA_MAGIC: if (extra || size !=3D sizeof(struct target_extra_context)) { @@ -362,8 +381,8 @@ static int target_restore_sigframe(CPUARMState *env, } =20 /* SVE data, if present, overwrites FPSIMD data. */ - if (sve) { - target_restore_sve_record(env, sve, vq); + if (sve && !target_restore_sve_record(env, sve, sve_size)) { + goto err; } unlock_user(extra, extra_datap, 0); return 0; --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654639354; cv=none; d=zohomail.com; s=zohoarc; b=NE65AysJ2qpDNJk91NZ3cvGzttcyRSgudvdxZSsL9ZPeAfUFuoDq00Efi2ZwK7ghPViyoULNbobJdMYORyWEy51ciefN/6yMDK8uOgUJK/heI/fLIJt0LhgLFrICKanO7cHqx9gG86+c3fPSZgbfmzHfsinX3fteyrtoEAIGb6c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654639354; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pHB4ROsLewdQ7HrrSMrZ3uGIT5+drN7tItK3h279f+o=; b=m/fSajD8NQGp2rkDtyULjtaglGXnxewIb4QXsoika6w3a/IMVSsx3UVKdpKvo1R5YQp24L3t7M4gbkg7nBI+SCd0Fe08RSmqk1gZ3irOi3/fTeHQ7o33hZ7z17egRhNRE+NOil/GkHn0AsWiE18bIdINs+x5McUAk+nowZkN1Xc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165463935405393.7444910262949; Tue, 7 Jun 2022 15:02:34 -0700 (PDT) Received: from localhost ([::1]:57048 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyhHU-0003B8-Cy for importer@patchew.org; Tue, 07 Jun 2022 18:02:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36518) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfx0-0007bq-Vs for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:19 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:33271) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfwr-0008GF-LD for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:18 -0400 Received: by mail-pj1-x102a.google.com with SMTP id hv24-20020a17090ae41800b001e33eebdb5dso14600264pjb.0 for ; Tue, 07 Jun 2022 13:37:09 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.37.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:37:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pHB4ROsLewdQ7HrrSMrZ3uGIT5+drN7tItK3h279f+o=; b=N/hEr0BhMpfEwwFDM1JdGf3/K3FQ6IUdnPRHv69r8jqeCw4OnUehmHSIWGtWoNkOCX atz6tauPsJ2hcvCBFpxbGhBL84VeV9IgRvtgvWL9hvS8p4dcDP+GqS9jUclaiwSsPiiF wCgw53gFm/UZsnWaBNVhRWYqNjRhP8UeP8vHEVPlhhifzSOYYr87ksKk05JHk3dq8ciL PfN85IpzBi9Uq96/dwoDFVkkSmvGekQW8f+cgryq0mvefZXP+md7mv3cjJBeU0y/E6Qo F6i3J49GJmYNO9Xb3tQ8QqElcVFUBv7q/t1iGlRAtVrewrQUuvjxqet1CVy9loH8hwFh xQGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pHB4ROsLewdQ7HrrSMrZ3uGIT5+drN7tItK3h279f+o=; b=C00fPQGJPryxcFxp9g+VJJWBgwohIzoHkh9tJQRxYWyQJJaHDp7TQCbntd1QuZExnW 4/Mp3ih0bd7pIGrWx2P+n2IVbUXVkIKFQz3HYCpjlLteTTD5LH3uWF2Qfv+89YAjhDoZ Qmpj5vj88P49A8pDJWw0KjNwbmsB+l7HpgmQ+QLdH11jem5Si8GC93a9A6nvMYTthz9W 96K2HGyDe07dfBNGeyLxDV9s6rreFr5n8XfI1j8y6FGRK2SHe+i8QhwmNq7TjJED2oun 4ZBogMVZO+EIQJFsq9Uv8sPvsH72mCXzvp/n0KXUyNapxgAiE43AZBGr2IDCdgCj+C+c bcLg== X-Gm-Message-State: AOAM530pM8B2qBGvKTS8S1Bdtx00OP1hDkTOgI9N3ylylfTV4T8Bcu9m SkkCVUWImfJ/CdXZWGPZx8u1lm4uFc7zZA== X-Google-Smtp-Source: ABdhPJxBPEKJzBRgwZmrFPLLwU5iawIEa1Z+JJuhsspaB3sGjYjBFAcetxVlXM47IRs1ZEs8oIdLDw== X-Received: by 2002:a17:90b:1e0f:b0:1e3:16bd:34e9 with SMTP id pg15-20020a17090b1e0f00b001e316bd34e9mr34499118pjb.63.1654634228667; Tue, 07 Jun 2022 13:37:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 66/71] linux-user/aarch64: Implement SME signal handling Date: Tue, 7 Jun 2022 13:33:01 -0700 Message-Id: <20220607203306.657998-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654639355531100001 Content-Type: text/plain; charset="utf-8" Set the SM bit in the SVE record on signal delivery, create the ZA record. Restore SM and ZA state according to the records present on return. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 162 +++++++++++++++++++++++++++++++++--- 1 file changed, 151 insertions(+), 11 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 22d0b8b4ec..1ad125d3d9 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -104,6 +104,22 @@ struct target_sve_context { =20 #define TARGET_SVE_SIG_FLAG_SM 1 =20 +#define TARGET_ZA_MAGIC 0x54366345 + +struct target_za_context { + struct target_aarch64_ctx head; + uint16_t vl; + uint16_t reserved[3]; + /* The actual ZA data immediately follows. */ +}; + +#define TARGET_ZA_SIG_REGS_OFFSET \ + QEMU_ALIGN_UP(sizeof(struct target_za_context), TARGET_SVE_VQ_BYTES) +#define TARGET_ZA_SIG_ZAV_OFFSET(VQ, N) \ + (TARGET_ZA_SIG_REGS_OFFSET + (VQ) * TARGET_SVE_VQ_BYTES * (N)) +#define TARGET_ZA_SIG_CONTEXT_SIZE(VQ) \ + TARGET_ZA_SIG_ZAV_OFFSET(VQ, VQ * TARGET_SVE_VQ_BYTES) + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -176,9 +192,9 @@ static void target_setup_end_record(struct target_aarch= 64_ctx *end) } =20 static void target_setup_sve_record(struct target_sve_context *sve, - CPUARMState *env, int vq, int size) + CPUARMState *env, int size) { - int i, j; + int i, j, vq =3D sme_vq(env); =20 memset(sve, 0, sizeof(*sve)); __put_user(TARGET_SVE_MAGIC, &sve->head.magic); @@ -207,6 +223,34 @@ static void target_setup_sve_record(struct target_sve_= context *sve, } } =20 +static void target_setup_za_record(struct target_za_context *za, + CPUARMState *env, int size) +{ + int vq =3D sme_vq(env); + int vl =3D vq * TARGET_SVE_VQ_BYTES; + int i, j; + + memset(za, 0, sizeof(*za)); + __put_user(TARGET_ZA_MAGIC, &za->head.magic); + __put_user(size, &za->head.size); + __put_user(vl, &za->vl); + + if (size =3D=3D TARGET_ZA_SIG_CONTEXT_SIZE(0)) { + return; + } + + /* + * Note that ZA vectors are stored as a byte stream, + * with each byte element at a subsequent address. + */ + for (i =3D 0; i < vl; ++i) { + uint64_t *z =3D (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i); + for (j =3D 0; j < vq * 2; ++j) { + __put_user_e(env->zarray[i].d[j], z + j, le); + } + } +} + static void target_restore_general_frame(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -252,16 +296,28 @@ static void target_restore_fpsimd_record(CPUARMState = *env, =20 static bool target_restore_sve_record(CPUARMState *env, struct target_sve_context *sve, - int size) + int size, int *svcr) { - int i, j, vl, vq; + int i, j, vl, vq, flags; + bool sm; =20 + /* ??? Kernel tests SVE && (!sm || SME); suggest (sm ? SME : SVE). */ if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) { return false; } =20 __get_user(vl, &sve->vl); - vq =3D sve_vq(env); + __get_user(flags, &sve->flags); + + sm =3D flags & TARGET_SVE_SIG_FLAG_SM; + if (sm) { + if (!cpu_isar_feature(aa64_sme, env_archcpu(env))) { + return false; + } + vq =3D sme_vq(env); + } else { + vq =3D sve_vq(env); + } =20 /* Reject mismatched VL. */ if (vl !=3D vq * TARGET_SVE_VQ_BYTES) { @@ -278,6 +334,8 @@ static bool target_restore_sve_record(CPUARMState *env, return false; } =20 + *svcr =3D FIELD_DP64(*svcr, SVCR, SM, sm); + /* * Note that SVE regs are stored as a byte stream, with each byte elem= ent * at a subsequent address. This corresponds to a little-endian load @@ -304,15 +362,57 @@ static bool target_restore_sve_record(CPUARMState *en= v, return true; } =20 +static bool target_restore_za_record(CPUARMState *env, + struct target_za_context *za, + int size, int *svcr) +{ + int i, j, vl, vq; + + if (!cpu_isar_feature(aa64_sme, env_archcpu(env))) { + return false; + } + + __get_user(vl, &za->vl); + vq =3D sme_vq(env); + + /* Reject mismatched VL. */ + if (vl !=3D vq * TARGET_SVE_VQ_BYTES) { + return false; + } + + /* Accept empty record -- used to clear PSTATE.ZA. */ + if (size <=3D TARGET_ZA_SIG_CONTEXT_SIZE(0)) { + return true; + } + + /* Reject non-empty but incomplete record. */ + if (size < TARGET_ZA_SIG_CONTEXT_SIZE(vq)) { + return false; + } + + *svcr =3D FIELD_DP64(*svcr, SVCR, ZA, 1); + + for (i =3D 0; i < vl; ++i) { + uint64_t *z =3D (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i); + for (j =3D 0; j < vq * 2; ++j) { + __get_user_e(env->zarray[i].d[j], z + j, le); + } + } + return true; +} + static int target_restore_sigframe(CPUARMState *env, struct target_rt_sigframe *sf) { struct target_aarch64_ctx *ctx, *extra =3D NULL; struct target_fpsimd_context *fpsimd =3D NULL; struct target_sve_context *sve =3D NULL; + struct target_za_context *za =3D NULL; uint64_t extra_datap =3D 0; bool used_extra =3D false; int sve_size =3D 0; + int za_size =3D 0; + int svcr =3D 0; =20 target_restore_general_frame(env, sf); =20 @@ -350,6 +450,14 @@ static int target_restore_sigframe(CPUARMState *env, sve_size =3D size; break; =20 + case TARGET_ZA_MAGIC: + if (za || size < sizeof(struct target_za_context)) { + goto err; + } + za =3D (struct target_za_context *)ctx; + za_size =3D size; + break; + case TARGET_EXTRA_MAGIC: if (extra || size !=3D sizeof(struct target_extra_context)) { goto err; @@ -381,9 +489,16 @@ static int target_restore_sigframe(CPUARMState *env, } =20 /* SVE data, if present, overwrites FPSIMD data. */ - if (sve && !target_restore_sve_record(env, sve, sve_size)) { + if (sve && !target_restore_sve_record(env, sve, sve_size, &svcr)) { goto err; } + if (za && !target_restore_za_record(env, za, za_size, &svcr)) { + goto err; + } + if (env->svcr !=3D svcr) { + env->svcr =3D svcr; + arm_rebuild_hflags(env); + } unlock_user(extra, extra_datap, 0); return 0; =20 @@ -451,7 +566,8 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, .total_size =3D offsetof(struct target_rt_sigframe, uc.tuc_mcontext.__reserved), }; - int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, vq =3D 0, sve_size =3D 0; + int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, za_ofs =3D 0; + int sve_size =3D 0, za_size =3D 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; abi_ulong frame_addr, return_addr; @@ -461,11 +577,20 @@ static void target_setup_frame(int usig, struct targe= t_sigaction *ka, &layout); =20 /* SVE state needs saving only if it exists. */ - if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { - vq =3D sve_vq(env); - sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); + if (cpu_isar_feature(aa64_sve, env_archcpu(env)) || + cpu_isar_feature(aa64_sme, env_archcpu(env))) { + sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(sve_vq(env)= ), 16); sve_ofs =3D alloc_sigframe_space(sve_size, &layout); } + if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { + /* ZA state needs saving only if it is enabled. */ + if (FIELD_EX64(env->svcr, SVCR, ZA)) { + za_size =3D TARGET_ZA_SIG_CONTEXT_SIZE(sme_vq(0)); + } else { + za_size =3D TARGET_ZA_SIG_CONTEXT_SIZE(0); + } + za_ofs =3D alloc_sigframe_space(za_size, &layout); + } =20 if (layout.extra_ofs) { /* Reserve space for the extra end marker. The standard end marker @@ -512,7 +637,10 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, target_setup_end_record((void *)frame + layout.extra_end_ofs); } if (sve_ofs) { - target_setup_sve_record((void *)frame + sve_ofs, env, vq, sve_size= ); + target_setup_sve_record((void *)frame + sve_ofs, env, sve_size); + } + if (za_ofs) { + target_setup_za_record((void *)frame + za_ofs, env, za_size); } =20 /* Set up the stack frame for unwinding. */ @@ -536,6 +664,18 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, env->btype =3D 2; } =20 + /* + * Invoke the signal handler with both SM and ZA disabled. + * When clearing SM, ResetSVEState, per SMSTOP. + */ + if (FIELD_EX64(env->svcr, SVCR, SM)) { + arm_reset_sve_state(env); + } + if (env->svcr) { + env->svcr =3D 0; + arm_rebuild_hflags(env); + } + if (info) { tswap_siginfo(&frame->info, info); env->xregs[1] =3D frame_addr + offsetof(struct target_rt_sigframe,= info); --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654639589; cv=none; d=zohomail.com; s=zohoarc; b=ZbvMlqKuCNr2lRZKREd3tsp7o1E0k5crdRB17aGaVJ1nTGllp9MNrKtbGPeMWcqjPFPnd6eBQRI80utyC66eV60nzTHMfUiLfi95qCLg0OEKDT5t6AiDBje7SteTIcUWiOoubMj/3K1axa4BcqomZN+X35eG2Ok3eQW/iBm3fco= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654639589; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=peylD0MqTkY6Ni4gfiTgUpLQJeWJHjooqBzEUJMAaO0=; b=Kf+/ydVHUdA0WMApNMGIzO6g/aBE0NNQRiVyG+8Fsg6dkosEF4uOXGAlrFK0Sc4ZUmc1yoAoiNKyOhrzUzE/ZdRqEDDdKZAG8f3Fx8t0CzlOrrB1jOfyF6TrTHbU4AkbTI+rg0Zui6HJp96mx2IHdxZyJPFZPBcroPjkunI791I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654639589875424.02579085059745; Tue, 7 Jun 2022 15:06:29 -0700 (PDT) Received: from localhost ([::1]:37118 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyhLI-0000Nz-MB for importer@patchew.org; Tue, 07 Jun 2022 18:06:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36588) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfx2-0007iS-Gw for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:20 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:39740) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfwv-0008N7-2M for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:20 -0400 Received: by mail-pf1-x429.google.com with SMTP id y196so16509810pfb.6 for ; Tue, 07 Jun 2022 13:37:12 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.37.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:37:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=peylD0MqTkY6Ni4gfiTgUpLQJeWJHjooqBzEUJMAaO0=; b=gOAiS0rVWkLDFTHVeBQJPQVlA2a66QQH93VP/ML0CbYCn8So8/2uYpQMM09PA3WaPj OXS2rhagBQWVdp5iUWYeWzRam9s5hPKpDJlM5TXzotAk3kNy5Q0sND16BL0iXbHVlx17 +1q4on+V9ep0SVsr03rRAevS9ZS4DDTH2vjWd5qetOV45S7TBCUSonMUN7qER2FXuJPT IQ0d2S5ZgObeDVRV8WNXodnWbwiKV9xTStfEYXXf3XwbtpapgY+07NjdyHfCjUFVMO+H xfOKy1XlxxZhtQ5ihTnNv3gC0dXOWeX5F6yi/1eMi+Kme/OJnocW41Jd6K3jvH/8pyis oo3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=peylD0MqTkY6Ni4gfiTgUpLQJeWJHjooqBzEUJMAaO0=; b=MbkDsGJmowT2VfC8p9fDBiJmszsD3dYnE5mNILfVF4REQbT/C8A53wLjKToyVHYZsL QAA4TH3veKNYv8tnh6IQ+0Ec3T8b/Z1igUh4jxnCR74p1jNtyuPbozeXmUhVX7xL+pY+ C7dPfR9g/jjPcGTvorCo1uPbqVWpSsJyEaKpREqg0zYIiHjDHM6cFkQQpHVB8xW+hWgs DLwH4Z5a0F6NtLycodV+E6ZIMOov5Ne4RM/qAXvmMjOqJ3taOyQ0xs8kzUFWUxF1M1lV ZTmHCQkwIXYb4CkoItNdDIgFLgn+Urq4g00ZGR55H6EKvTMfZswBJTFo6j5ZpuCpP5F7 htDw== X-Gm-Message-State: AOAM530uJSmBXtOFUg4XmPBxZldSMZyxAsUQV2P+2cRBmOlKNfVszgj1 9SNsCXWqlJgtu7UiOtRKO/+dM7o4lFBm1w== X-Google-Smtp-Source: ABdhPJzYdT9P3+p1MBa9i2vjSu+0xf7WFyjiAmFWPIj/eo3CJ0Pe22xat6LattqjvIXJ317VXFz70A== X-Received: by 2002:a63:1f55:0:b0:3fd:41c5:b53a with SMTP id q21-20020a631f55000000b003fd41c5b53amr18274454pgm.441.1654634229656; Tue, 07 Jun 2022 13:37:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 67/71] linux-user: Rename sve prctls Date: Tue, 7 Jun 2022 13:33:02 -0700 Message-Id: <20220607203306.657998-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654639590361100001 Content-Type: text/plain; charset="utf-8" Add "sve" to the sve prctl functions, to distinguish them from the coming "sme" prctls with similar names. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 8 ++++---- linux-user/syscall.c | 12 ++++++------ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_= prctl.h index 1d440ffbea..40481e6663 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -6,7 +6,7 @@ #ifndef AARCH64_TARGET_PRCTL_H #define AARCH64_TARGET_PRCTL_H =20 -static abi_long do_prctl_get_vl(CPUArchState *env) +static abi_long do_prctl_sve_get_vl(CPUArchState *env) { ARMCPU *cpu =3D env_archcpu(env); if (cpu_isar_feature(aa64_sve, cpu)) { @@ -14,9 +14,9 @@ static abi_long do_prctl_get_vl(CPUArchState *env) } return -TARGET_EINVAL; } -#define do_prctl_get_vl do_prctl_get_vl +#define do_prctl_sve_get_vl do_prctl_sve_get_vl =20 -static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2) +static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2) { /* * We cannot support either PR_SVE_SET_VL_ONEXEC or PR_SVE_VL_INHERIT. @@ -47,7 +47,7 @@ static abi_long do_prctl_set_vl(CPUArchState *env, abi_lo= ng arg2) } return -TARGET_EINVAL; } -#define do_prctl_set_vl do_prctl_set_vl +#define do_prctl_sve_set_vl do_prctl_sve_set_vl =20 static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) { diff --git a/linux-user/syscall.c b/linux-user/syscall.c index f55cdebee5..a7f41ef0ac 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6365,11 +6365,11 @@ static abi_long do_prctl_inval1(CPUArchState *env, = abi_long arg2) #ifndef do_prctl_set_fp_mode #define do_prctl_set_fp_mode do_prctl_inval1 #endif -#ifndef do_prctl_get_vl -#define do_prctl_get_vl do_prctl_inval0 +#ifndef do_prctl_sve_get_vl +#define do_prctl_sve_get_vl do_prctl_inval0 #endif -#ifndef do_prctl_set_vl -#define do_prctl_set_vl do_prctl_inval1 +#ifndef do_prctl_sve_set_vl +#define do_prctl_sve_set_vl do_prctl_inval1 #endif #ifndef do_prctl_reset_keys #define do_prctl_reset_keys do_prctl_inval1 @@ -6434,9 +6434,9 @@ static abi_long do_prctl(CPUArchState *env, abi_long = option, abi_long arg2, case PR_SET_FP_MODE: return do_prctl_set_fp_mode(env, arg2); case PR_SVE_GET_VL: - return do_prctl_get_vl(env); + return do_prctl_sve_get_vl(env); case PR_SVE_SET_VL: - return do_prctl_set_vl(env, arg2); + return do_prctl_sve_set_vl(env, arg2); case PR_PAC_RESET_KEYS: if (arg3 || arg4 || arg5) { return -TARGET_EINVAL; --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654638563; cv=none; d=zohomail.com; s=zohoarc; b=EoG3Mp4HcnJCEuT95G9LbtVw0UpIdnqKcWNDvOBXUoDiSwSysEwrTl1Kyw1tM/X7Zc7JkYEoDEmaQKRv0jTkcwBKCvcK5iuY6PO6lOahgbNBilxvLvNBm5I+hxJihaibn823wk2Nrf+Lctv90Git60gam8QmN9TnZIBjobBMWBk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654638563; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=E7DCQA7E2hAFRFgfvTFqXzlLXs1UhLAZLgu67MB30tY=; b=NFkHVNOFnt5cHAacj6DFJwJCfQ+77ycPhCX1M8fMb8CtwKETAh2/AVfZNfcvas3Nt+gZJP2rWe8JBR2RSka6Qcas/gcbI7SRGUowqnNvlpxCO4HdDocWLPyWyci7OgRt1vm8j9qf+1ps/Nc9dEmbDfE6tPGkV1AxtK35TWB/eaQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654638563741589.8748265427178; Tue, 7 Jun 2022 14:49:23 -0700 (PDT) Received: from localhost ([::1]:33910 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyh4k-0003W2-BZ for importer@patchew.org; Tue, 07 Jun 2022 17:49:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36516) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfx1-0007bp-1U for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:19 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:37660) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfwt-0008O1-OY for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:18 -0400 Received: by mail-pl1-x633.google.com with SMTP id t2so15809308pld.4 for ; Tue, 07 Jun 2022 13:37:11 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.37.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:37:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E7DCQA7E2hAFRFgfvTFqXzlLXs1UhLAZLgu67MB30tY=; b=O7653sdsd6y4tvW4Dxc9xiT2b4myVtNemCW+AxSt/jkCT53nY/+Bn7YTQalxGc0a4j qGoN7fAzpg3/bkAbKGk7yner+UlAozz48wUrpkDtJBLGHWtZT2aYUcGFmIHQWmLw1MRx h4pKRfGpqL1ieWKf3LeB7IGiRJ2Ky17Zn2Z7319Li0R+4eIKT4EB6cXUCo1EEEwrOBZX reF8tec9/UFRlil4qNFis+fibngQz/+gc+j1z8ou6rsnLOQerN5SH6MSf7DzMS7Zyl+q 9r+3XWTiRuUCJRH22jl6ulIgzT9Ik8hQFomCmmXwDhled0+s3v2GriyiInHd1+NZkQmC 72eQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E7DCQA7E2hAFRFgfvTFqXzlLXs1UhLAZLgu67MB30tY=; b=27ByhInCbMOUHE6he6PJN30UzgGdoDma1+ZP6fGw6SmOo/sjgiwt5+27PTUZSuW4f5 tdXG700iq1Msbtult62e8xod+VeQFmt8lSWmI622HISYiRas+slRF4v+jE/C4yeBsl7x sGtQ3qqo8ruzRSgG1ThUOvdqd7kUlaLwQK1+4WujPijoozDVn9v0b/VhjbGI9A7Yqdrp xJkCXevRwYNQZuw1LfsK/6juZYz2ncu9iBtwFimJJ8ZuglT0r1BsTZnm8K1wnhzXeUta V8BsE6WekfXYy3mKC/w3JXXFATpFb7Zq+fs1uNs3nTY+GcNnqO9OeeMjWgAM2X4mDeY0 mWsQ== X-Gm-Message-State: AOAM531uiz4t1Jx14lpkfPV0zXy5KXT2E4061RdtOfwzFPBah0FvX9ti XRFZhF2ZHGmFxVe8SIixbf1/YwQVth0yiw== X-Google-Smtp-Source: ABdhPJxKnTF+K7ecWerJPmhpP6t/YzZSwngxjQ+p2bzxeubwcAoai2rHg6Cp2vTmy8+C6PeIoH61lQ== X-Received: by 2002:a17:902:d481:b0:167:770b:67c with SMTP id c1-20020a170902d48100b00167770b067cmr13569253plg.77.1654634230508; Tue, 07 Jun 2022 13:37:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 68/71] linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL Date: Tue, 7 Jun 2022 13:33:03 -0700 Message-Id: <20220607203306.657998-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654638565307100001 Content-Type: text/plain; charset="utf-8" These prctl set the Streaming SVE vector length, which may be completely different from the Normal SVE vector length. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 48 +++++++++++++++++++++++++++++++ linux-user/syscall.c | 16 +++++++++++ 2 files changed, 64 insertions(+) diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_= prctl.h index 40481e6663..f8f8f88992 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -10,6 +10,7 @@ static abi_long do_prctl_sve_get_vl(CPUArchState *env) { ARMCPU *cpu =3D env_archcpu(env); if (cpu_isar_feature(aa64_sve, cpu)) { + /* PSTATE.SM is always unset on syscall entry. */ return sve_vq(env) * 16; } return -TARGET_EINVAL; @@ -27,6 +28,7 @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, ab= i_long arg2) && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { uint32_t vq, old_vq; =20 + /* PSTATE.SM is always unset on syscall entry. */ old_vq =3D sve_vq(env); =20 /* @@ -49,6 +51,52 @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, a= bi_long arg2) } #define do_prctl_sve_set_vl do_prctl_sve_set_vl =20 +static abi_long do_prctl_sme_get_vl(CPUArchState *env) +{ + ARMCPU *cpu =3D env_archcpu(env); + if (cpu_isar_feature(aa64_sme, cpu)) { + return sme_vq(env) * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_sme_get_vl do_prctl_sme_get_vl + +static abi_long do_prctl_sme_set_vl(CPUArchState *env, abi_long arg2) +{ + /* + * We cannot support either PR_SME_SET_VL_ONEXEC or PR_SME_VL_INHERIT. + * Note the kernel definition of sve_vl_valid allows for VQ=3D512, + * i.e. VL=3D8192, even though the architectural maximum is VQ=3D16. + */ + if (cpu_isar_feature(aa64_sme, env_archcpu(env)) + && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { + int vq, old_vq; + + old_vq =3D sme_vq(env); + + /* + * Bound the value of vq, so that we know that it fits into + * the 4-bit field in SMCR_EL1. Because PSTATE.SM is cleared + * on syscall entry, we are not modifying the current SVE + * vector length. + */ + vq =3D MAX(arg2 / 16, 1); + vq =3D MIN(vq, 16); + env->vfp.smcr_el[1] =3D + FIELD_DP64(env->vfp.smcr_el[1], SMCR, LEN, vq - 1); + vq =3D sme_vq(env); + + if (old_vq !=3D vq) { + /* PSTATE.ZA state is cleared on any change to VQ. */ + env->svcr =3D FIELD_DP64(env->svcr, SVCR, ZA, 0); + arm_rebuild_hflags(env); + } + return vq * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_sme_set_vl do_prctl_sme_set_vl + static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) { ARMCPU *cpu =3D env_archcpu(env); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index a7f41ef0ac..e8d6e20b85 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6346,6 +6346,12 @@ abi_long do_arch_prctl(CPUX86State *env, int code, a= bi_ulong addr) #ifndef PR_SET_SYSCALL_USER_DISPATCH # define PR_SET_SYSCALL_USER_DISPATCH 59 #endif +#ifndef PR_SME_SET_VL +# define PR_SME_SET_VL 63 +# define PR_SME_GET_VL 64 +# define PR_SME_VL_LEN_MASK 0xffff +# define PR_SME_VL_INHERIT (1 << 17) +#endif =20 #include "target_prctl.h" =20 @@ -6386,6 +6392,12 @@ static abi_long do_prctl_inval1(CPUArchState *env, a= bi_long arg2) #ifndef do_prctl_set_unalign #define do_prctl_set_unalign do_prctl_inval1 #endif +#ifndef do_prctl_sme_get_vl +#define do_prctl_sme_get_vl do_prctl_inval0 +#endif +#ifndef do_prctl_sme_set_vl +#define do_prctl_sme_set_vl do_prctl_inval1 +#endif =20 static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5) @@ -6437,6 +6449,10 @@ static abi_long do_prctl(CPUArchState *env, abi_long= option, abi_long arg2, return do_prctl_sve_get_vl(env); case PR_SVE_SET_VL: return do_prctl_sve_set_vl(env, arg2); + case PR_SME_GET_VL: + return do_prctl_sme_get_vl(env); + case PR_SME_SET_VL: + return do_prctl_sme_set_vl(env, arg2); case PR_PAC_RESET_KEYS: if (arg3 || arg4 || arg5) { return -TARGET_EINVAL; --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654639646; cv=none; d=zohomail.com; s=zohoarc; b=gTembQ09khdKZZ5efXT5p/93fbGSzeclatv1hzKFzNegozLpP83Fcca9osilSRHsJdqyyMGi5b5DaYLVqoqNdSN+K2MnVBxyXDrKm+VvGuBxUBmatxwy2PFcDW5L0EhDkV3tes+/klVMddsSujvRHu1l3blLXls3PLJlOVbAZEA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654639646; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8ss3EaTY1TKvXRQ5t3puVtJ4SylwysppKIF75i7g6zo=; b=ebIOfy1vkWjCA5L+tZTKZ4EgpFRKGiR2NvY+3JFXl/2qR2wsUmcR0DZbotZOmp9LnuO2z/zoWxkYW8B5dxAVq4MBVK4TFEo4bSPTRIR6uHSv2KYldjVHp83CduUv5gfrg1vmeycv/mnA1OztklK5zLASpXdKsBaE8FFxliXtTko= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654639646522394.77540643712746; Tue, 7 Jun 2022 15:07:26 -0700 (PDT) Received: from localhost ([::1]:38480 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyhMD-0001LJ-Fx for importer@patchew.org; Tue, 07 Jun 2022 18:07:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36578) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfx2-0007hY-9W for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:20 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:44683) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfwu-0008IQ-5R for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:19 -0400 Received: by mail-pl1-x62e.google.com with SMTP id h1so15783303plf.11 for ; Tue, 07 Jun 2022 13:37:11 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.37.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:37:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8ss3EaTY1TKvXRQ5t3puVtJ4SylwysppKIF75i7g6zo=; b=HoAqVqWW+Wh81IE7Dp8FnwFSqUG7cgPPRTxVSCo7lKL7aKKceTvMGUAMK8E51eALOV Tga7x5rRLYKLGcQDWXRSK8X1A4nDUdeVbMSF/ssdfeidJq71Qq88E0XjcWFGSI08QQ7b fPNjOnmDBB4k26NC947+iWl3OOlDV0ISDT1oNtFHcu5gzEvQ2zgUUfERZFjyc3igSfEo mKwmVk7YDw1vDv4yg2JfXfu3c5KIDoTVvplKXcyOYeHu2yfpw69313GcMQvmP2VUNrYJ SeN/icEIT89X8gPY+E4PhJYmWzRDwMQc7Tn9ikOSIW0s1ExqcaFx5y5R5UwSjk7eRwtW MGpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8ss3EaTY1TKvXRQ5t3puVtJ4SylwysppKIF75i7g6zo=; b=TVN44ZnYBZtfS0Usl/4dHiL99s+SVlfRi5TpZUwot2CJ8FiQILfgF7J716xe7IdPwo jh8TW8VOA+KOyegpiHCOkEAE+wWk5aryPAdQ70LW2LhSIboOliPQJMEu+vdE98EM/SGK wLCHNVTg4hZzcs9Vr0iIOineFAOmsf96SGrderuAvKiFLvzRrBdLZvBwfqMXeCqdenLy qiRvlPFGwAaPFVNgG9m9whCyTQpHyd8d4YvLjN4NVLSBSMuAQWVy0YYunCtARPkV+iob 2S7OXR7BAq0L4ebPJ7pL6V5cNIwCV/0KTVc1lVkl1fyVwJX/4c82o9BQ5nwaTQg4QfbM i85Q== X-Gm-Message-State: AOAM532VVMX1ArwDr5fG5kfuAqEXnzfYgidUb7urOP1W+MzcNDV0O67D 0soCVp1QpDi/HzJMCQVAcSe8YsxC3oOyVg== X-Google-Smtp-Source: ABdhPJxlWuoJdWiPrZTAo6pMPQh2y9rJClr05c5ijEOZaQ/FhW8Q0Qj8xuJh/JDM9R2wRRHmYIWbrg== X-Received: by 2002:a17:902:ecc9:b0:163:e41c:bf12 with SMTP id a9-20020a170902ecc900b00163e41cbf12mr30359335plh.164.1654634231437; Tue, 07 Jun 2022 13:37:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 69/71] target/arm: Only set ZEN in reset if SVE present Date: Tue, 7 Jun 2022 13:33:04 -0700 Message-Id: <20220607203306.657998-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654639648681100001 Content-Type: text/plain; charset="utf-8" There's no reason to set CPACR_EL1.ZEN if SVE disabled. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 75295a14a3..5cb9f9f02c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -203,11 +203,10 @@ static void arm_cpu_reset(DeviceState *dev) /* and to the FP/Neon instructions */ env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, CPACR_EL1, FPEN, 3); - /* and to the SVE instructions */ - env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, - CPACR_EL1, ZEN, 3); - /* with reasonable vector length */ + /* and to the SVE instructions, with default vector length */ if (cpu_isar_feature(aa64_sve, cpu)) { + env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, + CPACR_EL1, ZEN, 3); env->vfp.zcr_el[1] =3D cpu->sve_default_vq - 1; } /* --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654638235; cv=none; d=zohomail.com; s=zohoarc; b=B/EvzG9tX6HxdoBukrXtzjuDuC6jdzzxE5Zbf9DL4aHY5A/s2ypGmRlC3cxw2Fjyb/nRgTxW4TDzkQAv+vYRArq6IZPBL4FhXfDe793wqMKioEbLRgFOqn1YcI5RX/Yq/v1Dg9IdnlNByP06l537vC0oibSmBuTu35MztKDfPC4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654638235; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gRUKfNIQaiiNP0vvAyDKnRSVA5VX9NVJiBVrOsiCdko=; b=MAHcyzvGxQ4jNVJk2aEPQ5B6upjIs+gRJddf/MK4I6c64isb9ibT56mwVfQKN0Qz5YbLs7uLexxx6eRo4+UGcwbSfwZWijbrfhed+UlRbd+ygkxudEGj1c2yrBrAS8N3l/C7gqQ46fNMYnNHnigrXsDol7VfdRZEGQ9tMFOjiHk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165463823594252.84445815143283; Tue, 7 Jun 2022 14:43:55 -0700 (PDT) Received: from localhost ([::1]:46958 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nygzS-0001bW-KH for importer@patchew.org; Tue, 07 Jun 2022 17:43:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36608) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfx2-0007jf-TM for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:20 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:42537) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfwv-0008DU-5e for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:20 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d22so15786850plr.9 for ; Tue, 07 Jun 2022 13:37:12 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.37.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:37:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gRUKfNIQaiiNP0vvAyDKnRSVA5VX9NVJiBVrOsiCdko=; b=zADOhNo9A4xia2NWmohK53fkDMn9otAZ+9BOR2nwpwHn530Pf8cRakwQO06goIg3Vk mBDFwuyxtdtjve9WZK0s+Wu6VG+5s7j677zMgv2jNPhRAfm32DuEFeG0cR7rdXDSTxIH F6k4jCXLi10KA+bTZXKhjmM1/y5zSqezMJKEB7lJG8DbiEv2oZ6QSqvB7hra68SWjnyj aCbnsPjJEaDUTk/1MLZWVCzsNRs1qsVNEdP1VMeWPAxjvrzf/k8d5t4tJIjZoHeROclj DXlZ7NHsqsOO4sj0fFN+dZSR7dQMB7bD4MlzJKDNQrgqqjg3bVMNj30XvWWO3xpqrgJt wibA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gRUKfNIQaiiNP0vvAyDKnRSVA5VX9NVJiBVrOsiCdko=; b=DFwNcwIKZBob5X25QGY5NpLUo+T04aefspJ+V1qOiSGpkOtlZt7fBX7Q2bN17lrE/Q XY1lafM/GwhzDNbi4X89yZYPTiYIO2xQIUFwJTx27WqAOgrPRnpQXgWa6S7Buc+3khoo 75Jt4I5aO8tvle745T8ajhwdaq4cKuRySUGurUdcBFRoyta1cgk04NPYzYlaeavNUxEy b4p2GETVYpixdoN8T3Ko32j9kOcrNu/vekTAdK8z5iLvyaWcWOpu+dY09NXmMIvvidL+ PICVLNv3HTwgRgaAGn6SdlBx1Lz73lRsEyfncwsy0wJ2klqGHXUutSYHRuHVjfollGJC +HCA== X-Gm-Message-State: AOAM533HqEwkX/TyKN/JSAVYpWKdg3WBlIsqhHrzvHsp4rNjvP8BLKoD 9QK3tedAXMW7M3bMRoQ1aQYcPc4KRdE8dg== X-Google-Smtp-Source: ABdhPJypCmXWOrdJLgE5AksW0rGIa2c3ezGVwUOgW3DdCFU8tUOYnrdYxC+VFggcuQyjbDXx/J2XRw== X-Received: by 2002:a17:903:2312:b0:163:daf7:83a9 with SMTP id d18-20020a170903231200b00163daf783a9mr30791150plh.160.1654634232387; Tue, 07 Jun 2022 13:37:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 70/71] target/arm: Enable SME for user-only Date: Tue, 7 Jun 2022 13:33:05 -0700 Message-Id: <20220607203306.657998-71-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654638236911100001 Content-Type: text/plain; charset="utf-8" Enable SME, TPIDR2_EL0, and FA64 if supported by the cpu. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5cb9f9f02c..13b008547e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -209,6 +209,17 @@ static void arm_cpu_reset(DeviceState *dev) CPACR_EL1, ZEN, 3); env->vfp.zcr_el[1] =3D cpu->sve_default_vq - 1; } + /* and for SME instructions, with default vector length, and TPIDR= 2 */ + if (cpu_isar_feature(aa64_sme, cpu)) { + env->cp15.sctlr_el[1] |=3D SCTLR_EnTP2; + env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, + CPACR_EL1, SMEN, 3); + env->vfp.smcr_el[1] =3D cpu->sme_default_vq - 1; + if (cpu_isar_feature(aa64_sme_fa64, cpu)) { + env->vfp.smcr_el[1] =3D FIELD_DP64(env->vfp.smcr_el[1], + SMCR, FA64, 1); + } + } /* * Enable 48-bit address space (TODO: take reserved_va into accoun= t). * Enable TBI0 but not TBI1. --=20 2.34.1 From nobody Tue Feb 10 00:41:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654638444; cv=none; d=zohomail.com; s=zohoarc; b=b/s/4ImnEAtP+ATNQ37x5KRkgTjG9r6pgPC3h8QqqFLe510TaKjBXf+iGe8ncIRG+eQnXTZzDYvzDVH8uFgk9jrNcCA2oZwiRlpfxQRvebDKThQ3jrhc6hxrjCjbSjts8101FEd/4K/7I1DNpROxXk9Vh3Oe3t1wucbS8udezSY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654638444; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DykCJozY64Fe8oG2Osy4GtewqpVyxda/M4nkZEjhEDk=; b=huBlttq9g07qjmagOwVsFDaObMa+fOO0X+jLYRNsaZmy+BDs9EdCFKvqTaEci9dHG8G4d8mXO6QteyMSjJOP/VDEQslRaeBBGcwOSmOSmqLMmqr3tEtq5aLgPCl+RUOOSCuiON22QwH4vFIyxPGhU1w110qYnzAVkdcIl4exOxE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654638444846997.2792002394657; Tue, 7 Jun 2022 14:47:24 -0700 (PDT) Received: from localhost ([::1]:55582 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nyh2p-0007U1-Pc for importer@patchew.org; Tue, 07 Jun 2022 17:47:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36604) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nyfx2-0007jZ-Sv for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:20 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:46741) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nyfww-0008EU-1P for qemu-devel@nongnu.org; Tue, 07 Jun 2022 16:37:20 -0400 Received: by mail-pl1-x633.google.com with SMTP id d13so141128plh.13 for ; Tue, 07 Jun 2022 13:37:13 -0700 (PDT) Received: from stoup.. ([2602:ae:1547:e101:3cf2:c634:5b19:25f6]) by smtp.gmail.com with ESMTPSA id s18-20020aa78d52000000b0050dc76281fdsm13235645pfe.215.2022.06.07.13.37.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jun 2022 13:37:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DykCJozY64Fe8oG2Osy4GtewqpVyxda/M4nkZEjhEDk=; b=Z0m5xHf+DRD4UJ0qaaSDvgJGpGOcx4m/xuR7GjwfhLP3Ixln8ajd27uiWKElFu1s2A R3i3Ydfaxr4u29M99ZCits9L6RRFmuZZtmVT61SBpO/cLrG4RRQkIAXCfZfxpAH/D3MO YAqpxxdBt8ojd83qEaXtaE5fsfJhuhbH6ut4EqdKkQolSTVQIB6Ph39bZMTu+ec9EcdX 8sBQ4rhV6voSLxWVUzQqs7LQLSXfxYOCPq/sOPJibTuYU/7hh2AOb0x6w8xmX6A5655M qwtkXTdXbm36sj6imtHixjp7nf1yKzARgFBEYYHhBcamS7WLJG/oTocerDIf8e0FORjO ysnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DykCJozY64Fe8oG2Osy4GtewqpVyxda/M4nkZEjhEDk=; b=KzUe6oiE7tY7YEtBdESXTTEWRosBQQJMWkJpfl1Wvzu20TXYxmWydIinJH7Z7cO75N rVFXMfVAAsSYpNEP5KkPXV5C7kjQbq5WymU7Um6OwV0qJ8jy/ggXMb/Lhoap7OojqD7h R6+SQu2TDC9YMKRgnqE3gl5uHU3arAQNtAXofZjVbwBP91mx6+RnXYognbPD4WKiTPn3 OHrjhckyeOlgbgvwOpcqE+vjbTylEDRbULU6nAuwd+muErIz+pI5S3SnuzMV/y3jFCDc 9wUJy7qsHWYKS5tzFkRvmCGFJOIZGOz73fZ7myPiES7Y96OYKAjVryTpBOjc7st8cdes fBSg== X-Gm-Message-State: AOAM530QTbwZbdaydgeOKXx707riSfKMsQCGbdhaAmjKdNwwqngSXeH+ EJFHVfL2mKkoTfKsP3fuC/OryGMJ7fUkTQ== X-Google-Smtp-Source: ABdhPJwTkzJnOhhhQNXmfRDN87MB6UMipr91qDJnsb4uMsEV6TD3bbt1ct8Lh8TJKsMOnRNptBv5Bg== X-Received: by 2002:a17:90a:ae14:b0:1e0:51fa:5182 with SMTP id t20-20020a17090aae1400b001e051fa5182mr68270983pjq.60.1654634233259; Tue, 07 Jun 2022 13:37:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH v2 71/71] linux-user/aarch64: Add SME related hwcap entries Date: Tue, 7 Jun 2022 13:33:06 -0700 Message-Id: <20220607203306.657998-72-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220607203306.657998-1-richard.henderson@linaro.org> References: <20220607203306.657998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654638446196100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- linux-user/elfload.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f7eae357f4..8135960305 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -601,6 +601,18 @@ enum { ARM_HWCAP2_A64_RNG =3D 1 << 16, ARM_HWCAP2_A64_BTI =3D 1 << 17, ARM_HWCAP2_A64_MTE =3D 1 << 18, + ARM_HWCAP2_A64_ECV =3D 1 << 19, + ARM_HWCAP2_A64_AFP =3D 1 << 20, + ARM_HWCAP2_A64_RPRES =3D 1 << 21, + ARM_HWCAP2_A64_MTE3 =3D 1 << 22, + ARM_HWCAP2_A64_SME =3D 1 << 23, + ARM_HWCAP2_A64_SME_I16I64 =3D 1 << 24, + ARM_HWCAP2_A64_SME_F64F64 =3D 1 << 25, + ARM_HWCAP2_A64_SME_I8I32 =3D 1 << 26, + ARM_HWCAP2_A64_SME_F16F32 =3D 1 << 27, + ARM_HWCAP2_A64_SME_B16F32 =3D 1 << 28, + ARM_HWCAP2_A64_SME_F32F32 =3D 1 << 29, + ARM_HWCAP2_A64_SME_FA64 =3D 1 << 30, }; =20 #define ELF_HWCAP get_elf_hwcap() @@ -670,6 +682,14 @@ static uint32_t get_elf_hwcap2(void) GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG); GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI); GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE); + GET_FEATURE_ID(aa64_sme, (ARM_HWCAP2_A64_SME | + ARM_HWCAP2_A64_SME_F32F32 | + ARM_HWCAP2_A64_SME_B16F32 | + ARM_HWCAP2_A64_SME_F16F32 | + ARM_HWCAP2_A64_SME_I8I32)); + GET_FEATURE_ID(aa64_sme_f64f64, ARM_HWCAP2_A64_SME_F64F64); + GET_FEATURE_ID(aa64_sme_i16i64, ARM_HWCAP2_A64_SME_I16I64); + GET_FEATURE_ID(aa64_sme_fa64, ARM_HWCAP2_A64_SME_FA64); =20 return hwcaps; } --=20 2.34.1