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Date: Mon, 6 Jun 2022 16:14:48 -0700 Message-Id: <20220606231450.448443-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220606231450.448443-1-richard.henderson@linaro.org> References: <20220606231450.448443-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654559803457100001 Content-Type: text/plain; charset="utf-8" From: Xiaojuan Yang Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao Reviewed-by: Richard Henderson Message-Id: <20220606124333.2060567-42-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson --- configs/targets/loongarch64-softmmu.mak | 1 + target/loongarch/internals.h | 4 ++ target/loongarch/cpu.c | 9 +++ target/loongarch/gdbstub.c | 81 +++++++++++++++++++++++++ MAINTAINERS | 1 + gdb-xml/loongarch-base64.xml | 44 ++++++++++++++ gdb-xml/loongarch-fpu64.xml | 57 +++++++++++++++++ target/loongarch/meson.build | 1 + 8 files changed, 198 insertions(+) create mode 100644 target/loongarch/gdbstub.c create mode 100644 gdb-xml/loongarch-base64.xml create mode 100644 gdb-xml/loongarch-fpu64.xml diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loon= garch64-softmmu.mak index 666154022f..7bc06c850c 100644 --- a/configs/targets/loongarch64-softmmu.mak +++ b/configs/targets/loongarch64-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=3Dloongarch64 TARGET_BASE_ARCH=3Dloongarch TARGET_SUPPORTS_MTTCG=3Dy +TARGET_XML_FILES=3D gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu64.x= ml diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index a410c41c37..9d50fbdd81 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -49,4 +49,8 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, =20 hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 +int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int= n); +int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n= ); +void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs); + #endif diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 3b7d6289d2..4c8f96bc3a 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -487,6 +487,8 @@ static void loongarch_cpu_realizefn(DeviceState *dev, E= rror **errp) return; } =20 + loongarch_cpu_register_gdb_regs_for_features(cs); + cpu_reset(cs); qemu_init_vcpu(cs); =20 @@ -640,6 +642,13 @@ static void loongarch_cpu_class_init(ObjectClass *c, v= oid *data) dc->vmsd =3D &vmstate_loongarch_cpu; cc->sysemu_ops =3D &loongarch_sysemu_ops; cc->disas_set_info =3D loongarch_cpu_disas_set_info; + cc->gdb_read_register =3D loongarch_cpu_gdb_read_register; + cc->gdb_write_register =3D loongarch_cpu_gdb_write_register; + cc->disas_set_info =3D loongarch_cpu_disas_set_info; + cc->gdb_num_core_regs =3D 34; + cc->gdb_core_xml_file =3D "loongarch-base64.xml"; + cc->gdb_stop_before_watchpoint =3D true; + #ifdef CONFIG_TCG cc->tcg_ops =3D &loongarch_tcg_ops; #endif diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c new file mode 100644 index 0000000000..0c48834201 --- /dev/null +++ b/target/loongarch/gdbstub.c @@ -0,0 +1,81 @@ +/* + * LOONGARCH gdb server stub + * + * Copyright (c) 2021 Loongson Technology Corporation Limited + * + * SPDX-License-Identifier: LGPL-2.1+ + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/gdbstub.h" + +int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int= n) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + CPULoongArchState *env =3D &cpu->env; + + if (0 <=3D n && n < 32) { + return gdb_get_regl(mem_buf, env->gpr[n]); + } else if (n =3D=3D 32) { + return gdb_get_regl(mem_buf, env->pc); + } else if (n =3D=3D 33) { + return gdb_get_regl(mem_buf, env->badaddr); + } + return 0; +} + +int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + CPULoongArchState *env =3D &cpu->env; + target_ulong tmp =3D ldtul_p(mem_buf); + int length =3D 0; + + if (0 <=3D n && n < 32) { + env->gpr[n] =3D tmp; + length =3D sizeof(target_ulong); + } else if (n =3D=3D 32) { + env->pc =3D tmp; + length =3D sizeof(target_ulong); + } + return length; +} + +static int loongarch_gdb_get_fpu(CPULoongArchState *env, + GByteArray *mem_buf, int n) +{ + if (0 <=3D n && n < 32) { + return gdb_get_reg64(mem_buf, env->fpr[n]); + } else if (32 <=3D n && n < 40) { + return gdb_get_reg8(mem_buf, env->cf[n - 32]); + } else if (n =3D=3D 40) { + return gdb_get_reg32(mem_buf, env->fcsr0); + } + return 0; +} + +static int loongarch_gdb_set_fpu(CPULoongArchState *env, + uint8_t *mem_buf, int n) +{ + int length =3D 0; + + if (0 <=3D n && n < 32) { + env->fpr[n] =3D ldq_p(mem_buf); + length =3D 8; + } else if (32 <=3D n && n < 40) { + env->cf[n - 32] =3D ldub_p(mem_buf); + length =3D 1; + } else if (n =3D=3D 40) { + env->fcsr0 =3D ldl_p(mem_buf); + length =3D 4; + } + return length; +} + +void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs) +{ + gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_= fpu, + 41, "loongarch-fpu64.xml", 0); +} diff --git a/MAINTAINERS b/MAINTAINERS index e8938db694..954fb95218 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1137,6 +1137,7 @@ F: include/hw/intc/loongarch_*.h F: hw/intc/loongarch_*.c F: include/hw/pci-host/ls7a.h F: hw/rtc/ls7a_rtc.c +F: gdb-xml/loongarch*.xml =20 M68K Machines ------------- diff --git a/gdb-xml/loongarch-base64.xml b/gdb-xml/loongarch-base64.xml new file mode 100644 index 0000000000..4962bdbd28 --- /dev/null +++ b/gdb-xml/loongarch-base64.xml @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/loongarch-fpu64.xml b/gdb-xml/loongarch-fpu64.xml new file mode 100644 index 0000000000..e52cf89fbc --- /dev/null +++ b/gdb-xml/loongarch-fpu64.xml @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build index 74e5f3b2a7..6376f9e84b 100644 --- a/target/loongarch/meson.build +++ b/target/loongarch/meson.build @@ -11,6 +11,7 @@ loongarch_tcg_ss.add(files( 'fpu_helper.c', 'op_helper.c', 'translate.c', + 'gdbstub.c', )) loongarch_tcg_ss.add(zlib) =20 --=20 2.34.1