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charset="utf-8" From: Xiaojuan Yang Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao Reviewed-by: Richard Henderson Message-Id: <20220606124333.2060567-23-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson --- target/loongarch/cpu-param.h | 2 +- target/loongarch/cpu.h | 51 ++++++ target/loongarch/internals.h | 9 + target/loongarch/cpu.c | 24 +++ target/loongarch/machine.c | 17 ++ target/loongarch/tlb_helper.c | 315 ++++++++++++++++++++++++++++++++++ target/loongarch/meson.build | 1 + 7 files changed, 418 insertions(+), 1 deletion(-) create mode 100644 target/loongarch/tlb_helper.c diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index 9a769b67e0..414d8fff46 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -13,6 +13,6 @@ #define TARGET_VIRT_ADDR_SPACE_BITS 48 =20 #define TARGET_PAGE_BITS 14 -#define NB_MMU_MODES 4 +#define NB_MMU_MODES 5 =20 #endif diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 3ec978f47c..e0415d8929 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -184,6 +184,26 @@ FIELD(CSR_CRMD, WE, 9, 1) extern const char * const regnames[32]; extern const char * const fregnames[32]; =20 +#define LOONGARCH_STLB 2048 /* 2048 STLB */ +#define LOONGARCH_MTLB 64 /* 64 MTLB */ +#define LOONGARCH_TLB_MAX (LOONGARCH_STLB + LOONGARCH_MTLB) + +/* + * define the ASID PS E VPPN field of TLB + */ +FIELD(TLB_MISC, E, 0, 1) +FIELD(TLB_MISC, ASID, 1, 10) +FIELD(TLB_MISC, VPPN, 13, 35) +FIELD(TLB_MISC, PS, 48, 6) + +struct LoongArchTLB { + uint64_t tlb_misc; + /* Fields corresponding to CSR_TLBELO0/1 */ + uint64_t tlb_entry0; + uint64_t tlb_entry1; +}; +typedef struct LoongArchTLB LoongArchTLB; + typedef struct CPUArchState { uint64_t gpr[32]; uint64_t pc; @@ -256,6 +276,8 @@ typedef struct CPUArchState { uint64_t CSR_DBG; uint64_t CSR_DERA; uint64_t CSR_DSAVE; + + LoongArchTLB tlb[LOONGARCH_TLB_MAX]; } CPULoongArchState; =20 /** @@ -294,6 +316,35 @@ struct LoongArchCPUClass { DeviceReset parent_reset; }; =20 +/* + * LoongArch CPUs has 4 privilege levels. + * 0 for kernel mode, 3 for user mode. + * Define an extra index for DA(direct addressing) mode. + */ +#define MMU_KERNEL_IDX 0 +#define MMU_USER_IDX 3 +#define MMU_DA_IDX 4 + +static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) +{ + uint8_t pg =3D FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG); + + if (!pg) { + return MMU_DA_IDX; + } + return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); +} + +static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, + target_ulong *pc, + target_ulong *cs_base, + uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D cpu_mmu_index(env, false); +} + void loongarch_cpu_list(void); =20 #define cpu_list loongarch_cpu_list diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index 39960dee27..2fed768653 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -13,6 +13,9 @@ #define FCMP_UN 0b0100 /* unordered */ #define FCMP_GT 0b1000 /* fp0 > fp1 */ =20 +#define TARGET_PHYS_MASK MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS) +#define TARGET_VIRT_MASK MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS) + void loongarch_translate_init(void); =20 void loongarch_cpu_dump_state(CPUState *cpu, FILE *f, int flags); @@ -27,4 +30,10 @@ void restore_fp_status(CPULoongArchState *env); =20 extern const VMStateDescription vmstate_loongarch_cpu; =20 +bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + +hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + #endif diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index aa0e1f9167..9a5cabbf4c 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -303,6 +303,21 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) } } =20 + qemu_fprintf(f, "CRMD=3D%016" PRIx64 "\n", env->CSR_CRMD); + qemu_fprintf(f, "PRMD=3D%016" PRIx64 "\n", env->CSR_PRMD); + qemu_fprintf(f, "EUEN=3D%016" PRIx64 "\n", env->CSR_EUEN); + qemu_fprintf(f, "ESTAT=3D%016" PRIx64 "\n", env->CSR_ESTAT); + qemu_fprintf(f, "ERA=3D%016" PRIx64 "\n", env->CSR_ERA); + qemu_fprintf(f, "BADV=3D%016" PRIx64 "\n", env->CSR_BADV); + qemu_fprintf(f, "BADI=3D%016" PRIx64 "\n", env->CSR_BADI); + qemu_fprintf(f, "EENTRY=3D%016" PRIx64 "\n", env->CSR_EENTRY); + qemu_fprintf(f, "PRCFG1=3D%016" PRIx64 ", PRCFG2=3D%016" PRIx64 "," + " PRCFG3=3D%016" PRIx64 "\n", + env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3); + qemu_fprintf(f, "TLBRENTRY=3D%016" PRIx64 "\n", env->CSR_TLBRENTRY); + qemu_fprintf(f, "TLBRBADV=3D%016" PRIx64 "\n", env->CSR_TLBRBADV); + qemu_fprintf(f, "TLBRERA=3D%016" PRIx64 "\n", env->CSR_TLBRERA); + /* fpr */ if (flags & CPU_DUMP_FPU) { for (i =3D 0; i < 32; i++) { @@ -320,9 +335,17 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) static struct TCGCPUOps loongarch_tcg_ops =3D { .initialize =3D loongarch_translate_init, .synchronize_from_tb =3D loongarch_cpu_synchronize_from_tb, + + .tlb_fill =3D loongarch_cpu_tlb_fill, }; #endif /* CONFIG_TCG */ =20 +#include "hw/core/sysemu-cpu-ops.h" + +static const struct SysemuCPUOps loongarch_sysemu_ops =3D { + .get_phys_page_debug =3D loongarch_cpu_get_phys_page_debug, +}; + static void loongarch_cpu_class_init(ObjectClass *c, void *data) { LoongArchCPUClass *lacc =3D LOONGARCH_CPU_CLASS(c); @@ -337,6 +360,7 @@ static void loongarch_cpu_class_init(ObjectClass *c, vo= id *data) cc->dump_state =3D loongarch_cpu_dump_state; cc->set_pc =3D loongarch_cpu_set_pc; dc->vmsd =3D &vmstate_loongarch_cpu; + cc->sysemu_ops =3D &loongarch_sysemu_ops; cc->disas_set_info =3D loongarch_cpu_disas_set_info; #ifdef CONFIG_TCG cc->tcg_ops =3D &loongarch_tcg_ops; diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c index 49a06fdf28..b1e523ea72 100644 --- a/target/loongarch/machine.c +++ b/target/loongarch/machine.c @@ -8,6 +8,20 @@ #include "qemu/osdep.h" #include "cpu.h" #include "migration/cpu.h" +#include "internals.h" + +/* TLB state */ +const VMStateDescription vmstate_tlb =3D { + .name =3D "cpu/tlb", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(tlb_misc, LoongArchTLB), + VMSTATE_UINT64(tlb_entry0, LoongArchTLB), + VMSTATE_UINT64(tlb_entry1, LoongArchTLB), + VMSTATE_END_OF_LIST() + } +}; =20 /* LoongArch CPU state */ =20 @@ -79,6 +93,9 @@ const VMStateDescription vmstate_loongarch_cpu =3D { VMSTATE_UINT64(env.CSR_DBG, LoongArchCPU), VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU), VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU), + /* TLB */ + VMSTATE_STRUCT_ARRAY(env.tlb, LoongArchCPU, LOONGARCH_TLB_MAX, + 0, vmstate_tlb, LoongArchTLB), =20 VMSTATE_END_OF_LIST() }, diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c new file mode 100644 index 0000000000..fad8bc7746 --- /dev/null +++ b/target/loongarch/tlb_helper.c @@ -0,0 +1,315 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU LoongArch TLB helpers + * + * Copyright (c) 2021 Loongson Technology Corporation Limited + * + */ + +#include "qemu/osdep.h" + +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "exec/cpu_ldst.h" +#include "exec/log.h" +#include "cpu-csr.h" + +enum { + TLBRET_MATCH =3D 0, + TLBRET_BADADDR =3D 1, + TLBRET_NOMATCH =3D 2, + TLBRET_INVALID =3D 3, + TLBRET_DIRTY =3D 4, + TLBRET_RI =3D 5, + TLBRET_XI =3D 6, + TLBRET_PE =3D 7, +}; + +static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physica= l, + int *prot, target_ulong address, + int access_type, int index, int mmu_idx) +{ + LoongArchTLB *tlb =3D &env->tlb[index]; + uint64_t plv =3D mmu_idx; + uint64_t tlb_entry, tlb_ppn; + uint8_t tlb_ps, n, tlb_v, tlb_d, tlb_plv, tlb_nx, tlb_nr, tlb_rplv; + + if (index >=3D LOONGARCH_STLB) { + tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); + } else { + tlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); + } + n =3D (address >> tlb_ps) & 0x1;/* Odd or even */ + + tlb_entry =3D n ? tlb->tlb_entry1 : tlb->tlb_entry0; + tlb_v =3D FIELD_EX64(tlb_entry, TLBENTRY, V); + tlb_d =3D FIELD_EX64(tlb_entry, TLBENTRY, D); + tlb_plv =3D FIELD_EX64(tlb_entry, TLBENTRY, PLV); + tlb_ppn =3D FIELD_EX64(tlb_entry, TLBENTRY, PPN); + tlb_nx =3D FIELD_EX64(tlb_entry, TLBENTRY, NX); + tlb_nr =3D FIELD_EX64(tlb_entry, TLBENTRY, NR); + tlb_rplv =3D FIELD_EX64(tlb_entry, TLBENTRY, RPLV); + + /* Check access rights */ + if (!tlb_v) { + return TLBRET_INVALID; + } + + if (access_type =3D=3D MMU_INST_FETCH && tlb_nx) { + return TLBRET_XI; + } + + if (access_type =3D=3D MMU_DATA_LOAD && tlb_nr) { + return TLBRET_RI; + } + + if (((tlb_rplv =3D=3D 0) && (plv > tlb_plv)) || + ((tlb_rplv =3D=3D 1) && (plv !=3D tlb_plv))) { + return TLBRET_PE; + } + + if ((access_type =3D=3D MMU_DATA_STORE) && !tlb_d) { + return TLBRET_DIRTY; + } + + /* + * tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15] + * need adjust. + */ + *physical =3D (tlb_ppn << R_TLBENTRY_PPN_SHIFT) | + (address & MAKE_64BIT_MASK(0, tlb_ps)); + *prot =3D PAGE_READ; + if (tlb_d) { + *prot |=3D PAGE_WRITE; + } + if (!tlb_nx) { + *prot |=3D PAGE_EXEC; + } + return TLBRET_MATCH; +} + +/* + * One tlb entry holds an adjacent odd/even pair, the vpn is the + * content of the virtual page number divided by 2. So the + * compare vpn is bit[47:15] for 16KiB page. while the vppn + * field in tlb entry contains bit[47:13], so need adjust. + * virt_vpn =3D vaddr[47:13] + */ +static bool loongarch_tlb_search(CPULoongArchState *env, target_ulong vadd= r, + int *index) +{ + LoongArchTLB *tlb; + uint16_t csr_asid, tlb_asid, stlb_idx; + uint8_t tlb_e, tlb_ps, tlb_g, stlb_ps; + int i, compare_shift; + uint64_t vpn, tlb_vppn; + + csr_asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); + stlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); + vpn =3D (vaddr & TARGET_VIRT_MASK) >> (stlb_ps + 1); + stlb_idx =3D vpn & 0xff; /* VA[25:15] <=3D=3D> TLBIDX.index for 16KiB = Page */ + compare_shift =3D stlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT; + + /* Search STLB */ + for (i =3D 0; i < 8; ++i) { + tlb =3D &env->tlb[i * 256 + stlb_idx]; + tlb_e =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, E); + if (tlb_e) { + tlb_vppn =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN); + tlb_asid =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID); + tlb_g =3D FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G); + + if ((tlb_g =3D=3D 1 || tlb_asid =3D=3D csr_asid) && + (vpn =3D=3D (tlb_vppn >> compare_shift))) { + *index =3D i * 256 + stlb_idx; + return true; + } + } + } + + /* Search MTLB */ + for (i =3D LOONGARCH_STLB; i < LOONGARCH_TLB_MAX; ++i) { + tlb =3D &env->tlb[i]; + tlb_e =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, E); + if (tlb_e) { + tlb_vppn =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN); + tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); + tlb_asid =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID); + tlb_g =3D FIELD_EX64(tlb->tlb_entry0, TLBENTRY, G); + compare_shift =3D tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT; + vpn =3D (vaddr & TARGET_VIRT_MASK) >> (tlb_ps + 1); + if ((tlb_g =3D=3D 1 || tlb_asid =3D=3D csr_asid) && + (vpn =3D=3D (tlb_vppn >> compare_shift))) { + *index =3D i; + return true; + } + } + } + return false; +} + +static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical, + int *prot, target_ulong address, + MMUAccessType access_type, int mmu_idx) +{ + int index, match; + + match =3D loongarch_tlb_search(env, address, &index); + if (match) { + return loongarch_map_tlb_entry(env, physical, prot, + address, access_type, index, mmu_id= x); + } + + return TLBRET_NOMATCH; +} + +static int get_physical_address(CPULoongArchState *env, hwaddr *physical, + int *prot, target_ulong address, + MMUAccessType access_type, int mmu_idx) +{ + int user_mode =3D mmu_idx =3D=3D MMU_USER_IDX; + int kernel_mode =3D mmu_idx =3D=3D MMU_KERNEL_IDX; + uint32_t plv, base_c, base_v; + int64_t addr_high; + uint8_t da =3D FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA); + uint8_t pg =3D FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG); + + /* Check PG and DA */ + if (da & !pg) { + *physical =3D address & TARGET_PHYS_MASK; + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return TLBRET_MATCH; + } + + plv =3D kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT); + base_v =3D address >> TARGET_VIRT_ADDR_SPACE_BITS; + /* Check direct map window */ + for (int i =3D 0; i < 4; i++) { + base_c =3D env->CSR_DMW[i] >> TARGET_VIRT_ADDR_SPACE_BITS; + if ((plv & env->CSR_DMW[i]) && (base_c =3D=3D base_v)) { + *physical =3D dmw_va2pa(address); + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return TLBRET_MATCH; + } + } + + /* Check valid extension */ + addr_high =3D sextract64(address, TARGET_VIRT_ADDR_SPACE_BITS, 16); + if (!(addr_high =3D=3D 0 || addr_high =3D=3D -1)) { + return TLBRET_BADADDR; + } + + /* Mapped address */ + return loongarch_map_address(env, physical, prot, address, + access_type, mmu_idx); +} + +hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + CPULoongArchState *env =3D &cpu->env; + hwaddr phys_addr; + int prot; + + if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, + cpu_mmu_index(env, false)) !=3D 0) { + return -1; + } + return phys_addr; +} + +static void raise_mmu_exception(CPULoongArchState *env, target_ulong addre= ss, + MMUAccessType access_type, int tlb_error) +{ + CPUState *cs =3D env_cpu(env); + + switch (tlb_error) { + default: + case TLBRET_BADADDR: + cs->exception_index =3D EXCCODE_ADEM; + break; + case TLBRET_NOMATCH: + /* No TLB match for a mapped address */ + if (access_type =3D=3D MMU_DATA_LOAD) { + cs->exception_index =3D EXCCODE_PIL; + } else if (access_type =3D=3D MMU_DATA_STORE) { + cs->exception_index =3D EXCCODE_PIS; + } else if (access_type =3D=3D MMU_INST_FETCH) { + cs->exception_index =3D EXCCODE_PIF; + } + env->CSR_TLBRERA =3D FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, IST= LBR, 1); + break; + case TLBRET_INVALID: + /* TLB match with no valid bit */ + if (access_type =3D=3D MMU_DATA_LOAD) { + cs->exception_index =3D EXCCODE_PIL; + } else if (access_type =3D=3D MMU_DATA_STORE) { + cs->exception_index =3D EXCCODE_PIS; + } else if (access_type =3D=3D MMU_INST_FETCH) { + cs->exception_index =3D EXCCODE_PIF; + } + break; + case TLBRET_DIRTY: + /* TLB match but 'D' bit is cleared */ + cs->exception_index =3D EXCCODE_PME; + break; + case TLBRET_XI: + /* Execute-Inhibit Exception */ + cs->exception_index =3D EXCCODE_PNX; + break; + case TLBRET_RI: + /* Read-Inhibit Exception */ + cs->exception_index =3D EXCCODE_PNR; + break; + case TLBRET_PE: + /* Privileged Exception */ + cs->exception_index =3D EXCCODE_PPI; + break; + } + + if (tlb_error =3D=3D TLBRET_NOMATCH) { + env->CSR_TLBRBADV =3D address; + env->CSR_TLBREHI =3D FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, VPP= N, + extract64(address, 13, 35)); + } else { + if (!FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { + env->CSR_BADV =3D address; + } + env->CSR_TLBEHI =3D address & (TARGET_PAGE_MASK << 1); + } +} + +bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + CPULoongArchState *env =3D &cpu->env; + hwaddr physical; + int prot; + int ret =3D TLBRET_BADADDR; + + /* Data access */ + ret =3D get_physical_address(env, &physical, &prot, address, + access_type, mmu_idx); + + if (ret =3D=3D TLBRET_MATCH) { + tlb_set_page(cs, address & TARGET_PAGE_MASK, + physical & TARGET_PAGE_MASK, prot, + mmu_idx, TARGET_PAGE_SIZE); + qemu_log_mask(CPU_LOG_MMU, + "%s address=3D%" VADDR_PRIx " physical " TARGET_FMT_= plx + " prot %d\n", __func__, address, physical, prot); + return true; + } else { + qemu_log_mask(CPU_LOG_MMU, + "%s address=3D%" VADDR_PRIx " ret %d\n", __func__, a= ddress, + ret); + } + if (probe) { + return false; + } + raise_mmu_exception(env, address, access_type, ret); + cpu_loop_exit_restore(cs, retaddr); +} diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build index 103f36ee15..435cc75999 100644 --- a/target/loongarch/meson.build +++ b/target/loongarch/meson.build @@ -17,6 +17,7 @@ loongarch_tcg_ss.add(zlib) loongarch_softmmu_ss =3D ss.source_set() loongarch_softmmu_ss.add(files( 'machine.c', + 'tlb_helper.c', )) =20 loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss]) --=20 2.34.1