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Mon, 06 Jun 2022 07:36:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzTxARHUTbfpSvwoyk/WeBgrZltKzSHeERSGpawBpcOKiL2ZvYhhz37H4IwfLhvpa1qAbmdyw== X-Received: by 2002:a5d:62c7:0:b0:216:fa41:2f81 with SMTP id o7-20020a5d62c7000000b00216fa412f81mr10006566wrv.249.1654526211914; Mon, 06 Jun 2022 07:36:51 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Yang Zhong Subject: [PULL 03/29] target/i386: Fix wrong count setting Date: Mon, 6 Jun 2022 16:36:18 +0200 Message-Id: <20220606143644.1151112-4-pbonzini@redhat.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220606143644.1151112-1-pbonzini@redhat.com> References: <20220606143644.1151112-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1654526685397100001 Content-Type: text/plain; charset="utf-8" From: Yang Zhong The previous patch used wrong count setting with index value, which got wro= ng value from CPUID(EAX=3D12,ECX=3D0):EAX. So the SGX1 instruction can't be ex= posed to VM and the SGX decice can't work in VM. Fixes: d19d6ffa0710 ("target/i386: introduce helper to access supported CPU= ID") Signed-off-by: Yang Zhong Message-Id: <20220530131834.1222801-1-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index bb6a5dd498..9fdfec9d8b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5559,7 +5559,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, * supports. Features can be further restricted by userspace, but= not * made more permissive. */ - x86_cpu_get_supported_cpuid(0x12, index, eax, ebx, ecx, edx); + x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); =20 if (count =3D=3D 0) { *eax &=3D env->features[FEAT_SGX_12_0_EAX]; --=20 2.36.1