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Mon, 06 Jun 2022 07:36:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzv9/cGwHN2A+ficzzDjm0CXYh8OesQAaD5UB6hoHSCv47nJxhKHWjl9HeXyIDp8T4FgUETxQ== X-Received: by 2002:a5d:47c1:0:b0:217:1bfc:56c2 with SMTP id o1-20020a5d47c1000000b002171bfc56c2mr9179949wrc.336.1654526207953; Mon, 06 Jun 2022 07:36:47 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Stephen Michael Jothen Subject: [PULL 01/29] target/i386/tcg: Fix masking of real-mode addresses with A20 bit Date: Mon, 6 Jun 2022 16:36:16 +0200 Message-Id: <20220606143644.1151112-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220606143644.1151112-1-pbonzini@redhat.com> References: <20220606143644.1151112-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1654526989001100001 Content-Type: text/plain; charset="utf-8" From: Stephen Michael Jothen The correct A20 masking is done if paging is enabled (protected mode) but it seems to have been forgotten in real mode. For example from the AMD64 APM V= ol. 2 section 1.2.4: > If the sum of the segment base and effective address carries over into bi= t 20, > that bit can be optionally truncated to mimic the 20-bit address wrapping= of the > 8086 processor by using the A20M# input signal to mask the A20 address bi= t. Most BIOSes will enable the A20 line on boot, but I found by disabling the = A20 line afterwards, the correct wrapping wasn't taking place. `handle_mmu_fault' in target/i386/tcg/sysemu/excp_helper.c seems to be the = culprit. In real mode, it fills the TLB with the raw unmasked address. However, for = the protected mode, the `mmu_translate' function does the correct A20 masking. The fix then should be to just apply the A20 mask in the first branch of th= e if statement. Signed-off-by: Stephen Michael Jothen Message-Id: Signed-off-by: Paolo Bonzini --- target/i386/tcg/sysemu/excp_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index e1b6d88683..48feba7e75 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -359,6 +359,7 @@ static int handle_mmu_fault(CPUState *cs, vaddr addr, i= nt size, CPUX86State *env =3D &cpu->env; int error_code =3D PG_ERROR_OK; int pg_mode, prot, page_size; + int32_t a20_mask; hwaddr paddr; hwaddr vaddr; =20 @@ -368,7 +369,8 @@ static int handle_mmu_fault(CPUState *cs, vaddr addr, i= nt size, #endif =20 if (!(env->cr[0] & CR0_PG_MASK)) { - paddr =3D addr; + a20_mask =3D x86_get_a20_mask(env); + paddr =3D addr & a20_mask; #ifdef TARGET_X86_64 if (!(env->hflags & HF_LMA_MASK)) { /* Without long mode we can only address 32bits in real mode */ --=20 2.36.1